TWI574375B - Integrated circuit device - Google Patents

Description

Integrated circuit device

The present invention relates to an integrated circuit device, and more particularly to a capacitive arrangement of an integrated circuit device having an inductive component on a wafer.

Spiral inductors have been widely used in RF/high speed integrated circuit design. Generally, in order to avoid affecting the inductance performance and generating unwanted crosstalk, electronic components are not allowed to be disposed in the occupied area of the inductor to reduce eddy current loss and coupling. However, since the inductor occupies a considerable area of the germanium substrate, it causes a bottleneck in the manufacturing cost of the wafer.

Therefore, there is a need in the art for an improved integrated circuit arrangement.

An embodiment of the present invention provides an integrated circuit device. The integrated circuit device includes a substrate. A first capacitor is disposed on the substrate. A first metal pattern is coupled to the first capacitor. An electrode, a second metal pattern coupled to the second electrode of the first capacitor; a third metal pattern disposed over the first metal pattern and the second metal pattern, covering the first capacitor, the first a metal pattern and the second metal pattern, wherein the third metal pattern is electrically grounded; an inductor is disposed on the third gold Above the pattern.

200‧‧‧Substrate

201‧‧‧ surface

202‧‧‧ Well Area

204‧‧‧ gate oxide layer

206‧‧‧ gate

208‧‧‧ gate structure

210‧‧‧ source

212‧‧‧汲polar

214, 216, 218‧‧‧ oxide layer

250‧‧‧Inductance

252‧‧‧ inner circle

254‧‧‧ outer ring section

256‧‧‧Connected section

300‧‧‧Metal pattern

300-1, 300-2‧‧‧Metal connection

302-1, 302-2, 304-1, 304-2‧‧‧ metal patterns

310, 312, 314‧‧‧ metal layers

350‧‧‧Interconnection structure

400a‧‧‧Metal-oxide-semiconductor capacitor

400b~400d‧‧‧Metal-oxide-metal capacitor

500, 500a~500d‧‧‧ integrated circuit device

600‧‧‧Local

C1~C8‧‧‧ equivalent capacitance

S‧‧‧ spacing

M1‧‧‧ first metal layer

M2‧‧‧ second metal layer

M3‧‧‧ third metal layer

M4‧‧‧4th metal layer

M5‧‧‧ fifth metal layer

M6‧‧‧6th metal layer

M7‧‧‧ seventh metal layer

1 is a top plan view of an integrated circuit device according to some embodiments of the present invention.

2 is a partial enlarged view of the first diagram, showing a ground shielding metal pattern disposed under the inductance element, and a layout diagram of a metal pattern disposed under the ground shielding metal pattern for coupling the electrodes of the capacitor.

3 is a cross-sectional view taken along line C-C' of FIG. 2, showing a cross-sectional view of a plurality of metal-oxide-semiconductor capacitors disposed under different grounded shielding metal patterns in accordance with an embodiment of the present invention.

Figure 4 is a cross-sectional view taken along line D-D' of Figure 2, showing a cross-sectional view of a plurality of metal-oxide-semiconductor capacitors disposed under the same grounded shielding metal pattern in accordance with another embodiment of the present invention.

Figure 5 is a cross-sectional view taken along line C-C' of Figure 2, showing a cross-sectional view of a plurality of metal-oxide-metal capacitors disposed under different grounded shielding metal patterns in accordance with another embodiment of the present invention.

Figure 6 is a cross-sectional view taken along line C-C' of Figure 2, showing a cross-sectional view of a plurality of metal-oxide-metal capacitors disposed under different grounded shielding metal patterns in accordance with yet another embodiment of the present invention.

Figure 7 is a cross-sectional view taken along line C-C' of Figure 2, showing several metal-oxide-semiconductor capacitors and metal-oxides disposed under different grounded shielding metal patterns in accordance with other embodiments of the present invention. Schematic diagram of the metal capacitor.

In order to make the objects, features, and advantages of the present invention more comprehensible, the detailed description of the embodiments and the accompanying drawings. The present specification provides various embodiments to illustrate the technical features of various embodiments of the present invention. The arrangement of the various elements in the embodiments is for illustrative purposes and is not intended to limit the invention. The overlapping portions of the drawings in the embodiments are for the purpose of simplifying the description and are not intended to be related to the different embodiments.

Embodiments of the present invention provide an integrated circuit device that is related to a configuration of a capacitor. The integrated circuit device is provided with a capacitor element in a region between an on-chip inductor and a substrate, and the capacitor element is provided with a ground shield metal pattern for shielding the wafer. The ground of the upper inductive component is directly under the metal pattern. In some other embodiments of the invention, the capacitor can be used as a power net de-coupling capacitor.

1 is a top plan view of an integrated circuit device 500 according to some embodiments of the present invention. In some embodiments of the present invention, the main components of the integrated circuit device 500 include a substrate 200, an inductor 250, a plurality of metal patterns 300, and at least one capacitor (not shown in FIG. 1). The figure illustrates. As shown in FIG. 1, the inductor 250 and the metal pattern 300 are partial components of an interconnect structure (including a plurality of metal layers and a plurality of dielectric layers that are alternately stacked) above the substrate 200. In addition, in order to clearly show the positional relationship between the substrate 200, the inductor 250, and the metal pattern 300, the metal layers and dielectric layers of different layers disposed between the inductor 250 and the metal pattern 300 in the interconnect structure are not Shown.

In an embodiment of the invention, the substrate 200 can be a germanium substrate A germanium (SiGe) substrate, a bulk semiconductor substrate, a strained semiconductor substrate, a compound semiconductor substrate, an insulating layer overlying SOI substrate, or other commonly used semiconductor substrates. Additionally, in embodiments of the invention, p-type or n-type impurities may be implanted into the substrate 200 to change the conductivity type for design purposes. In some embodiments of the invention, the substrate 200 may include one or more insulators extending from a top surface of the substrate 200 into a portion of the substrate 200. The above-described insulator may include a niobium partial oxide (LOCOS) or a shallow trench spacer (STI) for defining an active region of the substrate 200.

In an embodiment of the invention, the inductor 250 is disposed above the substrate 200. The inductor 250 is formed using the topmost metal layer (Mtop) of the interconnect structure, or is formed using the topmost metal layer (Mtop) and the underlying metal layer (Mtop-1). As shown in FIG. 1, the inductor 250 can include an inner ring portion 252 and an outer ring portion 254 that are substantially parallel and concentric with each other. The inner ring portion 252 and the outer ring portion 254 of the inductor 250 may be connected to each other by a connecting portion 256, and the shapes of the inner ring portion 252 and the outer ring portion 254 may include a circle, a quadrangle or a polygon. When the inner ring portion 252 and the outer ring portion 254 of the inductor 250 are formed using the topmost metal layer (Mtop) of the interconnect structure, the connecting portion 256 may be a via plug that connects the topmost metal layer of the interconnect structure. Formed with the next metal layer (Mtop-1) on the top layer. When the inner ring portion 252 and the outer ring portion 254 of the inductor 250 are respectively formed by the topmost metal layer (Mtop) of the interconnect structure and the lower metal layer (Mtop-1) of the top layer, the connecting portion 256 may be formed by an interconnect structure. The formation is formed by a via plug connecting the topmost metal layer and the underlying metal layer.

In an embodiment of the invention, the metal pattern 300 is disposed on the inductor Directly below 250, and the metal pattern 300 and the inductor 250 respectively belong to different metal layers of the interconnect structure, that is, occupy different layers of metal layers of the interconnect structure. In some other embodiments of the invention, the metal pattern 300 and the inductor 250 are separated by at least two or more metal layers. For example, when the interconnect structure is formed using seven metal layers, the inductor 250 may be formed using the seventh metal layer (M7) and/or the sixth metal layer (M6), and the metal pattern 300 may utilize the second A layer metal layer (M2), a third metal layer (M3) or a fourth metal layer (M4) are formed. In some embodiments of the invention, the metal pattern 300 acts as a ground shield metal pattern for the inductor 250. As shown in FIG. 1 , the area occupied by the plurality of metal patterns 300 is larger than the area occupied by the inductor 250 , and thus the boundary of the occupied area of the inductor 250 may be located in the area occupied by the plurality of metal patterns 300 . Within the boundaries.

2 is an enlarged schematic view of a portion 600 of FIG. 1 showing a ground shielding metal pattern 300 disposed under the inductance element, and a layout of a metal pattern disposed under the ground shielding metal pattern for coupling the electrodes of the capacitor. . As shown in FIG. 2, the plurality of metal patterns 300 are composed of a plurality of metal strips having substantially the same shape. Referring to FIGS. 1 and 2 simultaneously, the metal pattern 300 can be divided into four regions along the diagonal lines A1-A1' and A2-A2' passing through the opposite corner portions of the inductor 250, and the metal patterns 300 in the respective regions are mutually connected. They are spaced apart to reduce the coupling effect between the metal pattern 300 and the corner portion of the inductor 250. Further, the metal patterns 300 in the respective regions are arranged in parallel at the same pitch S. In addition, two adjacent metal patterns 300 respectively located in adjacent regions are disposed perpendicular to each other and are spaced apart from each other by the same pitch S. Therefore, the metal patterns 300 located in two mutually opposing regions are not connected. In an embodiment of the invention, the metal pattern 300 can be borrowed The metal connecting portions 300-1, 300-2 located at the same metal layer are connected to each other and coupled to a ground node or a ground node of a power network. In other words, the metal pattern 300 is electrically grounded. The metal connection portions 300-1, 300-2 may have an annular portion extending substantially along an outer boundary of the plurality of metal patterns 300 to be connected to the plurality of metal patterns 300. The metal pattern 300 can electrically isolate the inductor 250 from the substrate 200 to avoid eddy current loss, and reduce unwanted crosstalk between the inductor 250 and other electronic components disposed on the substrate 200. And coupling (coupling) and other phenomena.

For those skilled in the art, the ground shielding metal pattern 300 is slightly changed according to the teachings of the embodiments of the present invention, so that the ground shielding metal pattern is cut in the vertical direction of the eddy current generated by the magnetic field induction of the inductor 250. Effectively reduce the influence of eddy current and improve the quality factor of the inductor 250.

Next, a schematic cross-sectional view of an integrated circuit device 500a according to an embodiment of the present invention will be described using Figs. The integrated circuit device 500a includes a metal-oxide-semiconductor capacitor (hereinafter referred to as MOS capacitor) 400a provided directly under the inductor and the ground shielding metal pattern (metal pattern 300). Fig. 3 is a schematic cross-sectional view taken along line C-C' of Fig. 2, and Fig. 4 is a schematic cross-sectional view taken along line D-D' of Fig. 2. Moreover, the cross-sectional view of FIG. 3 is a schematic cross-sectional view showing a plurality of MOS capacitors 400a disposed under different ground shielding metal patterns, and FIG. 4 is a view showing the number of the same grounding shielding metal patterns according to another embodiment of the present invention. A schematic cross-sectional view of a MOS capacitor 400a. In order to clearly show the inductance of the integrated circuit device 500a in the interconnect structure, the ground shielding metal pattern, the layer relationship of the MOS capacitor electrode wiring, and the layer of the MOS capacitor 400a and the substrate 200 The relationship is added to the different layer metal layers (including the inductor 250) above the metal pattern 300 (grounding mask metal pattern) in Figures 3 through 4, and the position of the interconnect structure 350 is indicated.

As shown in FIGS. 3 and 4, in an embodiment of the present invention, the MOS capacitor 400a is disposed on the p-type substrate 200 and directly under the metal pattern 300. The MOS capacitor 400a includes a well region 202, a gate structure 208, a source 210, and a drain 212. The well region 202 extends from a surface 201 of the substrate 200 into a portion of the substrate 200, and the well region 202 is doped with a p-type material. In some embodiments of the invention, well region 202 may be electrically floating. The gate structure 208 of the MOS capacitor 400a is disposed on the well region 202 and includes a gate oxide layer 204 and a gate 206 on the gate oxide layer 204. The source 210 and the drain 212 are formed on the well region 202, respectively, and extend from a surface 201 of the substrate 200 into a portion of the substrate 200. Source 210 and drain 212 are located on opposite sides of gate structure 208. Source 210 and drain 212 are doped with an n-type material. In some embodiments of the invention, the gate structure 208 acts as an electrode of the MOS capacitor 400a, and the source 210 and the drain 212 together serve as the other electrode of the MOS capacitor 400a.

In conjunction with the description of the above embodiments, another embodiment of the present invention is disposed on the substrate 200 by a metal oxide semiconductor varactor (MOS Varactor) or a p-type MOS capacitor, and is located on the metal pattern 300. Just below, the same technical effect can be achieved.

In the conventional semiconductor process technology, an insulating region is disposed between different types of well regions via an STI (shallow trench isolation) process to avoid leakage currents between adjacent but different types of well regions. On the other hand, the conventional semiconductor process technology forms a well region through ion implantation and diffusion processes, but is limited to half. Guided process technology, it is not easy to control the uniformity of ion implantation concentration in the well area, especially at the edge of the well area, the ion implantation concentration is higher than that of other areas in the well area, so that the formation at the edge of the well area The characteristics of the transistor are different from those of other regions formed in the well region, which is also referred to as the well proximity effect. To reduce the effects of well proximity effects and optimize layout space utilization, conventional techniques configure multiple transistors of the same type into the same well region.

Referring again to FIG. 3, the boundaries of the well regions 202 of the different MOS capacitors 400a disposed under the different ground shielding metal patterns (metal patterns 300) may be aligned with the boundaries of the metal patterns 300 or outside the boundaries of the metal patterns 300, respectively. It should be noted that the well regions 202 of different MOS capacitors 400a under different ground shielding metal patterns (metal patterns 300) are separated from each other without interconnection to ensure that the grounding shielding effect of the metal pattern 300 on the MOS capacitor 400a is not affected. . In addition, as shown in FIG. 3, the extending direction of the gate 206, the source 210, and the drain 212 of the MOS capacitor 400a located directly under each of the metal patterns 300 may be substantially parallel to the extending direction of the metal pattern 300. It should be noted that the inductor 250 is viewed in the direction in which the substrate is projected, the p-type well region 202 is covered by the metal pattern 300, and the substrate 200 is located in the region not covered by the metal pattern 300.

Referring to FIG. 4 again, in another embodiment of the present invention, the extending direction of the gate 206, the source 210, and the drain 212 of each MOS capacitor 400a may be substantially perpendicular to the extending direction of the metal pattern 300. The well regions 202 of the different MOS capacitors 400a disposed under the same grounded shielding metal pattern (metal pattern 300) may be spaced apart from each other without being interconnected, or may be connected to each other. Alternatively, a plurality of different MOS capacitors 400a may be disposed directly under the same metal pattern 300.

Referring to FIGS. 2 to 4 again, the metal pattern 300 and the inductor 250 may be separated by at least two or more metal layers. As shown in FIGS. 3 and 4, for example, the metal pattern 300 is formed on the second metal layer M2, and the inductor 250 is formed on the sixth metal layer M6 and the seventh metal layer M7, and the metal pattern 300 and the inductor 250 The space may be separated from each other by the metal layer 310 located in the third metal layer M3, the metal layer 312 located in the fourth metal layer M4, and the metal layer 314 located in the fifth metal layer M5. The pattern 300 and the inductor 250 are vertically projected in the regions of the metal layer 310 (the third metal layer M3), the 312 (the fourth metal layer M4), and the 314 (the fifth metal layer M5) without a line arrangement. In addition, at least two metal patterns 302-1, 302-2 parallel to each other may be disposed directly under the metal pattern 300. The metal patterns 302-1 and 302-2 are respectively coupled to the two electrodes of the MOS capacitor 400a. For example, the metal pattern 302-1 is coupled to the source 210 and the drain 212 of the MOS capacitor 400a, and the metal pattern is 302-2 is coupled to the gate 206 of the MOS capacitor 400a. The metal patterns 302-1 and 302-2 can be regarded as the electrode leads of the MOS capacitor 400a. The metal pattern 302-1 is coupled to a ground node of a power network or coupled to the metal pattern 300, and the metal pattern is The 302-2 is coupled to a power node of a power network. In other words, the metal pattern 302-1 is electrically grounded. As shown in FIG. 3, the equivalent capacitance of the MOS capacitor 400a is indicated by C1.

In another embodiment of the present invention, the inductor 250 is further formed on the sixth metal layer M6, the seventh metal layer M7, and the metal layer 310 located on the third metal layer M3. The metal layer 312 of the fourth metal layer M4 and the metal layer 314 of the fifth metal layer M5 form an inductance of three or more turns.

Referring again to Figures 2 through 4, in some embodiments of the invention, the metal The patterns 302-1 and 302-2 belong to the same metal layer and belong to different metal layers from the metal pattern 300, respectively. In other words, the metal patterns 302-1, 302-2 and the metal pattern 300 respectively occupy different layers of metal layers of the interconnect structure 350. The metal pattern 300 and the metal patterns 302-1, 302-2 may be spaced apart from each other and parallel to each other by a dielectric layer (not shown) of the interconnect structure 350 described above. For example, when the metal pattern 300 is formed using the second metal layer M2, the metal patterns 302-1, 302-2 may be formed using the first metal layer M1. Further, the MOS capacitor 400a is located directly under the metal patterns 302-1 and 302-2. The metal patterns 302-1, 302-2 may have the same or similar shape (profile) as the metal pattern 300, and for example, the metal patterns 302-1, 302-2 may be metal strips having the same or similar shape as the metal pattern 300. . Also, the width of the metal patterns 302-1, 302-2 may be designed to be less than one-half the width of the metal pattern 300. Therefore, in a plan view (Fig. 2), a boundary of the metal pattern 302-1 and a boundary of the metal pattern 302-2 are respectively located within a boundary of the metal pattern 300. That is, the metal pattern 302-1 and the metal pattern 302-2 are completely covered by the metal pattern 300, respectively, to ensure that the ground shielding effect of the metal pattern 300 on the metal patterns 302-1, 302-2 and the MOS capacitor 400a is not affected.

Fig. 5 is a schematic cross-sectional view taken along line C-C' of Fig. 2, showing a schematic cross-sectional view of an integrated circuit device 500b according to another embodiment of the present invention. The integrated circuit device 500b includes a plurality of metal-oxide-metal capacitors (MOM) 400b disposed under different grounded shielding metal patterns. If the components in the above drawings have the same or similar parts as those shown in FIGS. 1 to 4, reference may be made to the related descriptions above, and the description thereof will not be repeated.

As shown in FIG. 5, in an embodiment of the present invention, a metal-oxide-metal capacitor (hereinafter referred to as MOM capacitor) 400b is provided on the substrate 200. MOM electricity The main elements of the capacitor 400b include a metal pattern 300, metal patterns 302-1, 302-2, and an oxide layer 214 disposed on the metal pattern 300 and the metal patterns 302-1, 302-2. The oxide layer 214 can be a dielectric layer in the interconnect structure 350. In addition, the metal patterns 302-1 and 302-2 may be metal layers of the same layer in the interconnect structure 350, and the metal patterns 300 and the metal patterns 300 are adjacent metal layers in the interconnect structure 350, respectively. For example, when the metal pattern 300 is formed using the second metal layer M2, the metal patterns 302-1, 302-2 may be formed using the first metal layer M1. In other embodiments of the present invention, the metal patterns 302-1, 302-2 may be separated from the metal pattern 300 by two or more vertically stacked oxide layers, and it is only necessary to note that the oxide layer does not include any metal pattern embedded therein. . In this embodiment, the metal patterns 302-1 and 302-2 can be regarded as electrodes of the MOM capacitor 400b. The metal pattern 302-1 is coupled to a ground node of a power network or coupled to a metal pattern. 300, and the metal pattern 302-2 is coupled to a power node of a power network. In other words, the metal pattern 302-1 is electrically grounded. As shown in FIG. 5, the equivalent capacitance of the MOM capacitor 400b is the total capacitance C2 between the metal patterns 302-1, 302-2 and the equivalent capacitance C3 between the metal pattern 302-2 and the metal pattern 300. Hehe.

Fig. 6 is a schematic cross-sectional view taken along line C-C' of Fig. 2, showing a schematic cross-sectional view of an integrated circuit device 500c according to still another embodiment of the present invention. The integrated circuit device 500c includes a plurality of metal-oxide-metal capacitors (MOM capacitors) 400c disposed under different grounded shielding metal patterns. For the components in the above drawings, if they have the same or similar parts as those shown in FIGS. 1 to 5, reference may be made to the above related description, and the description thereof will not be repeated. The difference between the integrated circuit device 500c shown in FIG. 6 and the integrated circuit device 500b shown in FIG. 5 is an integrated circuit. The device 500c includes metal patterns 304-1, 304-2 disposed between the metal pattern 300 and the metal patterns 302-1, 302-2, and is disposed on the metal patterns 304-1, 304-2 and the metal patterns 302-1, 302. An oxide layer 216 between -2 and an oxide layer 218 disposed between the metal pattern 300 and the metal patterns 304-1, 304-2. The oxide layers 216, 218 can belong to a dielectric layer in the interconnect structure 350. In addition, the metal patterns 302-1, 302-2 may belong to the same layer of metal layers in the interconnect structure 350. The metal patterns 304-1, 304-2 may belong to the same layer of metal layers in the interconnect structure 350. The metal patterns 302-1 and 302-2 and the metal patterns 304-1 and 304-2 and the metal pattern 300 respectively belong to different metal layers in the interconnect structure 350. For example, when the metal pattern 300 is formed using the third metal layer M3, the metal patterns 304-1, 304-2 may be formed using the second metal layer M2, and the metal patterns 302-1, 302-2 may be utilized. A metal layer M1 is formed. In other embodiments of the present invention, the metal patterns 304-1, 304-2 may be separated from the metal pattern 300 and/or the metal patterns 302-1, 302-2 by two or more layers of vertically stacked oxide layers, only the above-mentioned No metal pattern is embedded in the oxide layer.

In the present embodiment, the metal patterns 302-1, 302-2, 304-1, and 304-2 can be regarded as the electrodes of the MOM capacitor 400c. Moreover, the metal patterns adjacent to each other among the metal patterns 302-1, 302-2, 304-1, and 304-2 are respectively coupled to different nodes. For example, the metal pattern 302-1 is coupled to the ground node, and the metal patterns 302-2, 304-1 adjacent to the metal pattern 302-1 are coupled to the power supply node and adjacent to the metal patterns 302-2, 304. The metal pattern 304-2 of -1 is coupled to the ground node. In other words, the metal patterns 302-1, 304-2 are electrically grounded. As shown in FIG. 6, the equivalent capacitance of the MOM capacitor 400c is equivalent capacitance C4 between the metal patterns 302-1 and 302-2, between the metal pattern 302-1 and the metal pattern 304-1, and the like. The effective capacitance C5, the equivalent capacitance C6 between the metal pattern 302-2 and the metal pattern 304-2, the equivalent capacitance C7 between the metal pattern 304-1 and the metal pattern 300, and the metal pattern 304-2 and the metal pattern 304- 1, the sum of the equivalent capacitance C8 between 304-2.

Fig. 7 is a schematic cross-sectional view taken along line C-C' of Fig. 2, showing a schematic cross-sectional view of an integrated circuit device 500d according to another embodiment of the present invention. The difference between the integrated circuit device 500d shown in FIG. 7 and the integrated circuit device 500c shown in FIG. 6 is that the integrated circuit device 500d includes a plurality of MOM capacitors 400c disposed under different grounded shielding metal patterns and The MOS capacitor 400a is disposed under the MOM capacitor 400c. For the components in the above drawings, if they have the same or similar parts as those shown in FIGS. 1 to 6, reference may be made to the related description above, and the description thereof will not be repeated. In the present embodiment, the metal patterns 302-1, 302-2, 304-1, and 304-2 can be regarded as the electrodes of the MOM capacitor 400c, and the metal patterns 302-1 and 302-2 can be regarded as the electrodes of the MOS capacitor 400a. Moreover, the metal patterns adjacent to each other among the metal patterns 302-1, 302-2, 304-1, and 304-2 are respectively coupled to different nodes. For example, the metal pattern 302-1 is coupled to the ground node, and the metal patterns 302-2, 304-1 adjacent to the metal pattern 302-1 are coupled to the power supply node and adjacent to the metal patterns 302-2, 304. The metal pattern 304-2 of -1 is coupled to the ground node. As shown in Fig. 7, the equivalent capacitance of the integrated circuit device 500d is the sum of the MOM capacitor 400c and the MOS capacitor 400a.

Embodiments of the present invention provide an integrated circuit device that disposes a MOS capacitor and/or a MOM capacitor directly under the inductive component on the wafer and is located on the ground shielding metal pattern and the substrate for shielding the inductive component on the wafer. In the area between. The MOS capacitor is disposed directly under the ground shielding metal pattern and utilizes two of the MOS capacitors and the ground shielding metal pattern. The metal patterns parallel to each other are used as electrode wires, respectively coupled to the two electrodes of the MOS capacitor, and respectively coupled to a ground node of a power network and a power node. The MOM capacitor may be formed by using at least two metal patterns in the interconnect structure and an oxide layer between the metal patterns, and the at least two metal patterns may be respectively used as two electrodes of the MOM capacitor, and respectively coupled to A ground node (or ground shield metal pattern) of a power network and a power node. The equivalent capacitance of the MOM capacitor includes a capacitance value formed by two metal patterns and an oxide layer, and a capacitance value formed by the two metal patterns and the ground shielding metal pattern and the oxide layer, respectively. In some embodiments of the invention, the capacitive configuration located directly below the inductive component on the wafer saves area of the circuit layout and is compatible with current semiconductor processes without adding additional process steps and costs. In addition, the capacitor disposed directly under the inductive component on the wafer can be used as a decoupling capacitor of the power network. Since the operating frequency of the decoupling capacitor is much smaller than the operating frequency of the inductive component on the wafer, the Interference from other integrated circuit components.

While the present invention has been described by way of example only, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

200‧‧‧Substrate

201‧‧‧ surface

202‧‧‧ Well Area

204‧‧‧ gate oxide layer

206‧‧‧ gate

208‧‧‧ gate structure

210‧‧‧ source

212‧‧‧汲polar

250‧‧‧Inductance

300‧‧‧Metal pattern

302-1, 302-2‧‧‧ metal pattern

310, 312, 314‧‧‧ metal layers

350‧‧‧Interconnection structure

400a‧‧‧Metal-oxide-semiconductor capacitor

500a‧‧‧Integrated circuit device

C1‧‧‧ equivalent capacitance

M1‧‧‧ first metal layer

M2‧‧‧ second metal layer

M3‧‧‧ third metal layer

M4‧‧‧4th metal layer

M5‧‧‧ fifth metal layer

M6‧‧‧6th metal layer

M7‧‧‧ seventh metal layer

Claims (20)

An integrated circuit device includes: a substrate; a first capacitor disposed on the substrate; a first metal pattern coupled to a first electrode of the first capacitor; and a second metal pattern coupled to a second electrode of the first capacitor; a third metal pattern disposed over the first metal pattern and the second metal pattern and covering the first capacitor, the first metal pattern, and the second metal pattern, The third metal pattern is electrically grounded; and an inductor is disposed above the third metal pattern, wherein the first capacitor comprises: a first oxide layer disposed on the first metal pattern and the second metal Between the pattern and the third metal pattern, wherein the first metal pattern is the first electrode of the first capacitor, and the second metal pattern is the second electrode of the first capacitor. The integrated circuit device of claim 1, further comprising a plurality of metal layers disposed on the substrate, wherein the third metal pattern and the first metal pattern respectively occupy different metal layers of the metal layers a layer, wherein the third metal pattern and the second metal pattern respectively occupy different metal layers of the metal layers. The integrated circuit device of claim 1, wherein in a top view, the third metal pattern is directly under the inductor, and the first metal pattern and the second metal pattern are located at the third metal pattern. Directly below, a boundary of the first metal pattern and a boundary of the second metal pattern are respectively located Within a boundary of the third metal pattern. The integrated circuit device of claim 1, wherein the first metal pattern, the second metal pattern, and the third metal pattern are spaced apart from each other and are parallel to each other. The integrated circuit device of claim 1, wherein the first capacitor is a first metal-oxide-metal capacitor. The integrated circuit device of claim 1, wherein the first metal pattern and the second metal pattern belong to a first metal layer, and the third metal pattern belongs to a second metal layer, and The second metal layer is different from the first metal layer. The integrated circuit device of claim 1, wherein the first metal pattern belongs to a first metal layer, the second metal pattern belongs to a second metal layer, and the third metal pattern belongs to a The third metal layer, and the first metal layer, the second metal layer, and the third metal layer are different from each other. The integrated circuit device of claim 1, further comprising: a second capacitor disposed between the substrate and the third metal pattern. The integrated circuit device of claim 8, wherein the second capacitor is a metal-oxide-semiconductor varactor. The integrated circuit device of claim 9, wherein the second capacitor is a first metal-oxide-semiconductor capacitor, and the first metal-oxide-semiconductor capacitor comprises: a first well region, Extending from a surface of the substrate to a portion of the substrate; a first gate structure disposed on the first well region; and a source and a drain respectively located at the first gate structure relatively a side, wherein the first gate structure is the first electrode, and the source and the anode are the second electrode. The integrated circuit device of claim 10, wherein the first well region is formed by implanting an impurity on the substrate. The integrated circuit device according to claim 10, wherein the impurity is a p-type impurity or an n-type impurity. The integrated circuit device of claim 10, further comprising: a third capacitor disposed between the substrate and the third metal pattern. The integrated circuit device of claim 13, wherein the third capacitor is a second metal-oxide-semiconductor capacitor disposed side by side with the first metal-oxide-semiconductor capacitor, wherein the second A second well region of the metal-oxide-semiconductor capacitor is spaced apart from the first well region. The integrated circuit device of claim 14, wherein the third metal pattern comprises a first metal line and a second metal line, wherein in a top view, the first metal line completely covers the first a well area, and the second metal line completely covers the second well area. The integrated circuit device of claim 15, wherein the substrate is exposed between the first metal line and the second metal line. The integrated circuit device of claim 1, further comprising: a fourth metal pattern between the first metal pattern and the third metal pattern; and a fifth metal pattern on the second metal Between the pattern and the third metal pattern; and an oxide layer disposed on the first metal pattern, the second metal pattern, Between the third metal pattern, the fourth metal pattern and the fifth metal pattern, wherein the first metal pattern and the fifth metal pattern are the first electrode of the first capacitor, the second metal pattern and the The fourth metal pattern is the second electrode of the first capacitor. The integrated circuit device of claim 17, further comprising a plurality of metal layers disposed on the substrate, wherein the third metal pattern, the first metal pattern and the fourth metal pattern respectively occupy the a different metal layer of the metal layer, wherein the third metal pattern, the second metal pattern, and the fifth metal pattern respectively occupy different metal layers of the metal layers. The integrated circuit device of claim 1, further comprising: a second capacitor disposed between the substrate and the first capacitor. The integrated circuit device of claim 19, wherein the second capacitor is a metal-oxide-semiconductor varactor or a first metal-oxide-semiconductor capacitor.