TWI781704B - Power amplifier module - Google Patents

Abstract

A power amplifier module includes a substrate including, in an upper surface of the substrate, an active region and an element isolation region; a collector layer, a base layer, and an emitter layer that are stacked on the active region; an interlayer insulating film that covers the collector layer, the base layer, and the emitter layer; a pad that is thermally coupled to the element isolation region; and an emitter bump that is disposed on the interlayer insulating film, electrically connected to the emitter layer through a via hole provided in the interlayer insulating film, and electrically connected to the pad. In plan view, the emitter bump partially overlaps an emitter region which is a region of the emitter layer and through which an emitter current flows.

Description

power amplifier module

The invention relates to a power amplifier module, in particular to a power amplifier module suitable for transmission systems such as mobile phones.

When the power amplifier module is in operation, the transistor itself heats up, so the temperature of the transistor rises and the performance of the power amplifier module decreases. In order to suppress performance degradation, it is desirable to efficiently dissipate heat from the heat source of the transistor to the outside of the power amplifier module. In a configuration in which a semiconductor chip including the transistor is mounted on a printed board via bumps, heat is dissipated by a heat path from the transistor to the printed board via the bumps.

Patent Document 1 below discloses a semiconductor device in which heat dissipation characteristics are improved by shortening the heat dissipation path. This semiconductor device includes an HBT, and an emitter electrode is arranged on an emitter region of the HBT. Wiring for the emitter is arranged on the emitter electrode via the interlayer insulating film of the first layer. The wiring for the emitter is connected to the emitter electrode through the opening provided in the interlayer insulating film of the first layer. An emitter main electrode terminal is disposed on the wiring for the emitter via a second-layer interlayer insulating film. The emitter main electrode terminal is connected to the emitter wiring through an opening provided in the interlayer insulating film of the second layer. A bump electrode is provided on the emitter main electrode terminal.

In this HBT, the thermal path from the emitter layer to the bump electrode via the emitter electrode, the wiring for the emitter, and the emitter main electrode terminal functions as a heat dissipation path for releasing heat generated in the HBT. Since the emitter layer, emitter electrode, wiring for emitter, emitter main electrode terminal, and bump electrode are sequentially stacked in the thickness direction of the substrate, heat dissipation can be shortened compared to a structure that releases heat laterally to the substrate. The effect of the path.

Patent Document 1: Japanese Patent Laid-Open No. 2003-77930

In the HBT disclosed in Patent Document 1, the cross-sectional area of the heat dissipation path connecting the emitter, base, and collector to their corresponding bump electrodes is limited by the areas of the emitter, base, and collector. For example, the cross-sectional area of the heat dissipation path provided in the opening of the interlayer insulating film of the first layer for connecting the emitter electrode and wiring for the emitter cannot be larger than that of the emitter electrode. Thus, it is difficult to unconditionally increase the cross-sectional area of the heat dissipation path. Therefore, it is difficult to sufficiently reduce the thermal resistance of the thermal path from the HBT to the bump electrode.

The object of the present invention is to provide a power amplifier module capable of increasing the heat dissipation efficiency by increasing the cross-sectional area of the heat dissipation path without being limited by the areas of the emitter, base, and collector.

A power amplifier module according to an aspect of the present invention has: A substrate comprising a conductive active region and an insulating element isolation region adjacent to the active region in the upper surface; The collector layer, the base layer and the emitter layer are sequentially stacked on the above active area; an interlayer insulating film covering the collector layer, the base layer, and the emitter layer; a spacer, thermally coupled to the above-mentioned component separation area; and an emitter bump disposed on the interlayer insulating film, electrically connected to the emitter layer through a via hole formed in the interlayer insulating film, and also electrically connected to the spacer, In a plan view, the emitter bump partially overlaps with an emitter region, which is a region where an emitter current flows in the emitter layer.

Since the spacer is electrically connected to the emitter bump, the thermal resistance of the heat path from the spacer to the emitter bump is reduced compared to a structure connected via an insulating layer. Accordingly, a heat dissipation path is formed that conducts heat generated by heat sources in the collector layer, the base layer, and the emitter layer to the pad through the substrate and from the pad to the emitter bump. This heat dissipation path joins the heat dissipation path formed in the region where the emitter region overlaps the emitter bump. Therefore, the actual cross-sectional area of the heat dissipation path increases. As a result, heat dissipation efficiency can be improved.

[First Embodiment] Referring to FIG. 1A and FIG. 1B , the power amplifier module of the first embodiment will be described. Fig. 1A is the emitter electrode, the base electrode and the collector electrode made of metal which are respectively connected to the emitter layer, the base layer and the collector layer of the transistor included in the power amplifier module of the first embodiment, and This is a plan view of wiring made of metal on an upper layer than these electrodes. In FIG. 1A , the first-layer emitter wiring E1 and the first-layer collector wiring C1 are hatched.

A base electrode B0 having a planar shape of a horseshoe (U-shape) is arranged to sandwich an emitter electrode E0 having a planar shape (for example, a rectangle) long in one direction (longitudinal direction in FIG. 1A ) in the width direction. . For example, in FIG. 1A , the base electrode B0 is arranged on both sides in the left-right direction and on the lower side in the longitudinal direction of the emitter electrode E0 . Collector electrodes C0 are disposed on both sides of the base electrode B0 . Each of the collector electrodes C0 also has a long planar shape (for example, a rectangle) in a direction parallel to the long side direction of the emitter electrode E0 . The collector electrode C0 , the base electrode B0 , and the emitter electrode E0 are arranged inside the active region 21 .

The first-layer emitter wiring E1 is arranged so as to substantially overlap the emitter electrode E0 in plan view. The first-layer collector wiring C1 is arranged so as to substantially overlap each of the collector electrodes C0. The first-layer collector wiring C1 extends outside the end of the collector electrode C0 in the longitudinal direction, and includes a collector connection portion C1 a connecting the extended portions to each other.

With respect to the width direction of the emitter electrode E0 (the lateral direction in FIG. 1A ), spacers T0 for heat dissipation are arranged on the outer sides of the pair of collector electrodes C0, and a thermally conductive film T1 for heat conduction is arranged to overlap thereon. . The pad T0 for heat dissipation is arranged in the same layer as the collector electrode C0, and the thermally conductive film T1 is arranged in the same layer as the first-layer collector wiring C1.

The second-layer emitter wiring E2 is arranged so as to partially overlap with a region in the emitter layer where an emitter current actually flows. The region where the emitter current flows in the emitter layer is referred to as an emitter region 36 . The emitter bump EB is arranged to substantially overlap the second layer emitter wiring E2. The second-layer emitter wiring E2 is electrically connected to the first-layer emitter wiring E1 below it via the inside of a via hole provided in the interlayer insulating film.

Here, the configuration that two regions "partially overlap" includes a configuration in which a part of one region overlaps a part of the other region in plan view, and a configuration in which the entire one region overlaps a part of the other region. constitute the two parties. The emitter region 36 basically coincides with the region where the emitter electrode E0 is arranged. In the example shown in FIG. 1A , the entire emitter region 36 partially overlaps the second-layer emitter wiring E2 and part of the emitter bump EB.

The second-layer emitter wiring E2 and the emitter bump EB pass above the collector electrode C0 disposed on both sides of the emitter electrode E0 and extend to above the pad T0 for heat dissipation and the heat conduction film T1 . The second-layer emitter wiring E2 is electrically connected to the heat conduction film T1 through the inside of a via hole provided in the interlayer insulating film.

The collector connection portion C1a of the first-layer collector wiring C1 is arranged outside the second-layer emitter wiring E2 and the emitter bump EB. The second-layer collector wiring C2 is arranged to overlap the collector connection portion C1a. The second-layer collector wiring C2 is electrically connected to the first-layer collector wiring C1 via the inside of a via hole provided in the interlayer insulating film. The collector bump CB is arranged to substantially overlap the second layer collector wiring C2. The collector bump CB is electrically connected to the second layer collector wiring C2.

FIG. 1B is a cross-sectional view at a dot chain line 1B-1B in FIG. 1A . In this cross-sectional view, not only electrodes and wirings but also substrates and semiconductor layers are shown. A heterojunction bipolar transistor (HBT) is included in the power amplifier module of the first embodiment.

The upper surface of the substrate 20 is divided into an active region 21 imparted with conductivity and an insulating element isolation region 22 . The element isolation region 22 is adjacent to the active region 21 and surrounds the active region 21 . The substrate 20 includes, for example, a base substrate made of a semi-insulating compound semiconductor and an epitaxial growth layer made of an n-type compound semiconductor grown on the base substrate. The element isolation region 22 is formed by insulating implantation into a part of the epitaxial growth layer. Here, "insulation implantation" refers to ion implantation performed to change a semiconductor into an insulating property. A region not subjected to insulating implantation corresponds to the active region 21 .

A mesa structure 30 in which a collector layer 31 , a base layer 32 , and an emitter layer 33 are sequentially stacked is formed on a part of the active region 21 of the substrate 20 . An emitter contact layer 34 is arranged on a part of the emitter layer 33 . The emitter layer 33 in the region where the emitter contact layer 34 is not arranged is depleted. The emitter current flows in the emitter region 36 that overlaps the emitter contact layer 34 in a planar view in the bonding interface between the emitter layer 33 and the base layer 32 . As shown in FIG. 1A , the emitter region 36 substantially coincides with the emitter electrode E0 and the emitter contact layer 34 in plan view. During the operation of the HBT, the emitter region 36 and the base layer 32 and the collector layer 31 immediately below it become a heat source 37 .

Collector electrodes C0 are disposed on the active regions 21 on both sides of the mesa structure 30 . The collector electrode C0 is in ohmic connection with the active region 21 . Base electrodes B0 are disposed on both sides of the emitter contact layer 34 . The base electrode B0 is arranged in the opening formed in the emitter layer 33 and is in ohmic connection with the base layer 32 . An emitter electrode E0 is arranged on the emitter contact layer 34 .

Spacers T0 for heat dissipation are arranged in the element isolation regions 22 on both sides of the active region 21 . The pad T0 for heat dissipation is in direct contact with the element isolation region 22 on the upper surface of the substrate 20 and is thermally coupled. The collector electrode C0, the base electrode B0, the emitter electrode E0, and the spacer T0 for heat dissipation are composed of a metal film or a metal multilayer film.

The interlayer insulating film 40 covers the mesa structure 30 , the emitter contact layer 34 , the collector electrode C0 , the base electrode B0 , the emitter electrode E0 , and the pad T0 for heat dissipation.

On the emitter electrode E0 , the collector electrode C0 , and the spacer T0 for heat dissipation, the first-layer emitter wiring E1 , the first-layer collector wiring C1 , and the thermally conductive film T1 are disposed, respectively. The first-layer emitter wiring E1 , the first-layer collector wiring C1 , and the thermally conductive film T1 are electrically connected to the emitter electrode E0 , the collector electrode C0 , and the pad T0 for heat dissipation through openings formed in the interlayer insulating film 40 . The heat conduction film T1 is electrically connected to the underlying pad T0 without an insulating film, thereby ensuring good heat conduction efficiency between the two.

An interlayer insulating film 41 is disposed on the interlayer insulating film 40 , the first-layer emitter wiring E1 , the first-layer collector wiring C1 , and the heat conduction film T1 . The interlayer insulating film 41 is formed of, for example, an insulating resin, and its upper surface is substantially planarized.

The second-layer emitter wiring E2 is arranged on the interlayer insulating film 41 . The second-layer emitter wiring E2 is electrically connected to the first-layer emitter wiring E1 through the inside of the first via hole 43 formed in the interlayer insulating film 41 . Furthermore, the second-layer emitter wiring E2 is electrically connected to the heat conduction film T1 through the inside of the second via hole 44 formed in the interlayer insulating film 41 . The second-layer emitter wiring E2 is thermally coupled to the pad T0 via the thermally conductive film T1.

A protective film 42 is disposed on the second-layer emitter wiring E2 and the interlayer insulating film 41 . An opening that substantially overlaps the second layer emitter wiring E2 in plan view is provided in the protective film 42 . An emitter bump EB is arranged on the second-layer emitter wiring E2 in the opening. The emitter bump EB includes, for example, a pillar 51 made of copper (Cu) and a solder 52 arranged on the upper surface thereof. A bump of this structure is called a Cu pillar bump.

Next, the excellent effect of the power amplifier module of the first embodiment will be described. The heat generated in the heat source 37 is transmitted to the emitter bump through the first heat path TP1 composed of the emitter electrode E0, the first-layer emitter wiring E1, the conductor in the first through hole 43, and the second-layer emitter wiring E2. Block EB. Since the emitter bump EB partially overlaps the emitter region (heat source 37 ), the first thermal path TP1 connects the heat source 37 and the emitter bump EB the shortest in the thickness direction. Therefore, the heat radiation efficiency via the first heat path TP1 can be improved. In addition, it is preferable to configure so that 90% or more of the emitter region overlaps the emitter bump EB in plan view. By adopting this configuration, the cross-sectional area of the planar section of the first thermal path TP1 can be increased, and the heat dissipation efficiency through the first thermal path TP1 can be improved. “Plane cross section” refers to a cross section taken on an imaginary plane parallel to the upper surface of the substrate 20 .

In addition, the heat-dissipating pad T0 made of conductors, the thermally conductive film T1 , and the conductors in the second via holes 44 have higher thermal conductivity than the interlayer insulating film 41 . Therefore, the heat generated in the heat source 37 is transmitted to the second heat path TP2 constituted by the substrate 20, the pad T0 for heat dissipation, the heat conduction film T1, the conductor in the second through hole 44, and the second-layer emitter wiring E2. Emitter bump EB.

The area of the flat cross section of the first through hole 43 arranged in the first thermal path TP1 is limited by the area of the emitter electrode E0. In contrast, since the second through hole 44 is disposed on the element isolation region 22 , the area of the planar section of the second through hole 44 is not so limited. Likewise, the area of the planar cross-section of the via hole provided in the interlayer insulating film 40 for connecting the pad T0 to the thermally conductive film T1 is not limited in this way. Therefore, the cross section of the second thermal path TP2 can be enlarged from the minimum cross section of the first thermal path TP1. By enlarging the planar cross-section area of the second via hole 44 and the via hole provided in the interlayer insulating film 40 to connect the pad T0 to the heat conduction film T1 , heat dissipation efficiency via the second thermal path TP2 can be improved.

In addition, since the emitter bump EB and the pad T0 for heat dissipation are arranged so as to partially overlap each other in plan view, the second heat path TP2 can be shortened. Thereby, the heat radiation efficiency via the 2nd thermal path TP2 can be further improved.

The planar section of the first thermal path TP1 corresponds to the planar section of the current path connecting the emitter bump EB and the emitter layer 33 . In order to improve heat dissipation efficiency, it is preferable to make the minimum value of the area of the plane section of the conductor portion connecting the emitter bump EB and the pad T0 for heat dissipation be larger than the current path electrically connecting the emitter bump EB and the emitter layer 33 The minimum value of the area of the plane section is large. In the first embodiment, for example, emitter bumps are given at positions respectively provided in either of the through holes of the interlayer insulating films 40, 41 arranged between the second-layer emitter wiring E2 and the emitter layer 33. The minimum value of the area of the flat section of the current path connecting EB to the emitter layer 33 . Either of the via hole 44 provided in the interlayer insulating film 40 or the second via hole 44 provided in the interlayer insulating film 41 to connect the pad T0 to the heat conduction film T1 is given to connect the emitter bump EB to the pad T0. The minimum value of the area of the plane section of the conductor part.

Also, in the first embodiment, heat is dissipated from the heat source 37 through two heat paths, the first heat path TP1 and the second heat path TP2 . Therefore, heat radiation efficiency can be improved compared to a configuration using only one of the heat paths.

[Second Embodiment] Next, the power amplifier module of the second embodiment will be described with reference to FIG. 2 and FIG. 3 . Hereinafter, the description of the same configuration as that of the power amplifier module of the first embodiment will be omitted.

Fig. 2 is the emitter electrode, the base electrode and the collector electrode made of metal which are respectively connected to the emitter layer, the base layer and the collector layer of the transistor included in the power amplifier module of the second embodiment, and This is a plan view of wiring made of metal on an upper layer than these electrodes. Components shown in FIG. 2 are denoted by the same reference numerals as those assigned to corresponding components of the power amplifier module of the first embodiment shown in FIG. 1A .

In the first embodiment, the spacer T0 for heat dissipation and the heat conduction film T1 ( FIG. 1A ) are arranged in a region intersecting an imaginary straight line extending the emitter region in a direction perpendicular to its longitudinal direction. In the second embodiment, the spacer T0 for heat dissipation and the heat conduction film T1 are arranged in a region intersecting an imaginary straight line extending the emitter region 36 in the longitudinal direction.

Fig. 3 is a cross-sectional view at one point chain line 3-3 in Fig. 2 . On the element isolation region 22 on the left side of the emitter electrode E0, a pad T0 for heat dissipation and a heat conduction film T1 are arranged. The second-layer emitter wiring E2 arranged on the interlayer insulating film 41 is electrically connected to the heat conduction film T1 via the inside of the second via hole 44 provided in the interlayer insulating film 41 .

In the element isolation region 22 on the opposite side to the side where the pad T0 for heat dissipation and the heat conduction film T1 are arranged when viewed from the emitter electrode E0 , the first layer collector wiring C1 is arranged via the interlayer insulating film 40 . The second layer collector wiring C2 is arranged on the interlayer insulating film 41 . The second-layer collector wiring C2 is electrically connected to the first-layer collector wiring C1 through the inside of the third via hole 45 provided in the interlayer insulating film 41 .

A collector bump CB is arranged on the second layer collector wiring C2. The collector bump CB has the same laminated structure as the emitter bump EB.

Next, the excellent effect of the power amplifier module of the second embodiment will be described. In the second embodiment, the same first thermal path TP1 and second thermal path TP2 as those of the first embodiment are also formed. Therefore, similarly to the first embodiment, the heat radiation efficiency from the heat source 37 can be improved.

In addition, in the second embodiment, with regard to the width direction of the emitter electrode E0, the size of the region where the mesa structure 30, the pad T0 for heat dissipation, and the heat conduction film T1 are arranged is larger than that of the corresponding power amplifier module of the first embodiment. The size of the region is small. This configuration is advantageous when a plurality of HBTs are arranged in the width direction of the emitter electrode E0 as in the embodiment described later with reference to FIG. 13 .

[Third Embodiment] Next, the power amplifier module of the third embodiment will be described with reference to FIGS. 4 to 6 . Hereinafter, the description of the same configuration as the power amplifier module ( FIGS. 2 and 3 ) of the second embodiment will be omitted.

Fig. 4 is the emitter electrode, the base electrode and the collector electrode made of metal which are respectively connected to the emitter layer, the base layer and the collector layer of the transistor included in the power amplifier module of the third embodiment, and This is a plan view of wiring made of metal on an upper layer than these electrodes. Components shown in FIG. 4 are denoted by the same reference numerals as those assigned to corresponding components of the power amplifier module of the second embodiment shown in FIG. 2 . In the second embodiment, the collector electrode C0 is arranged inside the active region 21 in plan view. In the third embodiment, the collector electrode C0 extends to the outside of the active region 21 .

The collector electrodes C0 disposed on both sides of the emitter electrode E0 spread toward the outside of the active region 21 in the width direction of the emitter electrode E0 . Further, the collector electrode C0 extends to the outside of the active region 21 toward one side in the longitudinal direction of the emitter electrode E0 . The direction in which the collector electrode C0 extends is opposite to the direction toward the pad T0 for heat dissipation and the thermally conductive film T1 viewed from the active region 21 . The collector electrodes C0 disposed on both sides of the emitter electrode E0 are continuous with each other outside the active region 21 . The first-layer collector wiring C1 has a planar shape substantially overlapping the collector electrode C0.

FIG. 5A is a cross-sectional view at a dot chain line 5A-5A in FIG. 4 . The collector electrode C0 extends from the active region 21 toward the right side to the outside of the active region 21 and reaches the element isolation region 22 . The first-layer collector wiring C1 arranged on the collector electrode C0 also extends to the element isolation region 22 . The collector electrode C0 is in direct contact with the surfaces of the active region 21 and the element isolation region 22 .

The second-layer collector wiring C2 arranged on the interlayer insulating film 41 is electrically connected to the first-layer collector wiring C1 through the inside of the third via hole 45 provided in the interlayer insulating film 41 . A collector bump CB is arranged on the second layer collector wiring C2. The collector bump CB partially overlaps the collector electrode C0 in a planar view.

FIG. 5B is a cross-sectional view at the dot chain line 5B-5B in FIG. 4 . The cross-sectional view of FIG. 5B corresponds to the cross-sectional view shown in FIG. 3 of the power amplifier module of the second embodiment. In the second embodiment, an interlayer insulating film 40 is disposed between the first-layer collector wiring C1 and the element isolation region 22 . In the third embodiment, the first-layer collector wiring C1 is in direct contact with the collector electrode C0 , and the collector electrode C0 is in direct contact with the element isolation region 22 . In the cross section shown in FIG. 5B , the collector bump CB also partially overlaps the collector electrode C0 in plan view.

Fig. 6 is a cross-sectional view at one point chain line 6-6 in Fig. 4 . The collector electrode C0 arranged on both sides of the mesa structure 30 spreads in the width direction of the emitter electrode E0 (right and left in FIG. 6 ), and reaches the element isolation region 22 . A first-layer collector wiring C1 is arranged on the collector electrode C0.

Next, the excellent effect of the power amplifier module of the third embodiment will be described. In the third embodiment, as in the second embodiment, it is possible to efficiently dissipate heat from the heat source 37 via the first thermal path TP1 ( FIG. 5B , FIG. 6 ) and the second thermal path TP2 ( FIG. 5B ).

Also, in the third embodiment, the third thermal path TP3 ( Figure 5A, Figure 5B, Figure 6). Therefore, heat dissipation efficiency can be further improved.

As shown in FIG. 6 , the heat generated by the heat generating source 37 is transmitted laterally across the substrate 20 and reaches the nearest collector electrode C0 . Thereafter, as shown in FIG. 5A , transfer occurs in the in-plane direction at the collector electrode C0 and the first layer collector wiring C1 and reaches the third via hole 45 . Since the long part of the third thermal path TP3 in the longitudinal direction of the emitter electrode E0 includes the collector electrode C0 made of metal and the first layer collector wiring C1 , efficient heat transfer can be performed.

Furthermore, in the third embodiment, the collector electrode C0 extends to the element isolation region 22 adjacent to the active region 21 , so the area of the flat cross section of the third thermal path TP3 can be increased. As a result, heat dissipation efficiency can be further improved.

Also, in the third embodiment, the second-layer emitter wiring E2 and the emitter bump EB ( FIG. 5A , FIG. 6 ) are connected to the collector electrode C0 ( FIG. 5A , FIG. 6 ) in contact with the upper surface of the substrate 20 . Partially overlap when looking down. In the overlapping portion, a fourth thermal path TP4 is formed from the collector electrode C0 through the first-layer collector wiring C1 and the interlayer insulating film 41 toward the second-layer emitter wiring E2 ( FIG. 5A ). Although the thermal conductivity of the interlayer insulating film 41 is lower than that of metal, when the area of the overlapping portion of the emitter wiring E2 and the collector electrode C0 of the second layer is large, the fourth thermal path TP4 also acts as a source of heat. The heat dissipation path for the heat generated by source 37 (FIG. 6) is fully functional. Therefore, heat dissipation efficiency can be improved.

[Modification of the third embodiment] Next, a power amplifier module according to a modified example of the third embodiment will be described with reference to FIGS. 7A and 7B .

7A and 7B are cross-sectional views of a power amplifier module according to a modified example of the third embodiment, corresponding to the cross-sectional views of the power amplifier module of the third embodiment in FIG. 5A and FIG. 6 . In this modified example, the thermal conductivity of the interlayer insulating film 41 in the region 41a where the second-layer emitter wiring E2 and the collector electrode C0 overlap in plan view is higher than that of the other regions. By doping the interlayer insulating film 41 in the overlapping region 41 a with particles having high thermal conductivity, the thermal conductivity of this portion can be increased. For example, after forming a resin film such as polyimide over the entire region, removing the resin film in the region 41a, and embedding an insulating material containing a plurality of particles having a higher thermal conductivity than the resin film in the removed region , thereby forming such an interlayer insulating film 41 .

In this modified example, the thermal resistance of the fourth thermal path TP4 from the collector electrode C0 to the second-layer emitter wiring E2 via the first-layer collector wiring C1 and the interlayer insulating film 41 can be reduced. As a result, the heat transferred to the collector electrode C0 through the third heat path TP3 can be efficiently dissipated through the fourth heat path TP4.

In the above modification of the third embodiment, a material having high thermal conductivity is used for only a part of interlayer insulating film 41 , but a material having high thermal conductivity may be used for the entire interlayer insulating film 41 . For example, the entire interlayer insulating film 41 may be formed of an insulating material including a plurality of particles made of an inorganic material having a higher thermal conductivity than resin.

[Fourth Embodiment] Next, the power amplifier module of the fourth embodiment will be described with reference to FIGS. 8 to 10 . Hereinafter, the description of the same configuration as the power amplifier module of the third embodiment will be omitted.

Fig. 8 is the emitter electrode, the base electrode and the collector electrode made of metal which are respectively connected to the emitter layer, the base layer and the collector layer of the transistor included in the power amplifier module of the fourth embodiment, and This is a plan view of wiring made of metal on an upper layer than these electrodes. The components shown in FIG. 8 are denoted by the same reference numerals as those added to the corresponding components of the power amplifier module of the third embodiment shown in FIG. 4 .

In the third embodiment, the second-layer emitter wiring E2 and the emitter bump EB ( FIG. 4 ) partially overlap the emitter region 36 . In contrast, in the fourth embodiment, the second-layer collector wiring C2 and the collector bump CB partially overlap the emitter region 36 . The second-layer emitter wiring E2 and the emitter bump EB do not overlap the emitter region 36 . The second-layer collector wiring C2 and the collector bump CB also partially overlap the collector electrode C0 arranged on both sides of the emitter electrode E0 .

The first-layer emitter wiring E1 arranged to overlap the emitter electrode E0 is drawn out to the outside of the second-layer collector wiring C2 (lower in the vertical direction in FIG. 8 ) in plan view. The first-layer emitter wiring E1 spreads outside the second-layer collector wiring C2 to increase its area. The second-layer emitter wiring E2 and the emitter bump EB are arranged to overlap in this widened region. In addition, the spacer T0 for heat dissipation is also disposed so as to overlap the widened region.

FIG. 9A is a cross-sectional view at the chain line 9A-9A of FIG. 8 , corresponding to the cross-sectional view shown in FIG. 5A of the power amplifier module of the third embodiment. In the third embodiment, the second-layer emitter wiring E2 ( FIG. 5A ) and the emitter bump EB ( FIG. 5A ) extend above the collector electrode C0 ( FIG. 5 ). In the fourth embodiment, the second-layer emitter wiring E2 and the emitter bump EB do not overlap the collector electrode C0. The second-layer collector wiring C2 and the collector bump CB are arranged directly above the collector electrode C0 and the first-layer collector wiring C1 . The second-layer collector wiring C2 is electrically connected to the first-layer collector wiring C1 through the inside of the third via hole 45 provided in the interlayer insulating film 41 .

FIG. 9B is a sectional view at the dot chain line 9B-9B in FIG. 8 , corresponding to the sectional view shown in FIG. 5B of the power amplifier module of the third embodiment. In the third embodiment, the second-layer emitter wiring E2 ( FIG. 5B ) is arranged directly above the emitter electrode E0 ( FIG. 5B ). In the fourth embodiment, the first-layer emitter wiring E1 arranged on the emitter electrode E0 extends toward the left side in FIG. 9B and reaches the pad T0 for heat dissipation arranged on the element isolation region 22 .

On the interlayer insulating film 41 , the second-layer emitter wiring E2 and the emitter bump EB are arranged so as to overlap the pad T0 for heat dissipation in plan view. The second-layer emitter wiring E2 is electrically connected to the first-layer emitter wiring E1 through the inside of the first via hole 43 provided in the interlayer insulating film 41 . Similar to the second thermal path TP2 ( FIG. 3 ) of the power amplifier module of the second embodiment, the second thermal path TP2 is formed from the heat source 37 to the emitter bump EB. Furthermore, a fifth thermal path TP5 is formed from the heat source 37 to the emitter bump EB via the emitter electrode E0 , the first-layer emitter wiring E1 , the conductor in the first through hole 43 , and the second-layer emitter wiring E2 .

The second-layer collector wiring C2 and collector bump CB arranged to partially overlap the collector electrode C0 arranged on the element isolation region 22 extend to a region above the emitter electrode E0 .

FIG. 10 is a cross-sectional view at the dot chain line 10-10 in FIG. 8, corresponding to the cross-sectional view shown in FIG. 6 of the power amplifier module of the third embodiment. In the third embodiment, the second-layer emitter wiring E2 ( FIG. 6 ) is arranged directly above the emitter electrode E0 ( FIG. 6 ). In the fourth embodiment, the second-layer collector wiring C2 and the collector bump CB are arranged directly above the emitter electrode E0 via the interlayer insulating film 41 .

The second-layer collector wiring C2 is electrically connected to the first-layer collector wiring C1 arranged on both sides of the mesa structure 30 via the inside of the third via hole 45 provided in the interlayer insulating film 41 .

Next, the excellent effect of the power amplifier module of the fourth embodiment will be described. In the fourth embodiment, a conductor from the heat source 37 passing through the substrate 20, the collector electrode C0, the first-layer collector wiring C1, the third through-hole 45, and the second-layer collector wiring C2 to reach the collector bump is formed. The third thermal path TP3 of the block CB (Fig. 10). In the third embodiment, the heat generated by the heat source 37 is transferred on the substrate 20 and reaches the collector electrode C0 ( FIG. 6 ), and then passes through the collector electrode C0 ( FIG. 5A) Passes in the in-plane direction and reaches the collector bump CB. In the fourth embodiment, the collector electrode C0 arranged on both sides of the heat source 37 is connected to the collector bump CB arranged directly above it via the conductor in the third through hole 45 . Therefore, the third thermal path TP3 is shorter than the configuration of the third embodiment. As a result, the heat dissipation efficiency from the heat source 37 via the collector bump CB can be improved.

Furthermore, in the fourth embodiment, the second thermal path TP2 including the heat dissipation pad T0 ( FIG. 9B ) is also used as the heat dissipation path in the same manner as in the power amplifier module ( FIG. 1B ) of the first embodiment. Therefore, similarly to the case of the first embodiment, heat dissipation efficiency can be improved.

[Modification of the fourth embodiment] Next, a modified example of the fourth embodiment will be described with reference to FIGS. 11A and 11B . 11A and 11B are cross-sectional views of the power amplifier module according to a modified example of the fourth embodiment, corresponding to the cross-sectional views of the power amplifier module of the fourth embodiment in FIG. 9B and FIG. 10 . In this modified example, the thermal conductivity of interlayer insulating film 41 in region 41b where first-layer emitter wiring E1 and second-layer collector wiring C2 overlap in plan view is higher than that of other regions.

In this modified example, a sixth layer that passes from the heat source 37 through the emitter electrode E0, the first-layer emitter wiring E1, the interlayer insulating film 41 of the region 41b, and the second-layer collector wiring C2 to reach the collector bump CB is formed. Thermal path TP6. Thus, the heat dissipation efficiency can be further improved compared with the fourth embodiment.

[Fifth Embodiment] Next, referring to FIG. 12, the power amplifier module of the fifth embodiment will be described. FIG. 12 is a cross-sectional view of the power amplifier module of the fifth embodiment. The power amplifier module of the fifth embodiment includes a module substrate 80 and a semiconductor chip 60 mounted on the module substrate 80 . The semiconductor wafer 60 has the same configuration as that of the power amplifier module of the fourth embodiment or a modified example of the fourth embodiment.

The module substrate 80 has a first pad 81 and a second pad 82 on one side (first side) 80 a, and has a third pad 83 on the other side (second side) 80 b. The first pad 81 is electrically connected to the third pad 83 via a plurality of via conductors 85 penetrating from the first surface 80a to the second surface 80b. The module substrate 80 further includes an inner layer conductor 86 disposed on the inner layer. The inner layer conductor 86 is electrically connected to the first pad 81 and the third pad 83 via the via conductor 85 . The inner layer conductor 86 functions as a ground plane, for example. In a plan view, the inner layer conductor 86 partially overlaps the second pad 82 . The thermal conductivity of the insulating film 87 between the inner layer conductor 86 and the second pad 82 is higher than that of other insulating parts of the module substrate 80 .

The emitter bump EB and the collector bump CB of the semiconductor wafer 60 are bonded to the first pad 81 and the second pad 82 , respectively. The third pad 83 is bonded to, for example, a ground pad of a printed circuit board such as a motherboard. The ground pad is connected to a large ground plane in the printed circuit board. This ground plane acts as a heat sink.

Next, the excellent effects of the power amplifier module of the fifth embodiment will be described. The heat generated by the heat source 37 of the semiconductor wafer 60 is transferred to the emitter bump EB through the second thermal path TP2 ( FIG. 9B ) and the fifth thermal path TP5 ( FIG. 9B ). The heat transferred to the emitter bump EB is further dissipated to the outside of the power amplifier module through the seventh thermal path TP7 including the first pad 81 , the via conductor 85 and the third pad 83 .

And, the heat generated by the heat generating source 37 is transferred to the collector bump CB through the third heat path TP3 ( FIG. 12 ). The heat transferred to the collector bump CB is dissipated to the outside of the power amplifier module through the eighth thermal path TP8 including the second pad 82, the insulating film 87, the inner conductor 86, the via conductor 85, and the third pad 83. .

Since the second pad 82 partially overlaps the inner layer conductor 86 , the thermal resistance of the eighth thermal path TP8 can be reduced. In addition, by making the thermal conductivity of the insulating film 87 arranged between the second pad 82 and the inner layer conductor 86 higher than that of other insulating parts of the module substrate 80, the thermal resistance of the eighth thermal path TP8 can be increased. Further decrease. Accordingly, the efficiency of heat dissipation from the heat source 37 of the semiconductor wafer 60 to the outside of the power amplifier module can be improved. In the fifth embodiment, the thermal conductivity of the entire region of the insulating film 87 is made higher than that of other insulating parts, but it is also possible to make the region of the insulating film 87 where the inner layer conductor 86 and the second pad 82 overlap. At least one portion has a higher thermal conductivity than the other insulating portions.

In the fifth embodiment, a wafer having the same configuration as the power amplifier module of the fourth embodiment is used as the semiconductor wafer 60, but it is also possible to use any one of the embodiments in the first to third embodiments or A chip having the same configuration as the power amplifier module of the modified example.

[Sixth Embodiment] Next, referring to FIG. 13 and FIG. 14 , the power amplifier module of the sixth embodiment will be described. The power amplifier module of the sixth embodiment includes a transistor Q having the same structure as the transistor ( FIG. 2 , FIG. 3 ) of the power amplifier module of the second embodiment. Hereinafter, description of the detailed configuration of the transistor Q will be omitted.

Fig. 13 is a plan view of main parts of the output stage amplifier of the power amplifier module of the sixth embodiment. In FIG. 13 , the components of the transistor Q are assigned the same reference numerals as those added to the corresponding components of the power amplifier module ( FIGS. 2 and 3 ) of the second embodiment. A plurality of HBT units 70 are arranged side by side. Each HBT unit 70 includes a transistor Q ( FIG. 2 ), a ballast resistor R, and a DC cut capacitor C . The direction in which the plurality of HBT cells 70 are arranged is perpendicular to the long side direction of the emitter electrode E0 of the transistor Q.

The second-layer emitter wiring E2 and the emitter bump EB extend in the direction in which the plurality of HBT cells 70 are arranged, and are shared by the plurality of transistors Q. FIG. In this way, the emitter bump EB overlaps the emitter electrodes E0 of the plurality of HBT cells 70 . The emitter bump EB also overlaps the pad T0 for heat dissipation and the heat conduction film T1 arranged in each HBT unit 70 .

The first-layer collector wiring C1 has a comb-like planar shape. Comb-teeth portions of the first-layer collector wiring C1 are arranged on both sides of the emitter electrode E0. The collector connection portion C1a arranged outside the second-layer emitter wiring E2 extends in the direction in which the plurality of HBT cells 70 are arranged, and connects the plurality of comb-shaped portions of the plurality of HBT cells 70 to each other. The second-layer collector wiring C2 is arranged to overlap the collector connection portion C1a.

A ballast resistor R and a DC cut capacitor C are arranged corresponding to each of the plurality of transistors Q. A first-layer base wiring B1 is connected to the base electrode B0. The first-layer base wiring B1 is led out to a region where the emitter bump EB is not arranged, and is connected to the second-layer bias wiring L2 via a ballast resistor R. Furthermore, the first-layer base wiring B1 functions as a lower electrode of the DC cutting capacitor C. As shown in FIG. The second-layer base wiring B2 arranged to partially overlap the first-layer base wiring B1 functions as an upper electrode of the DC cutting capacitor C. As shown in FIG. For example, the entire area of the second-layer base wiring B2 is arranged inside the first-layer base wiring B1 in plan view.

Fig. 14 is an equivalent circuit diagram of the output stage of the power amplifier of the sixth embodiment. A plurality of HBT units 70 are connected in parallel. The HBT unit 70 includes a transistor Q, a ballast resistor R and a DC cut capacitor C. Transistors Q of a plurality of HBT units 70 are connected in parallel. The power supply voltage Vcc is applied to the collector of the transistor Q via an inductor. The collector of the transistor Q is connected to the output terminal RFo of the high-frequency signal. The emitter of transistor Q is grounded.

A high frequency signal is input to the base of the transistor Q via the DC cut capacitor C. The bias current is given to the base via the ballast resistor R. In FIGS. 13 and 14 , an example in which four HBT units 70 are connected in parallel is shown, but the number of HBT units 70 connected in parallel is not limited to four. Generally, not less than ten but not more than forty HBT units 70 are connected in parallel.

Next, the excellent effects of the power amplifier of the sixth embodiment will be described. The power amplifier of the sixth embodiment uses a transistor Q having the same configuration as that of the power amplifier module of the second embodiment. Therefore, effective heat dissipation from the heat generation source of the transistor Q can be performed.

Furthermore, in the sixth embodiment, the pad T0 for heat dissipation and the heat conduction film T1 are arranged on the extension line after the emitter electrode E0 is extended in the longitudinal direction. Therefore, the number of HBT cells arrayed in the width direction of the emitter electrode E0 can be shortened compared to the case where the spacer T0 for heat dissipation and the heat conduction film T1 are arranged on both sides of the emitter electrode E0 ( FIG. 1A ). Total size of 70.

[Seventh Embodiment] Next, referring to FIG. 15, a power amplifier of a seventh embodiment will be described. The power amplifier of the seventh embodiment includes a transistor Q having the same structure as the transistor of the power amplifier module of the third embodiment ( FIG. 4 , FIG. 5A , FIG. 5B , and FIG. 6 ). Hereinafter, description of the detailed configuration of the transistor Q will be omitted.

Fig. 15 is a plan view of main parts of the output stage amplifier of the power amplifier module of the seventh embodiment. In FIG. 15 , the components of the transistor Q are denoted by the same reference numerals as those added to the corresponding components of the power amplifier module ( FIG. 4 ) of the third embodiment. Like the sixth embodiment ( FIG. 13 ), a plurality of HBT units 70 are arranged side by side. Each HBT unit 70 includes a transistor Q, a ballast resistor R, and a DC cut capacitor C. The connection configuration of the transistor Q, the ballast resistor R, and the DC cutoff capacitor C is the same as that of the sixth embodiment.

The collector electrode C0 has a comb-like planar shape. Comb-teeth portions of the collector electrode C0 are arranged on both sides of the emitter electrode E0. Adjacent comb tooth portions of two mutually adjacent HBT units 70 are continuous and integrated. The first-layer collector wiring C1 substantially overlaps the collector electrode C0 , and the first-layer collector wiring C1 also has a comb-like planar shape.

In the seventh embodiment, also in the same manner as in the sixth embodiment, the second layer emitter wiring E2 and the emitter bump EB are shared by a plurality of HBT units 70 .

Next, the excellent effect of the power amplifier module of the seventh embodiment will be described. Since the power amplifier module of the seventh embodiment uses the transistor Q having the same structure as that of the power amplifier module of the third embodiment, effective heat dissipation from the heat source of the transistor Q can be performed.

[Modification of the seventh embodiment] Next, a modified example of the seventh embodiment will be described. In the seventh embodiment, a transistor having the same structure as that of the power amplifier module of the third embodiment is used as the transistor Q constituting the HBT unit 70 . As another configuration, a transistor having the same structure as that of the power amplifier module ( FIGS. 7A and 7B ) according to the modified example of the third embodiment may be used.

[Eighth Embodiment] Next, referring to FIG. 16, the power amplifier module of the eighth embodiment will be described. The power amplifier module of the eighth embodiment includes a transistor Q having the same structure as the transistor of the power amplifier module of the fourth embodiment ( FIG. 8 , FIG. 9A , FIG. 9B , FIG. 10 ). Hereinafter, description of the detailed configuration of the transistor Q will be omitted.

Fig. 16 is a plan view of main parts of the output stage amplifier of the power amplifier module of the eighth embodiment. In FIG. 16 , the components of the transistor Q are denoted by the same reference numerals as those added to the corresponding components of the power amplifier module ( FIG. 8 ) of the fourth embodiment. Like the sixth embodiment ( FIG. 13 ), a plurality of HBT units 70 are arranged side by side. Each HBT unit 70 includes a transistor Q, a ballast resistor R, and a DC cut capacitor C. The connection configuration of the transistor Q, the ballast resistor R, and the DC cutoff capacitor C is the same as that of the sixth embodiment.

The collector electrode C0 has a comb-like planar shape. Comb-teeth portions of the collector electrode C0 are arranged on both sides of the emitter electrode E0. Adjacent comb tooth portions of two mutually adjacent HBT units 70 are continuous and integrated. The first-layer collector wiring C1 substantially overlaps the collector electrode C0 , and the first-layer collector wiring C1 also has a comb-like planar shape.

The second-layer collector wiring C2 and the collector bump CB are shared by a plurality of HBT cells 70 . The second-layer emitter wiring E2 and the emitter bump EB extend along the arrangement direction of the plurality of HBT units 70 and are shared by the plurality of HBT units 70 .

Next, the excellent effects of the power amplifier module of the eighth embodiment will be described. Since the power amplifier module of the eighth embodiment uses the transistor Q having the same structure as that of the power amplifier module of the fourth embodiment, effective heat dissipation from the heat source of the transistor Q can be performed.

[Modification of Eighth Embodiment] Next, a modified example of the eighth embodiment will be described. In the eighth embodiment, a transistor having the same structure as that of the power amplifier module of the fourth embodiment is used as the transistor Q constituting the HBT unit 70 . As another configuration, a transistor having the same structure as that of the power amplifier module ( FIGS. 11A and 11B ) according to the modified example of the fourth embodiment may be used.

Each of the above-mentioned embodiments is an example, and it is needless to say that partial replacement or combination of the configurations shown in different embodiments is possible. For the same function and effect brought about by the same configuration of multiple embodiments, each embodiment is not mentioned one by one. Also, the present invention is not limited to the above-mentioned embodiments. For example, it is obvious to those skilled in the art that various changes, improvements, combinations, etc. can be made.

20: Substrate 21: active area 22: Component separation area 30: Mesa structure 31: collector layer 32: Base layer 33: emitter layer 34: Emitter contact layer 36: Emitter area 37: heat source 40, 41: interlayer insulating film 41a: The area where the emitter wiring and the collector electrode of the second layer overlap when viewed from above 41b: The area where the emitter wiring of the first layer overlaps the collector wiring of the second layer when viewed from above 42: Protective film 43: First through hole 44: Second through hole 45: The third through hole 51: column 52: Solder 60: Semiconductor wafer 70: HBT unit 80:Module substrate 80a: first side 80b: Second side 81: The first pad 82: Second pad 83: The third pad 85: Through hole conductor 86: inner layer conductor 87: insulating film B0: base electrode B1: The first layer of base wiring B2: The second layer base wiring C: DC cut capacitor C0: collector electrode C1: The first layer collector wiring C1a: collector connection part C2: second layer collector wiring CB: collector bump E0: emitter electrode E1: The first layer of emitter wiring E2: The second layer emitter wiring EB: emitter bump L2: second layer bias wiring Q: Transistor R: ballast resistance T0: gasket for heat dissipation T1: thermal conductive film TP1: First thermal path TP2: Second thermal path TP3: Third Thermal Path TP4: Fourth thermal path TP5: Fifth Thermal Path TP6: sixth thermal path TP7: seventh thermal path TP8: eighth thermal path

[FIG. 1A] is an emitter electrode, a base electrode, and a collector electrode made of metal connected to the emitter layer, the base layer, and the collector layer of the transistor of the power amplifier module of the first embodiment, and [ FIG. 1B ] is a plan view of wiring made of metal on an upper layer than these electrodes, and [ FIG. 1B ] is a cross-sectional view at the dot chain line 1B-1B in FIG. 1A . [ FIG. 2 ] is an emitter electrode, a base electrode, and a collector electrode made of metal connected to the emitter layer, the base layer, and the collector layer of the transistor of the power amplifier module of the second embodiment, and This is a plan view of wiring made of metal on an upper layer than these electrodes. [FIG. 3] It is a cross-sectional view at the point chain line 3-3 of FIG. 2. [FIG. [FIG. 4] An emitter electrode, a base electrode, and a collector electrode made of metal connected to the emitter layer, the base layer, and the collector layer of the transistor of the power amplifier module of the third embodiment, and This is a plan view of wiring made of metal on an upper layer than these electrodes. [ FIG. 5A ] is a sectional view at the dotted line 5A- 5A in FIG. 4 , and [ FIG. 5B ] is a sectional view at the dotted line 5B- 5B in FIG. 4 . [ Fig. 6 ] is a cross-sectional view at a dot chain line 6-6 in Fig. 4 . [ FIG. 7A ] and [ FIG. 7B ] are sectional views of a power amplifier module according to a modified example of the third embodiment. [ FIG. 8 ] is an emitter electrode, a base electrode, and a collector electrode made of metal connected to the emitter layer, the base layer, and the collector layer of the transistor of the power amplifier module of the fourth embodiment, and This is a plan view of wiring made of metal on an upper layer than these electrodes. [ FIG. 9A ] is a cross-sectional view at the dotted line 9A-9A in FIG. 8 , and [ FIG. 9B ] is a cross-sectional view at the dotted line 9B-9B in FIG. 8 . [ Fig. 10 ] It is a cross-sectional view at the dot chain line 10-10 in Fig. 8 . [ FIG. 11A ] and [ FIG. 11B ] are sectional views of a power amplifier module according to a modified example of the fourth embodiment. [ Fig. 12 ] is a sectional view of a power amplifier module of a fifth embodiment. [ Fig. 13 ] It is a plan view of main parts of the output stage amplifier of the power amplifier module of the sixth embodiment. [ Fig. 14 ] is an equivalent circuit diagram of the output stage of the power amplifier of the sixth embodiment. [ Fig. 15 ] It is a plan view of main parts of the output stage amplifier of the power amplifier module of the seventh embodiment. [ Fig. 16 ] It is a plan view of main parts of the output stage amplifier of the power amplifier module of the eighth embodiment.

21: active area

36: Emitter area

B0: base electrode

C0: collector electrode

C1: The first layer collector wiring

C1a: collector connection part

C2: second layer collector wiring

CB: collector bump

E0: emitter electrode

E1: The first layer of emitter wiring

E2: The second layer emitter wiring

EB: emitter bump

T0: gasket for heat dissipation

T1: thermal conductive film

Claims (5)

A power amplifier module, which has: a substrate, including a conductive active area in the upper surface, and an insulating element separation area adjacent to the active area; a collector layer, a base layer, and an emitter layer, according to The sequential build-up layer is on the active area; the collector electrode partially overlaps the active area when viewed from above, and is electrically connected to the active area; an interlayer insulating film covers the collector layer, the base layer, and the emitter layer and the collector electrode; and a collector bump, which is disposed on the interlayer insulating film, is electrically connected to the collector electrode through a through hole provided in the interlayer insulating film, and is connected to the emitter layer in plan view. The region where the emitter current flows, that is, the emitter region partially overlaps. The power amplifier module according to claim 1, wherein the thermal conductivity of at least a part of the interlayer insulating film in the overlapping region of the emitter region and the collector bump is higher than that of other regions of the interlayer insulating film. The power amplifier module according to claim 1 or 2, further comprising: a pad, thermally coupled with the element separation region; and an emitter bump, arranged on the interlayer insulating film and electrically connected to the emitter layer, The emitter bump is partially overlapped with the spacer in plan view, and the emitter bump is electrically connected to the spacer through another via hole provided in the interlayer insulating film. The power amplifier module according to claim 3, further having a module substrate on which a chip including the substrate is installed, and the module substrate has: a first pad arranged on the first surface and connected to the emitter bump electrical connection; the second pad is configured on the first surface and is electrically connected to the collector bump; The third pad is arranged on the second surface opposite to the first surface; a through-hole conductor reaches from the first surface to the second surface, and electrically connects the first pad to the third pad; and an inner layer conductor arranged in the inner layer and electrically connected to the via conductor, and partially overlapping the second pad. The power amplifier module according to claim 4, wherein the thermal conductivity of at least a part of the insulating film between the inner layer conductor and the second pad in the area where the inner layer conductor overlaps with the second pad is higher than that of the module The thermal conductivity of the insulating portion in other regions of the substrate is high.

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