JP2005310923A - Semiconductor device and chip packaging method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an SiC power device which is reduced in size and is tolerable to a large current flow, by solving the problem, wherein when a horizontal FET using an SiC semiconductor, electrodes and interconnections exist on top of a chip, and therefore the interconnections need to be formed thick, to avoid power loss and electromigration in order to cause a large current to flow in the FET, which leads to another problem, wherein the interconnections occupy most of the chip area, thus resulting in the increase in the size of the chip. <P>SOLUTION: On top of the SiC chip, a plurality of transistor groups are distributed and distributed drain pads and source pads are formed for individual transistor groups. On an insulator substrate, a plurality of drain pads and a plurality of source pads are so formed that they are mirrored images of the distributed drain pads and source pads on the SiC chip. All the drain pads are packed into a single integrated drain pad, and all the source pads are packed into a single integrated source pad by internal interconnections. Due to this structure, an active region inside the chip where the FETs exist can be formed wide, resulting in reduction in the size of the chip itself. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

The present invention relates to a semiconductor device and a chip mounting method in which a power device module is miniaturized by avoiding the enlargement of wiring in a SiC semiconductor power device.
Examples of power devices using Si semiconductors include MOS-FETs, junction FETs, and IGBTs. There are two types of power FETs, a horizontal type in which current flows in the horizontal direction and a vertical type in which current flows in the vertical direction.

  In the horizontal type in which current flows in the horizontal direction, the drain electrode, the gate electrode, and the source electrode are all provided on the upper surface of the chip. The channel is on the semiconductor surface and current flows laterally from the drain to the source. In the horizontal type, the p region, the n type region, and the electrodes are all on the surface, so the wafer process is simple, easy to manufacture, and easy to mount. Low on-resistance.

  In the vertical FET, the source electrode and the gate electrode are on the front surface, but the drain electrode is on the back surface of the chip, and current flows vertically. Since the vertical type can take a wide depletion layer before and after the pn junction, the breakdown voltage at the time of off can be increased. Since there is no drain wiring on the surface, the area occupied by the wiring can be reduced. However, the structure is complicated and has a drawback of high on-resistance and high manufacturing cost. Most FETs which are Si semiconductors and have a high withstand voltage when turned off are vertical type.

  An IGBT (isolated gate bipolar transistor) is obtained by adding a p-type layer in the vicinity of the drain electrode of a vertical FET. Holes in the p-type layer flow upward, electrons from the n-type layer flow downward, and carriers of both conductivity types contribute to the current, so that a larger current can flow than the FET. Bipolar is used because both electrons and holes are used as carriers.

  At present, it is said that the most common power device of Si semiconductor as a switching element for driving a motor or the like can handle a high voltage and large current of 600 V or more and 60 A or more by IGBT. In addition to the chip, the cooling mechanism is optimally devised. Since the Si semiconductor deteriorates when the heat resistance reaches a temperature of 150 ° C. due to the neck, it is necessary to increase heat dissipation and cool with cooling water.

  However, power devices with higher voltages and higher currents are desired. As a result, in the Si semiconductor, the on-resistance increases as the breakdown voltage increases, and the loss increases. An SiC power device can meet the demand.

Japanese Patent Application Laid-Open No. 2002-158322 “Semiconductor Module”

    Patent Document 1 discloses a Si power device in which a heat sink is improved by attaching a hollow heat sink to a chip and passing cooling water through the heat sink.

  SiC semiconductors have excellent heat resistance, and can be used at high temperatures that cannot be used with Si semiconductors. For example, it is said to operate even at a high temperature of about 250 ° C. If so, the cooling mechanism can be further simplified with a SiC semiconductor. In addition, SiC has a dielectric breakdown electric field about 10 times that of Si. Therefore, even a small element can be a high breakdown voltage device.

  Since SiC has a much higher breakdown electric field than Si, it should be possible to provide a power FET with a high withstand voltage during off-state. If a SiC semiconductor is used, it will be possible to produce a horizontal type with a high breakdown voltage and a large current. However, in the horizontal type, all of the gate electrode, the source electrode, the drain electrode, the gate wiring, the source wiring, and the drain wiring exist on the surface of the chip. To pass a large current, the cross-sectional area of the wiring must be increased so that electromigration does not occur. If a large number of wirings having a large cross-sectional area are formed on the surface, the area of the chip becomes excessive. If the chip is large, the device including the package becomes large, which is not preferable.

  In a conventional power FET, gate electrodes, source electrodes, drain electrodes, and the like of many FET units are aggregated to form gate pads, source pads, and drain pads, which are connected to package lead pins by wire bonding. Therefore, the area for wiring laying becomes enormous, and wiring may occupy most of the chip area.

  FIG. 1 is a diagram showing an electrode and wiring distribution of a Si power FET according to a conventional example. A comb-shaped gate region (p-Si), a drain region (n-Si), and a source region (n-Si) are formed by diffusion and ion implantation on the upper surface of the chip 2, and the comb-shaped gate electrodes 7, 7,. , Source electrodes 8, 8,..., Drain electrodes 9, 9,. Although not shown in the figure, the drain, source, and gate regions are portions under the respective electrodes.

  Since it is necessary to flow as much current as possible in the power device, the gate, source, and drain are formed in a parallel region extending horizontally. Although the channel length is short, the channel width becomes wide. The channel length determines the response time and withstand voltage, but is not related to the current, and is about several μm to several tens of μm. The channel width is proportional to the current, so it needs to be long. In FIG. 1, comb electrodes are combined extending from both sides, but the total length of the facing portions of the comb electrodes is the channel width. Here, only a set of six electrodes is shown, but there are actually many more. Here is a brief description. In order to flow as much current as possible, the channel width of the facing portion of the comb electrode may be several cm to m.

  A current flows laterally through the comb-shaped drain electrode 9 and source electrode 8. Since current flows at a uniform density between channels, the comb-shaped electrodes 9 and 8 have a small current at the tip and a large current at the root. A drain assembly wiring 29 is a combination of comb-shaped drain electrodes 9, 9. Since all the line segment-like drain electrodes 9 are orthogonal to each other and a current larger than each drain electrode flows, a wide collective wiring (aluminum) 29 is formed. The same applies to the source electrode 8, and a source aggregate wiring 28 connected to all the thin line segment source electrodes 8, 8... Is provided. This is also a thick wiring because a large current flows.

  There is also a gate assembly wiring 27 for the gate electrode 7. Since the current flowing through the gate electrode is small, the aggregate wiring 27 does not have to be very thick. Although the source aggregate wiring 28 covers the gate electrode 7, there is actually an interlayer insulating film between them, and the gate electrode and the source electrode are electrically insulated.

  A drain pad 39 is provided so as to partially overlap the drain collective wiring 29. It is a wire bonding pad for connecting to a lead pin (not shown) of the package. A source pad 38 is provided so as to overlap a part of the source aggregate wiring 28. This is also a pad for wire bonding for connecting to a lead pin (not shown) of the package. A gate pad 37 is also provided on the gate aggregate wiring 27. Since the pad serves as a terminal for wire bonding, it is provided at an appropriate place on the chip.

  As can be seen from this figure, fine comb-shaped drain electrode 9, source electrode 8 and gate electrode 7 exist in parallel in the portion where each FET element exists. It is a region that operates as a transistor. The collective wirings 29, 28, and 27 for collecting these electrodes are provided in a region different from the operation region. Also, pads for wire bonding are required separately from wiring, and an area is also required for this purpose. Therefore, the entire surface of the semiconductor chip 2 does not become an operation area. The collective wiring is a group of many electrodes. Since there is only one pad per chip, all the electrodes must be bonded together in the collective wiring. As the number of FET units increases, wiring becomes more complicated and disturbed. Therefore, the area occupied by the wiring is increasing. It is an object of the present invention to reduce the area occupied by wiring in a power device, and to provide a smaller device with higher output.

  In one chip, the collective wiring of each electrode is not combined into one, but distributed pads in which a plurality of electrodes are aggregated are provided in a distributed manner, and individual electrodes are connected to the plurality of distributed aggregate pads through appropriate paths. . Thereby, the wiring area required on the chip is reduced. Do not directly connect the chip's distributed collective wiring and package pins, but distribute the distributed pad on the surface of a separate wiring board so that it is mirror-symmetrical, and the drain pad, source pad, and gate pad on the periphery. In addition, a three-dimensional substrate wiring is provided inside, thereby collecting a plurality of collective wirings. The chip is connected to the wiring board to connect the corresponding distributed drain pad, source pad, and gate pad. The integrated drain pad, source pad, and gate pad of the wiring board are wire bonded to be connected to the pins. By doing so, the area occupied by the wiring on the chip can be reduced. The chip can be downsized accordingly. Alternatively, even if the size of the chip is the same, the operating region operating as an FET can be increased, and a higher output device can be obtained.

  A plurality of pads are formed by collecting a plurality of drain electrode assembly pads, source electrode assembly pads, gate electrode assembly wirings, and pads locally on the chip, having separate wirings and having pads in mirror-symmetrical positions. Are integrated into one substrate pad by substrate wiring, and are bonded to the lead pins of the package by wire bonding. This reduces the amount of collective wiring in the chip. The width of the collective wiring can also be made narrower. Further, the degree of freedom of the position occupied by the FET group is higher than that of the conventional one.

[Example 1: Distributed narrow pad]
A distributed transistor wiring structure according to the first embodiment of the present invention will be described with reference to FIG. This is a simplified example in which transistor groups are provided in three locations. This is an extremely simple example, and a group of transistors may be provided by being distributed in three or more places. From this point of view, the conventional example shown in FIG. 1 has only one transistor group.

  In FIG. 2, they will be called A group, B group, and C group in order from the top. In group A, drain and source n-type regions and gate p-type regions are provided in parallel. There is a drain pad 39 on the left side, and two drain electrodes 9, 9 extend in parallel from the drain pad 39. There are two gate electrodes 7 between them, and a source electrode 8 in the center. The gate electrodes 7, 7 extend long and are connected to the gate assembly wiring 27 on the right side of the chip. The source electrode 8 extends to the right and is connected to the source pad 38.

  The same applies to the group B. The gate electrodes 7 and 7 and the source electrode 8 are sandwiched between the two drain electrodes 9 and 9. The drain electrode is connected to the drain pad 39. The group B drain pads 39 are separated from the group A drain pads. There are also gate electrodes 7 and 7 and a source electrode 8 between the drain electrodes of the A group and the B group. The gate electrodes 7 are connected to a common gate aggregate wiring 27. One gate pad 37 is provided in the gate aggregate wiring 27. Since a large current does not flow through the gate wiring, the aggregate wiring of the gate electrodes can be thin. The source electrode 8 is connected to the group B source pads 38.

The same applies to the group C, and the drain electrodes 9 and 9 are connected to independent drain pads 39. The source electrode is connected to an independent source pad 38.
In this way, the drain electrode, the source electrode, and the gate electrode are arranged in a comb shape such that the drain electrode, the source electrode, and the gate electrode are parallel to each other and partially engaged with each other. The collective wiring becomes small (or disappears) and is connected to pads 38,..., 39,. There are a plurality of pads 38,..., 39,. .., 8, 8..., A large number of wirings are required, so that a large amount of the upper surface of the chip is remarkably reduced. Unlike the conventional example where the chip area is largely consumed due to the wiring distribution, the chip area can be reduced by narrowing the drain wiring and the source wiring.

  Here, only the gate electrode forms a collective wiring and is integrated into one gate pad 37. This is possible because the distribution of transistor groups is simple. When there are more transistor groups and the distribution is complicated, a plurality of pads can be provided for the gate electrode. As a result, the area of the gate aggregate wiring can be reduced.

  FIG. 3 shows a longitudinal sectional view of a portion including the drain electrode and the source electrode in FIG. FIG. 4 shows a longitudinal sectional view of a portion including the source pad. FIG. 5 shows a longitudinal sectional view of a portion including the drain pad.

The vertical sectional view of FIG. 3 shows the vertical structure of a lateral FET composed of a drain / gate / source region. A p-type layer 6 is epitaxially grown on an n-type layer 5 of a semiconductor crystal, and n ⁺ -regions and p ⁺ -regions are generated at appropriate portions by ion implantation or thermal diffusion. These are the parts that become the gate, drain, and source. A gate electrode 7, a drain electrode 9, and a source electrode 8 are provided on these regions. In the case of a junction type FET, the gate electrode and the p ⁺ type crystal layer are in ohmic contact. In the case of SiC, a junction type transistor is also promising.

  Of course, a MOS-FET can be used. In the case of a MOS-FET, an insulating film is formed on the gate. The present invention can be applied to either a junction type or a MOS type. 3 to 5 show the junction type, but in the case of MOS, a gate insulating layer is formed instead of the p-region.

  Five layers of oxide films are provided on the semiconductor crystal. Let it be C, E, F, K, H from the bottom. Wiring is embedded in the oxide film. The lowermost oxide film C has the electrodes 8, 9, and 7 described above. The gate electrode 7, the source electrode 8, and the drain electrode 9 extend in a direction perpendicular to the paper surface. A gate wiring 27 is provided in the gate electrode 7, a source wiring 28 is provided in the source electrode 8, and a drain wiring 29 is provided in the drain electrode 9 in the oxide film E immediately above.

  Further, as shown in FIG. 4, through holes 48, 48... Are formed to connect neighboring source electrodes 8, 8, and a source pad 38 is provided thereon. As shown in FIG. 5, through-holes 49, 49... Are formed to connect the nearest drain electrodes 9, 9, and a drain pad 39 is provided thereon so as to be exposed to the top.

  Such a wiring structure can be formed by repeating photolithography, etching, oxidation, aluminum sputtering, and vapor deposition. The wiring of the source electrode is more complicated. This is because it is necessary to pass over the drain electrode. As a result, a plurality of equivalent drain pads and source pads are formed on the upper surface of the chip. There is no wiring that gathers them together.

In this way, a plurality of independent pads can be formed, but the wiring for bringing them together is provided in a separate substrate. The substrate may be a plastic substrate provided with internal wiring, or may be a ceramic insulator substrate such as AlSiC or Al ₂ O ₃ .

  FIG. 6 shows the surface of the wiring board 60 corresponding to the chip 2 of FIG. This is a surface to be bonded to the upper surface of the chip 2. Dispersion pads are arranged so as to be mirror-symmetrical with the pads on the chip so that the pads make good contact when they are brought together. In FIG. 6, three distributed source pads 58, 58, 58 are provided side by side in the central portion in the vertical direction. Three distributed drain pads 59, 59, 59 are provided on the right end side by side on a straight line. A gate pad 57 is formed at the left end.

  There are a plurality of distributed pads for the source and drain. A plurality of dispersion pads may also be provided for the gate. A single substrate gate pad 67, a substrate source pad 68, and a substrate drain pad 69, which are a collection of them, are provided at the end of the substrate surface. This is a wire bonding pad. Inside the substrate 60 is a conductor source wire 88, and the distributed source pads 58, 58, 58 are connected to a single substrate source pad 68. Similarly, there is a drain wiring 89 inside the substrate 60, and the distributed drain pads 59, 59, 59 are connected to a single substrate drain pad 69.

  Thus, in the chip / wiring board structure of the present invention, the substrate is provided with a plurality of drain, source, and gate pads at positions that are mirror-symmetrical with the chip pads. The drain pads are combined into one by the internal wiring. The combined one is coupled to a unified substrate drain pad, a unified substrate source pad, and a unified substrate gate pad provided at the periphery of the substrate. That is, the substrate is an insulating plate having individual pads, internal wiring, unified pads, and the like.

  When the chip is attached to the substrate, the corresponding pads are bonded, so that the drain and source wirings are all integrated into one drain pad and source pad by the internal wiring of the substrate.

  The embodiment of FIGS. 2 and 6 shows a structure in which there are only three transistors and only 3 × 2 = 6 pads in order to clearly show detailed electrodes (drain, source, and gate). This is a simplified example. In practice, more complex structures can be taken.

[Example 2: A plurality of drain pads and source pads arranged in the same direction]
FIG. 7 shows an example in which a plurality of FET unit drain electrodes D, D (9)... Are combined in a drain pad 39 and a plurality of FET source electrodes S, S (8). This joins five drain electrodes D to one drain pad 39. The source pads 38 are arranged in the vertical direction, and the drain pads 39 are also arranged in the vertical direction. This is a parallel arrangement type in which drain pads and source pads are arranged vertically. The pad area is larger than that of FIG. Since the multilayer wiring is formed by stacking a large number of oxide films as shown in FIGS. 3 to 5, the area of the uppermost pad can be arbitrarily determined. Here, the pad area is increased in order to increase the bonding accuracy and reduce the current density.

  A number of drain electrodes, source electrodes, and gate electrodes exist in parallel under the pad. The gate electrodes G, G... Are combined into one by wiring embedded in the oxide film. The gate electrode may be connected to a plurality of gate pads. This shows only a part of 2 × 2, but actually, a large number of drain pads and source pads are arranged on one chip vertically and horizontally. For example, the pads are arranged in parallel vertically and horizontally, such as 8 × 8 or 16 × 16.

[Example 3: A plurality of alternately arranged drain pads and source pads]
FIG. 8 shows an example in which a plurality of FET unit drain electrodes D and D (9) are combined into a drain pad 39 and a plurality of source electrodes S and S (8) are combined into a source pad 38. This is also a pad with a large area. This shows an example in which drain pads and source pads are alternately arranged in a staggered pattern. There are parallel drain electrodes D, gate electrodes G, and source electrodes S extending in a straight line, and the plurality of electrodes are joined to the dispersion pad by multilayer wiring as in FIG. In this case, the source pad 38 and the drain pad 39 can be alternately arranged. This also indicates a minimum unit of 2 × 2, and a larger number of matrices are formed on one chip.

[Example 4: A plurality of alternately arranged matrix type drain pads and source pads]
FIG. 9 shows the structure of an alternating chip in which such a large number of pads are dispersed. In this configuration, drain pads 39 and source pads 38 are alternately arranged in an m × n matrix. Even in the case of the co-directional array type of FIG. Each drain pad 39 and source pad 38 is a collection of a plurality of drain electrodes and source electrodes of a plurality of transistors. Here, the drain pad is indicated by D and the source pad is indicated by S. A portion corresponding to the middle between the opposing drain pad and source pad is an operation region that functions as an FET. Here, there are source / gate / drain regions, and comb-shaped electrodes are alternately provided in parallel. In order to avoid complication, the individual electrodes are omitted in FIG. 9, and only the pads are drawn.

  A small pad may be provided as shown in FIGS. 2 and 6, but since a multi-layer wiring structure is used, a wide drain pad and source pad may be formed on the uppermost layer. By doing so, wide square drain pads and source pads are arranged in a matrix in the vertical and horizontal directions.

  In FIG. 9, drain pads 39 and source pads 38 are provided in staggered S, D, S, D... In each of 5 × 5 matrix elements. The number D of drain pads and the number S of source pads should be equal, and S = D. Here, one of the matrix elements is a gate pad (G) 37. There are one gate pad, twelve source pads, twelve drain pads, and twelve FET groups.

  FIG. 10 shows a plan view of the wiring board. This is a substrate made of an insulator, not a semiconductor, and has a pad on the surface, and is bonded and bonded to a distributed pad of the chip. A pad group is provided on the substrate in a mirror image symmetrical with the chip-like pad. Dispersed drain pads D, D... (59) and distributed source pads S, S... (58) are on the substrate 60, and a substrate drain pad 69, a substrate source pad 68, and a substrate gate pad 67 are provided at the periphery. Provided. Inside, the distributed drain pads 59, 59... Are integrated into the substrate drain pad 69. Similarly, the distributed source pads 58, 58... Are integrated into the substrate source pad 68. Only one gate pad is shown, but more may be used. The gate pad is also connected to the substrate gate pad 67 inside.

  FIG. 11 is a longitudinal sectional view showing a state in which the chip 2 is bonded to the wiring board 60 with the pad surfaces facing each other. Chip-type drain pads 39 and 39, source pads 38 and 38, gate pads and substrate-side drain pads 59 and 59, source pads 58 and 58, and gate pads are abutted and soldered, and the chip and substrate are bonded with an adhesive. Glued. An internal source line 88 couples the substrate source pad 68 and the distributed source pads 58, 58. The internal source wiring 89 couples the substrate drain pad 69 and the distributed drain pads 59, 59... In the substrate. An internal gate wiring 87 connects the distributed gate pad and the substrate gate pad 67.

[Embodiment 5: Bonding two chips having a plurality of alternately arranged drain pads and source pads to one wiring board]
12 (1) and 12 (2) show an embodiment in which two chips are bonded to one wiring board 60. FIG. The two chips may have exactly the same structure, or may have different structures. FIG. 12A shows a plan view of the substrate. FIG. 12 (2) shows a longitudinal sectional view. On the surface of the substrate 60, there are drain pads D, D... And source pads S, S. There are two of them with pads formed in a matrix. A wide substrate drain pad 69, a substrate source pad 68, a substrate gate pad 67 and the like are exposed at the edge of the substrate. There is one gate pad for each.

  Internal wirings 87, 88, and 89 are provided inside the substrate. The individual distributed drain pads 59 (D) are coupled to one substrate drain pad 69 by a drain wiring 89. The individual distributed source pads 58 (S)... Are coupled to the substrate source pads 68 by source wirings 88. Gate pad G is also coupled to substrate gate pad 67 by gate wiring 87.

  In the case of a ceramic substrate, such a structure can be manufactured by laminating a plurality of ceramic plates having wiring and through holes. In FIG. 12, the wiring inside the substrate seems to intersect, but since there is actually a depth, the wirings are not in contact with each other. Although it is somewhat complicated to make a structure as shown in FIG. 12 (2) on a ceramic substrate, such internal wiring can be easily manufactured by insert molding if plastic is used.

  As such, in the present invention, the chip and the wiring substrate are combined to form one device. Since the comb-shaped drain, gate, and source are provided along the line segment connecting the source pad and the drain pad, in the chip of FIGS. 9 and 12, the extending direction of these regions can be uniform.

  However, it is not uniform and the extension directions can be mixed. The drain and gate source electrodes may be comb-shaped parallel electrodes, which may extend in the x direction and may extend in the y direction. In addition, in some cases, an angle of 45 ° can be formed in the x direction.

  The reason why such a complicated structure of the FET group is possible is that there are a plurality of isolated pads. With such an arrangement in which the drain, gate, and source extending directions are alternately changed, even if all the drain electrodes and source electrodes are combined as shown in FIG. is there. However, if a large number of isolated pads are provided as in the present invention, it is possible to make it possible to have such a group of alternately parallel transistors.

If the number of gate pads is also distributed and more than one, the degree of design freedom is further increased.
Compared with the conventional example of FIG. 1, it can be seen that the present invention can omit most of the collective wirings 29 and 28 intersecting in the direction orthogonal to the unit comb electrodes. Since this portion has a large current, it is a thick wiring, but there is a great effect that it can be removed from the chip. If the vacant part is effectively used as an operation region of the FET, a device capable of flowing a larger current can be obtained.

  As for the degree of design freedom, the gate electrode can be taken out between the two pads as shown in FIGS. Also, the direction and range of the drain electrode, source electrode, and gate electrode of the adjacent FET can be determined independently. Therefore, more FETs can be manufactured on one chip.

A source that has a large number of FETs and comb-shaped electrodes ohmic-bonded to the gates, sources, and drains of the FETs, and a large number of drain electrodes coupled to one drain pad by a drain wiring lined on the chip surface. The top view of the chip | tip of the power FET device concerning the prior art example which couple | bonded many source electrodes to one source pad by wiring, and couple | bonded many gate electrodes to one gate pad.

A power device chip according to an embodiment of the present invention having a plurality of FETs and a plurality of comb-shaped electrodes joined to their gates, sources and drains, a plurality of distributed drain pads, and drain electrodes and source electrodes joined to the source pads FIG.

The longitudinal cross-sectional view cut | disconnected in the surface which crosses a drain electrode, a source electrode, and a gate electrode in the device chip | tip of FIG. Five insulating layers (oxide films) are formed on the n-type and p-type layers of the semiconductor. A source electrode and a drain electrode are in ohmic contact with the n ⁺ region formed in the p-type layer, and a gate electrode is in ohmic contact (junction type) with the p ⁺ region.

FIG. 3 is a longitudinal cross-sectional view of the device chip of FIG. 2, including a source wiring and a source pad. A plurality of source electrodes are integrated by through holes and pads. A plurality of such source pads are distributed on the chip.

The longitudinal cross-sectional view cut | disconnected including the part of drain wiring and the drain pad in the device chip | tip of FIG. A plurality of drain electrodes are integrated by through holes and pads. A plurality of such drain pads are dispersed on the chip.

The top view of the opposing surface of the wiring board which should join the chip | tip of FIG. Chip pads are distributed drain pads, distributed source pads, and distributed gate pads in mirror-symmetric positions, and there are unified substrate drain pads, substrate source pads, and substrate gate pads in the periphery. The distributed pad and the unified substrate pad are coupled by internal wiring.

An embodiment of the present invention in which a plurality of drain electrodes, a distributed drain pad in which source electrodes are gathered, and a plurality of source pads are provided on a chip, wherein the drain pads and source pads are arranged in one direction. The top view of the chip | tip part which shows the case of.

An embodiment of the present invention in which a plurality of drain electrodes, a distributed drain pad including a collection of source electrodes, and a plurality of source pads are provided on a chip, wherein the drain pads and the source pads are alternately arranged in a staggered pattern. The top view of a part of chip | tip which shows the case of arrangement | sequence.

FIG. 2 is a plan view of a power device chip according to an embodiment of the present invention in which a plurality of distributed drain pads and source pads are arranged in a matrix in a staggered manner.

The top view of the opposing surface of the wiring board corresponding to the device chip shown in FIG. Dispersive drain pads and source pads are formed at mirror-symmetric positions.

FIG. 11 is a longitudinal sectional view showing a state where the chip of FIG. 9 is attached to the wiring board of FIG. 10.

In the Example which joins two device chips as shown in FIG. 9 to one wiring board, the top view (1) which shows the opposing surface of a wiring board, and the longitudinal cross-sectional view (2) of a coupling | bonding state.

Explanation of symbols

2 Device chip
5 n-type SiC layer
6 p-type SiC layer
7 Gate electrode
8 Source electrode
9 Drain electrode
27 Gate collective wiring
28 Source set wiring
29 Drain collective wiring
37 Gate pad
38 Source Pad
39 Drain pad
48 through hole 49 through hole 57 gate pad 58 source pad 59 drain pad 60 substrate 67 substrate gate pad 68 substrate source pad 69 substrate drain pad 87 gate wiring 88 source wiring 89 drain wiring

Claims (2)

A distributed drain pad and a distributed source pad in which a plurality of field effect transistor (FET) groups of junction type or MOS type are dispersed on a SiC chip, and a drain electrode and a source electrode belonging to each transistor group are assembled. A plurality of distributed drain pads and distributed source pads are formed on the insulating wiring board so as to be mirror-symmetrical with the pads on the chip, and the substrate drain pad, the substrate source pad, and the substrate gate pad are formed on the periphery. By providing internal wiring, all drain pads are integrated into the substrate drain pad, all source pads are integrated into the substrate source pad, all gate pads are integrated into the substrate gate pad, the wiring substrate and the chip are bonded together, Drain pad, source pad and distributed drain pad, source pad of wiring board All the drain electrodes, source electrodes, and gate electrodes on the chip are connected to one substrate drain pad, substrate source pad, and substrate gate pad through the wiring substrate. Semiconductor device chip mounting method. A plurality of junction-type or MOS-type field effect transistor (FET) groups manufactured by dispersion, a drain electrode belonging to each transistor group, a distributed drain pad in which the source electrodes are assembled, and a distributed source pad SiC semiconductor chip, a plurality of distributed drain pads formed so as to be mirror-symmetrical with pads on the chip, distributed source pads, and substrate drain pads, substrate source pads, and substrate gate pads provided in the periphery And all the drain pads as substrate drain pads, all the source pads as substrate source pads, and all the gate pads as substrate gate pads. Paste the multiple drain pads and source pads of the chip and distribute the wiring board The drain pad and the source pad are bonded, and all the drain electrodes, source electrodes, and gate electrodes on the chip are connected to one substrate drain pad, substrate source pad, and substrate gate pad through the wiring substrate. A semiconductor device characterized by that.

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