CN116779559A - Thermal management scheme for power stages including top-cooled power semiconductor switching devices - Google Patents

Abstract

A power stage assembly for improving heat dissipation and EMC of top-cooled semiconductor power switching devices (e.g., high voltage, high current lateral GaN power transistors in embedded die packages). The power switching devices are mounted on a PCB substrate with electrical connections between the underside of each device package and the PCB. Each device package has a thermally conductive pad on the top side. A heat sink is secured in thermal contact with the thermally conductive pad of each device and a heat sink is in thermal contact with the heat sink. The heat sink is a multilayer structure comprising: a thermally conductive metal substrate layer in contact with the heat sink; providing a conductive layer of an EMC layer, the EMC layer being connected to a power ground; a conductive layer defining a large area thermal pad in thermal contact with the thermal pad of each die; and a dielectric material electrically isolating the conductive layer of the heat spreader.

Description

Thermal management scheme for power stages including top-cooled power semiconductor switching devices

Technical Field

The present invention relates to thermal management schemes for power semiconductor switching devices, for example, thermal management schemes for power stages or power modules comprising gallium nitride (GaN) power transistors for high current/high voltage applications.

Background

The power semiconductor switching device may include a lateral High Electron Mobility Transistor (HEMT), such as a lateral enhancement mode (E-mode) HEMT fabricated using wide band gap semiconductor technology, e.g., a group III nitride semiconductor material.

GaN power transistors, such as lateral GaN HEMTs, achieve high current, high voltage operation combined with high switching frequencies. For some power applications, the advantages of GaN power devices and systems are superior to silicon technology using Si IGBTs and diodes, as well as silicon carbide (SiC) power transistors and diodes. For example, power switching systems including lateral GaN power transistors provide higher switching efficiency, lower losses, and smaller profile than similar systems based on silicon or SiC technology. In order to benefit from the inherent performance characteristics of lateral GaN transistors, important design considerations include, for example: device layout (topology), low inductance interconnect and packaging, and efficient thermal management. Island Technology-based materials are currently commercially available from GaN Systems Inc ^(R) For high current operation at 100V and 650V, which lateral GaN power transistor enables the gate width W of the device _g Larger on-resistance R _on Smaller and higher current capacity per unit active area.

For example, gaN Systems Inc. early submitted andembedded die packages related patent literature and non-patent publications disclose embedded die package schemes that use either a top side thermal pad or a bottom side thermal pad to provide low inductance interconnection and low thermal resistance.

GaN power switching devices achieve high current capacity in compact Surface Mount Device (SMD) packages, such as GaNPx type embedded die packages. To provide high current capacity, a power module or power stage assembly may include a plurality of GaN transistors mounted on a substrate that provides electrical connections, e.g., a power substrate such as a Printed Circuit Board (PCB) or a power substrate of a power module, on which the plurality of GaN transistors are connected in parallel and configured to provide high-side and low-side switches of a half-bridge or other switching topology. For example, the power substrate may be based on multilayer PCB technology using FR4 type dielectric layers and copper conductive layers, IMS (insulated metal substrate) technology or DBC (direct bonded copper) technology.

Ruoyu Hou (Hou) provides background information about thermal management designs for GaN power switching devices including GaN transistors such as e-model lateral GaN HEMTs using top-cooled designs and bottom-cooled designs in a lecture entitled "thermal management techniques for GaN transistors" published by 7.14 in 2020. For example, due to drain-source on-resistance R _DSon And conduction losses are temperature dependent and as junction temperature Tj increases, failure times are increased, so good device-level and system-level thermal design is an important consideration in achieving improved performance, e.g., reducing overall losses, improving system efficiency and/or improving system reliability.

For example, the smaller die size and smaller embedded die package size of high current GaN HEMTs provide higher power density and small area thermal pads, which present challenges for thermal management, particularly efficient removal of heat from multiple power devices mounted in close proximity on a power substrate. Regarding electromagnetic compatibility (EMC), EMC is also a design consideration since GaN HEMTs operate at higher switching frequencies.

There is a need for improved or alternative thermal management schemes for semiconductor power switching devices, such as power stages including GaN power transistors.

Disclosure of Invention

The present invention seeks to provide an improved or alternative thermal management solution for a power switching device (e.g. a power stage comprising high current/high voltage GaN power transistors) which alleviates or circumvents at least one of the problems mentioned above.

One aspect of the present invention provides a power stage assembly for a top-cooled semiconductor power switching device, the power stage assembly comprising:

a PCB substrate;

a plurality of embedded die packages, each die comprising a semiconductor power switching device comprising at least one power transistor having source, drain and gate contact regions of the transistor on a front side of the die, and a thermally conductive pad on a back side of the die;

the plurality of embedded die packages are mounted on a PCB substrate, wherein electrical connections exist between conductive traces of the PCB and source, drain and gate contact areas on the front side of each die;

a heat spreader in thermal contact with the thermally conductive pad on the backside of each die; the heat sink is secured to the PCB substrate;

and a heat sink in thermal contact with the heat sink;

wherein, the radiator is multilayer structure, and multilayer structure includes:

a first layer comprising a thermally conductive metal substrate layer in contact with a heat sink;

a second layer comprising a thermally conductive dielectric layer;

a third layer comprising an electrically and thermally conductive material defining an electromagnetic compatibility (EMC) shielding layer;

a fourth layer comprising a thermally conductive dielectric layer;

a fifth layer comprising an electrically and thermally conductive material defining a thermally conductive pad in thermal contact with the thermally conductive pad of each die;

a dielectric layer provides electrical isolation between the conductive layers; and is also provided with

The EMC shield is interconnected to the power ground; and is also provided with

The area of the thermal pad of the third layer is greater than the area of the thermal pad of each embedded die package for providing lateral heat dissipation.

A second aspect of the invention provides a heat sink for a power stage assembly configured for a half-bridge switching module, wherein a plurality of embedded die packages are arranged to provide a high side switch comprising one power switching device or a plurality of parallel connected power switching devices and a low side switch comprising one power switching device or a plurality of parallel connected power switching devices,

the heat spreader includes a multi-layer Insulated Metal Substrate (IMS) structure comprising:

a first layer comprising a thermally conductive metal substrate layer;

a second layer comprising a thermally conductive dielectric layer;

a third layer comprising an electrically and thermally conductive material defining an electromagnetic compatibility (EMC) shielding layer;

a fourth layer comprising a thermally conductive dielectric layer;

a fifth layer comprising an electrically and thermally conductive material defining a thermally conductive pad in thermal contact with the thermally conductive pad of each die;

a dielectric layer provides electrical isolation between the conductive layers; and is also provided with

The EMC shield is interconnected to the power ground;

the area of the heat conduction pad of the fifth layer is larger than that of each embedded die package, and the heat conduction pad is used for providing transverse heat dissipation;

the thermal pad of the fifth layer of the heat sink comprises a first thermal pad for the low side switch and a second thermal pad for the high side switch, and wherein the first thermal pad is electrically interconnected to the EMC shielding layer through the fourth layer.

Another aspect of the invention provides a power stage assembly for a top-cooled semiconductor power switching device, the power stage assembly comprising:

PCB substrate

A plurality of embedded die packages, each embedded die package comprising a semiconductor power switching device comprising at least one power transistor having source, drain and gate contact regions on a bottom side of the die package and a thermally conductive pad on a top side of the die package;

the plurality of embedded die packages are mounted on a PCB substrate, wherein electrical connections exist between conductive traces of the PCB substrate and source, drain and gate contact areas on the bottom side of each die package;

a heat spreader in thermal contact with the thermally conductive pad on the backside of each die; the heat sink is secured to the PCB substrate;

and is also provided with

A heat sink in thermal contact with the heat sink;

wherein the heat sink is a multi-layer structure comprising:

a first layer comprising a thermally conductive metal substrate layer in contact with a heat sink;

a second layer comprising a thermally conductive dielectric layer;

a third layer comprising an electrically and thermally conductive material defining a thermally conductive pad in contact with the thermally conductive pad on the top side of each die package;

the dielectric layer provides electrical isolation between the first and second layers of the heat spreader;

the area of the thermal pad of the third layer is greater than the area of the thermal pad of each embedded die package for providing lateral heat dissipation.

For example, the power stage assembly of the exemplary embodiments is particularly applicable to group III nitride power switching devices, such as high voltage/high current lateral GaN HEMTs, which enable higher current capacity per unit die area and can be packaged in compact embedded die packages that provide high power density and low inductance interconnections.

Drawings

Fig. 1 (prior art) shows some examples of GaN power transistors with GaNPx packages with bottom side thermal pads;

fig. 2 (prior art) shows some examples of GaN power transistors with GaNPx packages with topside thermal pads;

FIG. 3 (Prior Art) shows a schematic cross-sectional view of an example of a GaNPx packaged GaN power transistor and PCB substrate, and a bottom cooling assembly for a heat sink for thermal management;

fig. 4 (prior art) shows a schematic cross-sectional view of an example of a GaN power transistor and PCB substrate of a GaNPx package, and a top cooling component of a heatsink for thermal management;

fig. 5 (prior art) shows a schematic cross-sectional view of an example of an assembly of a bottom-cooled GaNPx packaged GaN power transistor, wherein the PCB substrate is an IMS PCB mounted on a heat sink.

FIG. 6A (prior art) shows a GaN half-bridge power switching device including an IMS PCB for including a bottom cooling device package; a heat sink; and a schematic side view of a power stage assembly of a gate drive board mounted over the IMS PCB;

FIG. 6B (prior art) shows an oblique view of the power stage assembly of FIG. 6A;

fig. 7 (prior art) shows a schematic block diagram of a GaN half-bridge IMS PCB and gate drive board for the assembly shown in fig. 6A and 6B.

Fig. 8 shows a schematic cross-sectional view of a top cooling power stage assembly comprising a GaN half-bridge according to a first exemplary embodiment;

fig. 9 shows a photograph of a portion of a PCB for a power switching device including a GaN half-bridge including two GaN power transistors;

fig. 10 shows a photograph of one side of the IMS heat sink of the first exemplary embodiment;

fig. 11 shows a schematic view of a silk screened layer of the IMS heat sink of the first exemplary embodiment shown in fig. 10, which is mounted on the half-bridge PCB shown in fig. 9;

FIG. 12 shows a schematic cross-sectional view of the top cooling power stage assembly shown in FIG. 8, wherein arrows schematically illustrate heat dissipation paths from the die, through the IMS heat spreader, to the heat sink;

FIG. 13 shows a schematic cross-sectional view of a first top cooling power module assembly according to a second exemplary embodiment;

fig. 14A and 14B show top and bottom views, respectively, of an IMS heat sink of a second exemplary embodiment;

fig. 15 shows a schematic diagram of the silk screened layers of a half bridge PCB and an IMS heat sink of a second exemplary embodiment;

FIG. 16 illustrates a data table showing elements of thermal resistance of an exemplary conventional top-cooling power assembly including a TIM and a top-cooling power assembly including an exemplary embodiment of an IMS heat spreader (single layer) for an exemplary GaN half-bridge power switching device;

FIG. 17 shows a graph comparing the total thermal resistance RthJA (C/W) and GaN power loss (W) of an exemplary half-bridge power switching device with a conventional top-cooling power assembly including a TIM and a top-cooling power assembly including an exemplary embodiment of an IMS heatsink (single layer);

FIG. 18 shows a graph comparing system power (W) and fin thermal resistance R of an exemplary half-bridge power switching device with a conventional top-cooling power assembly including a TIM and a top-cooling power assembly including an exemplary embodiment of an IMS heatsink (single layer) _th HS-A (C/W); and is also provided with

FIG. 19 shows a graph comparing dollar cost per watt ($/W) versus fin thermal resistance R for an exemplary half-bridge power switching device with a conventional top-cooling power assembly including a TIM and a top-cooling power assembly including an exemplary embodiment of an IMS heatsink (single layer) _th HS-A(C/W)。

The foregoing and other features, aspects and advantages will become more apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Detailed Description

Device structures for enhancement mode (E-mode) lateral GaN power transistors are described, for example, in U.S. patent No. 11,139,373 to "Scalable circuit-under-pad device topologies for lateral GaN power transistors" issued at 5 of 10 of 2021, U.S. patent application No. 17/085,137 to "Device topologies for high current lateral power semiconductor devices" filed at 30 of 10 of 2020, and references cited herein. For example, a silicon-based GaN device structure for a GaN HEMT may include a silicon substrate, and an epitaxial layer structure (epitaxial layer) formed on the silicon substrate, the epitaxial layer structure including a GaN heterostructure, e.g., a GaN barrier layer and an AlGaN channel layer, to provide a 2DEG active region. The source, drain and gate contact regions of the lateral GaN power transistor are disposed on the front side (which may be referred to as the "active side") of the die. The backside of the die (e.g., a metallization layer on the backside of the silicon substrate) provides a thermal contact. While GaN HEMTs may be supplied as bare dies, various forms of embedded die packages with low inductance interconnects may be provided to allow for placement of either the top side thermal pad or the bottom side thermal pad.

Examples of embedded die packages for E-mode lateral GaN power transistors are disclosed, for example, U.S. patent application No. US16/928,305 entitled "Embedded die packaging for power semiconductor devices" filed 7/14/2020; U.S. patent No. 9,659,854, entitled "Embedded Packaging for Devices and Systems Comprising Lateral GaN Power Transistors"; U.S. patent No. 9,589,868, entitled "Packaging Solutions for Devices and Systems Comprising Lateral GaN Power Transistors"; U.S. patent No. 9,589,869, entitled "Packaging Solutions for Devices and Systems Comprising Lateral GaN Power Transistors"; in U.S. patent No. 9,824,949, entitled "Packaging Solutions for Devices and Systems Comprising Lateral GaN Power Transistors".

GaN Systems Co., ltdThe embedded die package may be configured for top side cooling or bottom side cooling. For example, fig. 1 (prior art) shows an example of a GaN power transistor with a GaNPx package with a bottom side thermal pad. Fig. 2 (prior art) shows an example of a GaN power transistor with a GaNPx package with a topside thermal pad.

Fig. 3 shows a schematic cross-sectional view of an example of a GaN power transistor and PCB substrate of a GaNPx package, and a bottom cooling assembly of a heat sink for thermal management. In this configuration, the thermal pad and source, drain and gate contacts are disposed on one side of the package. The packaged GaN power transistor is mounted, such as by soldering, on a PCB that provides electrical connections for the source, drain and gate contacts. The thermal pad is in thermal contact with a thermal conduction hole extending through the PCB to the thermal pad on an opposite side of the PCB. The heat sink is in thermal contact with the thermal pad of the PCB through a layer of Thermal Interface Material (TIM)And (5) installation. Fig. 3 schematically illustrates a thermal resistance of various components that facilitate conduction and convective heat dissipation, the thermal resistance comprising: thermal resistor R between electrical contacts and nodes on a die _th JC; thermal resistance R of solder connection between die contact and corresponding top conductive trace of PCB _th A holder; thermal resistor R of PCB _th A PCB; thermal resistor R of TIM _th TIM; thermal resistor R from heat sink to ambient _th HS-A. The total thermal resistance between the junction and the surrounding environment may be referred to as R _th And JA. The junction temperature Tj depends on the ambient temperature T _A Power loss of GaN HEMT and thermal resistor R from radiating fin to surrounding environment _th Sum of HS-A:

Tj＝T _A +P x R _th JA

the excellent electrical quality factor (Figure of Merit) of GaN HEMTs limits the total power loss. Reducing the total heat resistance R _th The thermal design of JA is very important to optimize device performance, for example, by reducing Tj to reduce overall conduction and switching losses and improve system reliability.

Fig. 4 shows a schematic cross-sectional view of an example of a GaN power transistor and PCB substrate showing a GaNPx package, and a top cooling assembly of a heat sink for thermal management. In a top-cooled embedded die package, thermal pads are provided on the top side of the package, and electrical contacts for the source, drain, and gate are provided on the bottom side (which corresponds to the active side of the die). In the design of the top cooling assembly, the electrical connections of the PCB are separated from the thermal connections of the heat sink. The total thermal resistance includes thermal resistance R between thermal contact pads and nodes on the die _th JC; thermal resistor R of TIM _th TIM; thermal resistor R from heat sink to ambient _th HS-A。

For bottom cooling power assemblies, for example, as schematically shown in fig. 3, where both electrical connections and thermal pads are on one side of the device, the relatively high thermal resistance of the PCB and solder connections and TIMs may be limiting factors for heat dissipation of power module assemblies employing FR4 type PCB technology through copper heat sinks. FR4 PCB technology is a mature process and achieves layout flexibility and low cost, but the thermal resistance of FR4 dielectrics (e.g., 0.25W/mK) is relatively high.

The use of an Insulated Metal Substrate (IMS) PCB may reduce the thermal resistance of the bottom cooling assembly, as shown in the example shown in fig. 5. IMS PCBs provide lower thermal resistance, but on the other hand, IMS PCBs include only 1-layer or 2-layer electrical connections, and IMS substrates introduce parasitic inductances and coupling capacitances due to the metal substrates. Fig. 6A, 6B and 7 illustrate examples of bottom-cooled IMS power stage components for power semiconductor switching devices including half-bridge switching topologies, where the high side and low side switches include GaN HEMTs. The assembly includes an IMS PCB with a GaN half-bridge mounted thereon, a heat sink, and a gate drive board mounted on the IMS PCB. An exemplary IMS PCB may include an isolated aluminum (Al) or copper (Cu) substrate/support layer, a dielectric layer (e.g., 30 μm to 200 μm dielectric such as thermal prepreg with a thermal conductivity in the range of, for example, 1-5W/mK), and a copper foil conductive layer (e.g., 35 μm to 140 μm) patterned to provide an electrical connection. As schematically shown in fig. 5, the use of an IMS PCB and a thermal grease between the IMS PCB and the heat sink can significantly reduce thermal resistance relative to conventional FR4 PCBs and TIMs as schematically shown in fig. 3.

For a top cooling power assembly, for example, as schematically shown in fig. 4, where there are electrical connections on one side of the die and thermal pads on the other side of the die, the power semiconductor device is sandwiched (e.g., clamped or fixed) between a PCB carrying the electrical connections and a heat sink contacting the thermal pads on the die. The heat dissipation of the top-cooled power module assembly is largely dependent on the parameters of the thermally conductive interface material (TIM) layer disposed between the contact surfaces of the thermal pad and the heat sink. The TIM layer adheres the heat sink to the thermal pad, as well as providing both thermal contact and electrical isolation, so the key parameters of the TIM are thermal conductivity, dielectric strength, mechanical strength, and cost. Other design considerations for the top cooling module include providing an appropriate creepage distance and clearance distance between the PCB and the heat sink.

A schematic cross-sectional view of the top cooling power stage assembly of the first exemplary embodiment is shown in fig. 8. The power stage includes a half-bridge switching topology in which the high side switch and the low side switch include GaN HEMTs mounted on a PCB. For example, gaN HEMTs are packaged in a GaNPx type embedded die package with a topside thermal pad and source, drain and gate contact regions on the backside, as shown in fig. 2. As shown, by way of example, for the PCB shown in fig. 9, the PCB layout includes die attach areas for the high side switch and the low side switch, each die attach area including a single GaN device.

As shown in the schematic cross-sectional view in fig. 8, the source, drain, and gate contact regions of each GaN HEMT are electrically connected (e.g., soldered) to corresponding conductive traces on the PCB. The thermally conductive pad on the top side of the package of each GaN HEMT is in thermal contact with a heat spreader that extends laterally over the area of the PCB surrounding the GaN HEMT. The large area heat sink is in thermal contact with the heat sink. The heat spreader is an IMS heat spreader comprising an isolated metal substrate, e.g., an Al support layer or a Cu support layer; a thermally conductive dielectric layer, e.g., a thermal prepreg layer; and an electrically conductive layer, e.g., a Cu foil layer, defining a first thermally conductive pad and a second thermally conductive pad, as shown in the top plan view of fig. 10. The thermal pad of each GaN HEMT is in contact with a respective one of the first thermal pad and the second thermal pad of the IMS heat sink with a thermally conductive layer, e.g., a thermally conductive grease or other suitable material, between the thermal pads of the package and the thermal pad of the heat sink. Fig. 11 shows a schematic top plan view to illustrate the alignment of an IMS heat sink mounted on a PCB. The area of the IMS heat sink is much larger than that of the GaN HEMT. The IMS heat spreader extends laterally of the GaN HEMT to provide a lateral heat dissipation path and a larger thermal contact for the heat sink. For example, in an exemplary embodiment, area A of the thermal pad of the GaNPx embedded die package _D Is about 45mm ² (e.g., 8.2mm x5.6 mm), and area a of each thermal pad on the IMS heatsink _H Is about 345mm ² (e.g., 30mmx11.5 mm) to provide a of 7.5:1 _H :A _D Relative area. The rth_jhs heat improvement rate was 42%.

The IMS heat sink is secured to the PCB using any suitable mechanical attachment, for example, using one or more screws or clamps to secure the heat sink to the PCB with the GaN HEMT sandwiched between the PCB and the heat sink. The heat sink is secured to the IMS heat sink by a layer of thermally conductive grease between the heat sink and the heat sink. Fig. 12 shows a schematic cross-sectional view of the top cooling power stage assembly shown in fig. 8, with the added arrows schematically showing the heat dissipation path from the die, through the IMS heat spreader, to the heat sink. The IMS heat sink provides a lateral heat dissipation path to dissipate heat over a larger area of the entire heat sink.

For brevity, fig. 8-12 illustrate an exemplary power stage assembly with a power substrate PCB configured for a half-bridge switching topology, where the high side switch and the low side switch are each a single GaN power switching device. In alternative embodiments, the power substrate PCB may be configured for a full bridge switching topology or other switching topologies, wherein the high side and low side switches comprise GaN power switching devices. For higher current applications, the high side switch and the low side switch may each include multiple parallel GaN HEMTs to provide greater current capacity. In the latter case, the power substrate PCB may comprise a die attach area for each high side switch and low side switch, and the IMS heat sink may be structured to provide a larger thermal contact area, a first thermal contact area for contact with each high side switch and a second thermal contact area for contact with each low side switch. For some application areas, gaN power switching devices are packaged in embedded die packages, such as GaNPx type packages. For some applications, gaN power switching devices are provided in bare die form.

A schematic cross-sectional view of a top cooling power stage assembly of a second exemplary embodiment is shown in fig. 13. The power stage includes a half-bridge switching topology in which the high side switch and the low side switch include GaN power switching devices mounted on a PCB. As shown, by way of example, for the PCBs shown in fig. 10 and 15, the high side switch and the low side switch each include a single GaN HEMT. For example, gaN HEMTs are packaged in a GaNPx type embedded die package with a topside thermal pad and source, drain and gate contact regions on the backside, as shown in fig. 2. The large area heat sink is in thermal contact with the heat sink. The heat spreader is an IMS heat spreader comprising an isolated metal substrate, e.g., an Al support layer or a Cu support layer; a first thermally conductive dielectric layer, e.g., a thermal prepreg layer; and a first conductive layer, e.g., a Cu foil layer; a second thermally conductive dielectric layer, e.g., a thermal prepreg layer; and a second conductive layer, for example, a copper foil layer. The second conductive layer defines a first thermal pad and a second thermal pad, as shown in the top plan view in fig. 14A. The first conductive layer defines an EMC shielding layer or plate that extends over the first and second conductive pad regions of the second conductive layer. A first thermal pad for the low side switch is interconnected to a first conductive layer defining an EMC shielding layer through a conductive via (e.g., a series of laser drilled copper-filled vias). Thus, the source of the low side device connected to Power Ground (PGND) is connected to the EMC shield defined by the first conductive layer. The thermal pad of each GaN HEMT is in contact with a respective one of the first thermal pad and the second thermal pad of the IMS heat sink with a thermally conductive layer, e.g., a thermally conductive grease or other suitable material, between the thermal pads of the package and the thermal pad of the heat sink. The IMS heat spreader extends laterally of the GaN HEMT to provide a lateral heat dissipation path and a larger thermal contact for the heat sink. The IMS heat sink is secured to the PCB using any suitable mechanical attachment, for example, using one or more fasteners or clamps to secure the heat sink to the PCB with the GaN HEMT sandwiched between the PCB and the heat sink. The heat sink is secured to the IMS heat sink by a layer of thermally conductive grease between the heat sink and the heat sink.

The data table in fig. 16 compares thermal resistance of an exemplary conventional top-cooling power assembly including a TIM layer between a thermal pad and a heatsink of a GaN device; and elements of the top cooling power assembly including an exemplary embodiment of an IMS heat spreader between the GaN device and the heat sink. The dimensions of the two example heat sinks are the same. In this embodiment, the IMS heat sink has a single copper layer. The thermal resistance of the IMS heatsink is significantly reduced compared to conventional TIM layers. In the present exemplary embodiment, the thermal resistance between the junction and the heat sink was reduced from 2.9C/W to 1.68C/W by 42%.

FIG. 17 shows a graph comparing the total thermal resistance R of an exemplary half-bridge power switching device with a conventional top-cooling power assembly including a TIM and an exemplary top-cooling power assembly including an exemplary embodiment of an IMS heatsink with a single copper layer _th JA (C/W) and GaN power loss (W).

FIG. 18 shows a graph comparing system power (W) and fin thermal resistance R of an exemplary half-bridge power switching device with a conventional top cooling power assembly including TIM and a top cooling power assembly including an exemplary embodiment of an IMS heatsink for different types of fins _th HS-A(C/W)。

FIG. 19 shows a graph comparing dollar cost per watt ($/W) and fin thermal resistance R for an exemplary half-bridge power switching device with a conventional top-cooling power assembly including TIM and an exemplary embodiment of a top-cooling power assembly including an IMS heatsink with a single copper layer for different types of fins _th HS-A(C/W)。

A top cooling assembly for a power switching stage including a GaN power transistor of an exemplary embodiment has been described that includes an IMS heatsink for reducing thermal resistance and improving heat dissipation. In some embodiments, the IMS heat sink provides an additional conductive shielding layer to enhance EMC performance.

In alternative embodiments, a heat spreader formed from a DBC (direct bonded copper) substrate or an AMB (active metal brazing) substrate may be used instead of an IMS heat spreader.

Other suitable heat sink structures include a support substrate that includes at least one thermally conductive layer that provides electrical isolation, and at least one conductive layer that defines a thermally conductive pad for each power semiconductor device, and optionally a second conductive layer that provides an EMC shielding layer. The heat sink has a larger area of the thermal pad in contact with the topside thermal pad of each power switching device than the area of the thermal pad of the packaged device. Thus, the thermal pad provides horizontal or lateral heat spreading prior to electrical isolation. Inserting a heat spreader between the thermal pad and the heat sink of the power semiconductor device provides a lateral heat dissipation path of lower thermal resistance.

An IMS substrate having a first conductive layer and a second conductive layer provides a structure in which one conductive layer provides a thermal pad for lateral thermal diffusion and the other conductive layer provides an EMC shielding layer.

The top-cooling device is useful for power electronics design because the flexibility of the PCB layout of the power substrate is greater when the thermal and electrical layers do not overlap and the flexibility of system/heat sink design and mounting for high power applications and low power applications is improved.

A further obstacle to improving the thermal performance of top-cooled devices is the limited area/size of the thermal pads of the devices. Thermal performance is limited by the area of the thermal pad due to the smaller die size and smaller package. On the other hand, in larger-sized packages, parasitic effects such as interconnect inductance or resistance may limit the performance of power semiconductor devices such as GaN HEMTs that can be switched quickly (fast on and off times, and operate at higher switching frequencies).

In the power stage assembly of the exemplary embodiments disclosed herein, significant enhancement of the thermal performance of the top-cooled device is achieved while maintaining good switching performance and EMC performance, which helps to improve the system level $/W.

While the power stage components of the exemplary embodiments have been described in detail with reference to semiconductor power switching devices that include lateral GaN transistors (such as high voltage/high current GaN HEMTs, in which the active layer includes a GaN/AlGaN heterostructure), it is apparent that nitride semiconductor device structures according to alternative embodiments may include lateral GaN power transistors and/or diodes. More generally, the nitride semiconductor device includes a group III nitride semiconductor, i.e., a compound semiconductor including nitrogen and at least one group III element such as GaN, alGaN, alN, inGaN, inAlGaN, and the nitride semiconductor device structure includes a hetero-layer structure of a first nitride semiconductor layer and a second nitride semiconductor layer having different band gaps, which forms an active region including a two-dimensional electron gas (2 DEG) region of a transistor and/or a diode.

The power stage assembly for GaN power switching devices with improved top side cooling and EMC performance as disclosed herein may be more generally applicable to power switching devices fabricated using other semiconductor technologies that require top side cooling to be provided.

Although embodiments of the present invention have been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation.

Claims (17)

1. A power stage assembly for a top-cooled semiconductor power switching device, the power stage assembly comprising:

a PCB substrate;

a plurality of embedded die packages, each die package comprising a semiconductor power switching device comprising at least one power transistor having an electrical contact area on a front side of the embedded die package and a thermally conductive pad on the back side of the embedded die package;

the plurality of embedded die packages are mounted on the PCB substrate, wherein there is an electrical connection between the conductive trace of the PCB and the electrical contact area on the front side of each die package;

a heat spreader in thermal contact with the thermally conductive pad on the backside of each die package; the heat sink is secured to the PCB substrate;

and a heat sink in thermal contact with the heat sink;

wherein the heat sink is a multi-layered structure comprising:

a first layer comprising a thermally conductive metal substrate layer in contact with the heat sink;

a second layer comprising a thermally conductive dielectric layer;

a third layer comprising an electrically and thermally conductive material defining an electromagnetic compatibility (EMC) shielding layer;

a fourth layer comprising a thermally conductive dielectric layer;

a fifth layer comprising an electrically and thermally conductive material defining a thermally conductive pad in thermal contact with the thermally conductive pad of each die;

the dielectric layer provides electrical isolation between the conductive layers; and is also provided with

The EMC shield is interconnected to a power ground; and is also provided with

The thermal pad of the fifth layer has an area greater than an area of the thermal pad of each embedded die package for providing lateral heat dissipation.

2. The power stage assembly of claim 1, wherein the layer of the heat sink is provided by a multi-layer Insulated Metal Substrate (IMS).

3. The power stage assembly of claim 1 or 2, wherein the top-cooled power switching device is a GaN power switching device.

4. A power stage assembly according to any of claims 1 to 3 configured for a half-bridge switching topology, a full-bridge switching topology or other switching topologies comprising a plurality of power switching devices.

5. The power stage assembly of any of claims 1-4, wherein the thermal pad of the embedded die package has an area a _D And the heat conduction pad of the heat radiator has an area A _H And wherein A _H :A _D The area ratio of (2) is in the range of 3:1 to 10:1.

6. The power stage assembly of any of claims 1-4, wherein the thermal pad of the embedded die package has an area a _D And the heat conduction pad of the heat radiator has an area A _H And wherein A _H :A _D The area ratio of (2) is greater than 5:1.

7. The power stage assembly of any of claims 1-6, configured for a half-bridge switching topology, wherein:

the embedded die package is arranged to provide a high side switch comprising one power switching device or a plurality of power switching devices connected in parallel and a low side switch comprising one power switching device or a plurality of power switching devices connected in parallel, and

the thermal pad of the fifth layer of the heat sink comprises a first thermal pad for the low side switch and a second thermal pad for the high side switch, and wherein the first thermal pad is interconnected to the EMC shielding layer through the fourth layer.

8. The power stage assembly of any of claims 1-6 configured for a full bridge switching topology, wherein:

the embedded die package is arranged to provide a high side switch comprising one power switching device or a plurality of power switching devices connected in parallel and a low side switch comprising one power switching device or a plurality of power switching devices connected in parallel, and

the thermal pad of the fifth layer of the heat spreader comprises a first thermal pad for each of the low side switches and a second thermal pad for each of the high side switches, and wherein the first thermal pad is interconnected to the EMC shielding layer through the fourth layer.

9. A heat sink for a power stage assembly configured for a half-bridge switching module, wherein a plurality of embedded die packages are arranged to provide a high side switch comprising one power switching device or a plurality of parallel connected power switching devices and a low side switch comprising one power switching device or a plurality of parallel connected power switching devices,

the heat spreader includes a multi-layer Insulated Metal Substrate (IMS) structure comprising:

a first layer comprising a thermally conductive metal substrate layer;

a second layer comprising a thermally conductive dielectric layer;

a third layer comprising an electrically and thermally conductive material defining an electromagnetic compatibility (EMC) shielding layer;

a fourth layer comprising a thermally conductive dielectric layer;

a fifth layer comprising an electrically and thermally conductive material defining a thermally conductive pad in thermal contact with the thermally conductive pad of each die;

the dielectric layer provides electrical isolation between the conductive layers; and is also provided with

The EMC shield is interconnected to a power ground;

the area of the thermal pad of the fifth layer is larger than the area of the thermal pad of each embedded die package for providing lateral heat dissipation;

the thermal pad of the fifth layer of the heat sink comprises a first thermal pad for the low side switch and a second thermal pad for the high side switch, and wherein the first thermal pad is interconnected to the EMC shielding layer through the fourth layer.

10. A power stage assembly for a top-cooled semiconductor power switching device, the power stage assembly comprising:

a PCB substrate;

a plurality of embedded die packages, each embedded die package comprising a semiconductor power switching device comprising at least one power transistor having an electrical contact area on a bottom side of the die package and a thermally conductive pad on a top side of the die package;

the plurality of embedded die packages are mounted on the PCB substrate, wherein an electrical connection exists between conductive traces of the PCB substrate and the electrical contact areas on the back side of each die package;

a heat spreader in thermal contact with the thermally conductive pad on the backside of each die; the heat sink is secured to the PCB substrate;

and

a heat sink in thermal contact with the heat sink;

wherein the heat sink is a multi-layered structure comprising:

a first layer comprising a thermally conductive metal substrate layer in contact with the heat sink;

a second layer comprising a thermally conductive dielectric layer;

a third layer comprising an electrically and thermally conductive material defining a thermally conductive pad in contact with the thermally conductive pad of each die package;

the dielectric layer provides electrical isolation between the first layer and the second layer of the heat spreader;

the area of the thermal pad of the third layer is greater than the area of the thermal pad of each embedded die package for providing lateral heat dissipation.

11. The power stage assembly of claim 10, wherein the layer of the heat sink is provided by a multi-layer insulating metal substrate.

12. The power stage assembly of claim 10 or 11, wherein the top-cooled power switching device is a GaN power switching device.

13. The power stage assembly of any of claims 10 to 12 configured for a half-bridge switching topology, a full-bridge switching topology, or other switching topologies comprising a plurality of power switching devices.

14. The power stage assembly of any of claims 10-13, wherein the thermal pad of the embedded die package has an area a _D And the heat sink is electrically connected to the heat sinkThe area of the heat pad is A _H And wherein A _H :A _D The area ratio of (2) is in the range of 3:1 to 10:1.

15. The power stage assembly of any of claims 10-13, wherein the thermal pad of the embedded die package has an area a _D And the heat conduction pad of the heat radiator has an area A _H And wherein A _H :A _D The area ratio of (2) is greater than 5:1.

16. The power stage assembly of any of claims 10 to 15, configured for a half-bridge switching topology, wherein:

the embedded die package is arranged to provide a high side switch comprising one power switching device or a plurality of power switching devices connected in parallel and a low side switch comprising one power switching device or a plurality of power switching devices connected in parallel, and

the thermal pad of the fifth layer of the heat sink includes a first thermal pad for the low side switch and a second thermal pad for the high side switch.

17. The power stage assembly of any of claims 1-6 configured for a full bridge switching topology, wherein:

the embedded die package is arranged to provide a high side switch comprising one power switching device or a plurality of power switching devices connected in parallel and a low side switch comprising one power switching device or a plurality of power switching devices connected in parallel, and

the thermal pad of the fifth layer of the heat sink includes a first thermal pad for each of the low side switches and a second thermal pad for each of the high side switches.