CN106601876A - LED chip structure and manufacturing method thereof - Google Patents
LED chip structure and manufacturing method thereof Download PDFInfo
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- CN106601876A CN106601876A CN201510679865.XA CN201510679865A CN106601876A CN 106601876 A CN106601876 A CN 106601876A CN 201510679865 A CN201510679865 A CN 201510679865A CN 106601876 A CN106601876 A CN 106601876A
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- gallium nitride
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 78
- 229910002601 GaN Inorganic materials 0.000 claims abstract description 71
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims abstract description 71
- 229910052594 sapphire Inorganic materials 0.000 claims abstract description 70
- 239000010980 sapphire Substances 0.000 claims abstract description 70
- 239000011148 porous material Substances 0.000 claims abstract description 69
- 238000000034 method Methods 0.000 claims abstract description 33
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 230000008859 change Effects 0.000 claims description 6
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 6
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052733 gallium Inorganic materials 0.000 claims description 5
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 5
- 230000003287 optical effect Effects 0.000 claims description 4
- 241000931526 Acer campestre Species 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 239000010437 gem Substances 0.000 claims 2
- 229910001751 gemstone Inorganic materials 0.000 claims 2
- 241001062009 Indigofera Species 0.000 claims 1
- 239000010410 layer Substances 0.000 description 81
- 238000010586 diagram Methods 0.000 description 11
- 238000000605 extraction Methods 0.000 description 11
- 239000000463 material Substances 0.000 description 11
- 238000002360 preparation method Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 229910002804 graphite Inorganic materials 0.000 description 2
- 239000010439 graphite Substances 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000005587 bubbling Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000004678 hydrides Chemical class 0.000 description 1
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- 238000001259 photo etching Methods 0.000 description 1
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
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- Engineering & Computer Science (AREA)
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
The invention provides a manufacturing method of an LED chip structure. The method comprises the following steps that S1) a sapphire substrate is provided; S2) laser irradiates the back side of the sapphire substrate and is focused in the sapphire substrate, and a pore array is formed in the sapphire substrate; S3) a growth buffer layer, an N type gallium nitride layer, a multi-quantum well luminescent layer and a P type gallium nitride layer are grown on the surface of the sapphire substrate successively; S4) the P type gallium nitride layer and the multi-quantum well luminescent layer are etched to form a recess area, and part of the surface of the N type gallium nitride layer is exposed out of the recess area; and S5) a P electrode is prepared in the surface of the P type gallium nitride layer, an N electrode is prepared in the surface of the recess area, and an LED chip structure is obtained. In the LED chip structure, due to existence of the pore array, the light emitting efficiency of an LED can be improved, a stress of a GaN epitaxial layer can be reduced, and the internal quantum efficiency of the LED is improved.
Description
Technical field
The invention belongs to LED chip field, is related to a kind of LED chip structure and preparation method thereof.
Background technology
Light emitting diode (Light Emitting Diode, abbreviation LED) is a kind of light emitting semiconductor device, using quasiconductor P-N
Junction electroluminescence principle is made.LED has energy consumption low, small volume, life-span length, good stability, and response is fast, and emission wavelength is steady
The fixed photoelectric properties for having waited, have in fields such as illumination, household electrical appliances, display screen, display lamps apply well at present.In recent years,
In order to improve the quality of lighting and integrated level of LED product, unit area light efficiency (lm/W/cm2) become measurement LED chip
An important indicator.
Gallium nitride (GaN) material series are that the band gap of a kind of preferable short-wave long light-emitting device material, gallium nitride and its alloy is covered
Cover from redness to ultraviolet spectral region.Since Japan in 1991 is developed after homojunction gallium nitride blue led,
InGaN/AlGaN double heterojunction ultra-brightness blue leds, InGaN single quantum well GaN LED come out one after another.Gallium nitride based LED
, power less than traditional LED profiles is higher.A small amount of gallium nitride based LED is provided for and traditional LED identicals luminous quantity.
GaN base light emitting is typically grown in nonconducting Sapphire Substrate, because the refractive index of GaN material makes more greatly
Most of light that LED sends roundtrip inside GaN material is consumed, and only 4% or so light can be emitted.For
The light extraction efficiency of LED is improved, graphical sapphire substrate (Patterned Sapphire Substrate, PSS) is generally adopted
With, the LED that the emergent light brightness ratio of the LED grown on PSS is traditional is greatly improved, while reverse leakage current reduces, LED
Life-span also extended.Also invented the methods such as surface coarsening, photon crystal structure, gradual change dielectric layer to improve GaN simultaneously
The light extraction efficiency of LED.However, LED light extraction efficiency need further raising.
Therefore, how a kind of Novel LED chip structure and preparation method thereof is provided, further to improve the light extraction efficiency of LED,
Become those skilled in the art's important technological problems urgently to be resolved hurrily.
The content of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of LED chip structure and its making side
Method, for solving the problems, such as prior art in LED chip light extraction it is inefficient.
For achieving the above object and other related purposes, the present invention provides a kind of manufacture method of LED chip structure, including following
Step：
S1：One Sapphire Substrate is provided；
S2：Using laser is from the Sapphire Substrate back side illuminaton and focuses on inside the Sapphire Substrate, in the sapphire
Substrate interior forms pore array；
S3：In the sapphire substrate surface successively grown buffer layer, n type gallium nitride layer, multiple quantum well light emitting layer and p-type nitrogen
Change gallium layer；
S4：The p-type gallium nitride layer and the multiple quantum well light emitting layer are etched, sunk area, the sunk area exposure is formed
Go out the part surface of the n type gallium nitride layer；
S5：P electrode is made on the p-type gallium nitride layer surface, on the sunk area surface N electrode is made, obtain LED
Chip structure.
Alternatively, the Sapphire Substrate is plain film substrate or patterned substrate.
Alternatively, the optical maser wavelength is 1064nm.
Alternatively, in the pore array, the figure cycle is 0.5～10 μm.
Alternatively, the altitude range of the pore is 0.5～5 μm, and width range is 0.1～3 μm.
Alternatively, the pore array includes one layer of pore.
Alternatively, the distance between the pore array and described Sapphire Substrate upper surface scope is 1～200 μm.
Alternatively, the pore array includes at least two-layer gas pore.
Alternatively, in step S3, using MOCVD method or molecular beam epitaxy growth institute
State cushion, n type gallium nitride layer, multiple quantum well light emitting layer or p-type gallium nitride layer.
The present invention also provides a kind of LED chip structure, including：
Sapphire Substrate；The Sapphire Substrate has been internally formed pore array；
It is sequentially formed in cushion, n type gallium nitride layer, multiple quantum well light emitting layer and the p-type nitridation of the sapphire substrate surface
Gallium layer；
Through the p-type gallium nitride layer and the multiple quantum well light emitting layer and expose the n type gallium nitride layer segment surface
Sunk area；
The P electrode on the p-type gallium nitride layer surface is formed at, the N electrode on the sunk area surface is formed at.
Alternatively, the pore array includes one or more layers pore.
As described above, LED chip structure of the present invention and preparation method thereof, has the advantages that：The present invention utilizes laser
Technology forms pore array in Sapphire Substrate, and using pore is different from sapphire refractive index the light extraction efficiency of LED is obtained
Significantly lifted, increase LED chip external quantum efficiency.And the method is not limited to plain film or graphical sapphire substrate.Simultaneously
Because the presence of pore in Sapphire Substrate can effectively reduce the stress of GaN epitaxial layer, the internal quantum efficiency of LED is improved.It is comprehensive
Two aspect factors more than closing, can greatly improve the luminous efficiency of LED.
Description of the drawings
Fig. 1 is shown as the process chart of the manufacture method of the LED chip structure of the present invention.
Fig. 2 is shown as the cross-sectional view of the Sapphire Substrate provided in the manufacture method of the LED chip structure of the present invention.
Fig. 3 is shown as being internally formed pore array in the Sapphire Substrate in the manufacture method of the LED chip structure of the present invention
Schematic diagram.
Fig. 4-Fig. 6 is shown as the plane figure of several different pore arrays.
Fig. 7 is shown as schematic diagram of the pore array including two-layer pore.
Fig. 8 is shown as growing buffering successively in the sapphire substrate surface in the manufacture method of the LED chip structure of the present invention
The schematic diagram of layer, n type gallium nitride layer, multiple quantum well light emitting layer and p-type gallium nitride layer.
Fig. 9 is shown as etching the p-type gallium nitride layer and the MQW in the manufacture method of the LED chip structure of the present invention
Luminescent layer, forms the schematic diagram of sunk area.
Figure 10 is shown as making P electrode on the p-type gallium nitride layer surface in the manufacture method of the LED chip structure of the present invention,
The schematic diagram of N electrode is made on the sunk area surface.
Figure 11 is shown as the light path schematic diagram in the LED chip structure without the pore array.
Figure 12 is shown as the light path schematic diagram in LED chip structure of the present invention with the pore array.
Component label instructions
S1～S5 steps
A, b figure cycle
1 Sapphire Substrate
2 pore arrays
3 cushions
4 n type gallium nitride layers
5 multiple quantum well light emitting layers
6 p-type gallium nitride layers
7 sunk areas
8 P electrodes
9 N electrodes
Specific embodiment
Embodiments of the present invention are illustrated below by way of specific instantiation, those skilled in the art can be by disclosed by this specification
Content understand easily the present invention other advantages and effect.The present invention can also be added by specific embodiments different in addition
To implement or apply, the every details in this specification can also be based on different viewpoints and application, in the essence without departing from the present invention
Various modifications and changes are carried out under god.
Refer to Fig. 1 to Figure 12.It should be noted that the diagram provided in the present embodiment only illustrates in a schematic way the present invention
Basic conception, only show in schema then with relevant component in the present invention rather than according to component count, shape during actual enforcement
And size is drawn, it is actual when the implementing kenel of each component, quantity and ratio can be a kind of random change, and its assembly layout
Kenel is likely to increasingly complex.
The present invention provides a kind of manufacture method of LED chip structure, refers to Fig. 1, is shown as the process chart of the method,
Comprise the following steps：
S1：One Sapphire Substrate is provided；
S2：Using laser is from the Sapphire Substrate back side illuminaton and focuses on inside the Sapphire Substrate, in the sapphire
Substrate interior forms pore array；
S3：In the sapphire substrate surface successively grown buffer layer, n type gallium nitride layer, multiple quantum well light emitting layer and p-type nitrogen
Change gallium layer；
S4：The p-type gallium nitride layer and the multiple quantum well light emitting layer are etched, sunk area, the sunk area exposure is formed
Go out the part surface of the n type gallium nitride layer；
S5：P electrode is made on the p-type gallium nitride layer surface, on the sunk area surface N electrode is made, obtain LED
Chip structure.
Referring initially to Fig. 2, execution step S1：One Sapphire Substrate 1 is provided.
Specifically, (the Al of the Sapphire Substrate 12O3) can be using plain film substrate or patterned substrate.Herein, it is described graphical
Substrate (Patterned Sapphire Substrate, PSS) refers to that surface has the Sapphire Substrate of figure.The forming method of figure
It is generally as follows：Dry etching mask is grown on a sapphire substrate, mask is carved into figure with the photoetching process of standard, utilize
ICP lithographic techniques etch sapphire, and remove mask, obtain figure.The growth GaN material in patterned substrate, can make
Longitudinal extension of GaN material is changed into horizontal extension, the dislocation density of GaN epitaxy material on the one hand can be effectively reduced, so as to subtract
The non-radiative recombination of little active area, reduces reverse leakage current, improves the life-span of LED；The light that another aspect active area sends, Jing
GaN and Sapphire Substrate interface Multiple Scattering, change the angle of emergence of total reflection light, light probability are increased out, so as to improve
The extraction efficiency of light.The reason for comprehensive these two aspects, the LED for making the emergent light brightness ratio of the LED grown on PSS traditional has
Improved, while reverse leakage current reduces, the life-span of LED is also extended.The pattern class of PSS is also more, makes at present
The figure of cone is similar to a kind of commonplace pattern, the figure cycle is about 3 μm, about 1.5 μm of height.Certainly,
The patterned substrate may also be employed other type figures.
Referring next to Fig. 3 to Fig. 7, execution step S2：Using laser is from the Sapphire Substrate back side illuminaton and focuses on institute
State inside Sapphire Substrate 1, in the Sapphire Substrate 1 pore array 2 is internally formed.
The fusing point of Sapphire Substrate is very high, 2045 DEG C is reached, in the present invention, using the characteristic of laser in the Sapphire Substrate 1
It is middle to form the pore array 2.
As an example, crossed irradiation using two beam laser, the pore is obtained at laser joint.Because two beam laser are being handed over
Interfere and offset on point, its energy is converted to interior energy by luminous energy, release amount of heat, the point is melted to form small sky
Hole.
As an example, the optical maser wavelength for adopting can be 1064nm, 355nm or 248nm.
It is pointed out that when forming the pore array using laser, at laser joint, sapphire on laser optical path
Substrate can't be destroyed, because laser still maintains luminous energy form when through transparent Sapphire Substrate, will not produce many waste heats
Amount, just can be converted into only at interference point interior can simultaneously melt material.
As shown in figure 3, being shown as schematic diagram of the pore array 2 including one layer of pore.Fig. 4 is shown as the pore array
A kind of plane figure, black arrow shows figure cycle a, the b in pore array in the both direction of primitive unit cell wherein in figure.
As an example, the altitude range of the pore is 0.5～5 μm, and width range is 0.1～3 μm.The pore array and institute
It is 1～200 μm to state the distance between Sapphire Substrate upper surface scope.
As an example, in the pore array 2, the figure cycle is 0.5～10 μm.It is pointed out that herein the figure cycle can
Think the figure cycle on different directions, for example, for the layout shown in Fig. 3, the figure cycle both can be a, also may be used
Being b.
Fig. 5 and Fig. 6 also show other two kinds of plane figures of the pore array.However, the pore array can also be in it
Its arrangement mode, should not too limit the scope of the invention herein.
Additionally, in other embodiments, the pore array 2 may also include at least two-layer pore.As shown in fig. 7, being shown as
The pore array 2 includes the situation of two-layer pore.
Pore present in the Sapphire Substrate 1 is different from sapphire refractive index, can increase the reflection or refraction of light, carries
High light-emitting efficiency.Meanwhile, the presence of pore in Sapphire Substrate can effectively reduce the stress of GaN epitaxial layer, improve LED's
Internal quantum efficiency.
Then Fig. 8, execution step S3 are referred to：In the nitridation of the surface of the Sapphire Substrate 1 successively grown buffer layer 3, N-type
Gallium layer 4, multiple quantum well light emitting layer 5 and p-type gallium nitride layer 6.
As an example, the material of the cushion 3 is GaN, and it can be monolayer GaN layer, also can be by low-temperature gan layer and height
Warm GaN layer is formed by stacking.The multiple quantum well layer 5 can be made up of shallow quantum well layer and multiple quantum well light emitting layer.Certainly, it is described
Cushion 3, n type gallium nitride layer 4, multiple quantum well light emitting layer 5 and p-type gallium nitride layer 6 can also have the functional layer knot for more refining
Structure, it is described too to limit the scope of the invention herein.
As an example, the cushion 3, N can be grown using MOCVD method or molecular beam epitaxy
Type gallium nitride layer 4, multiple quantum well light emitting layer 5 or p-type gallium nitride layer 6.Wherein metallo-organic compound chemical gaseous phase deposition
(Metal-organic Chemical Vapor Deposition, MOCVD) be with III race, the organic compound of II race's element and
V, hydride of VI race's element etc. as crystal growth source material, in pyrolysis mode in the enterprising circulation of qi promoting phase epitaxy of substrate,
Grow the thin layer monocrystal material of various III-V races, group Ⅱ-Ⅵ compound semiconductor and their multivariate solid solution.Generally
Crystal growth in MOCVD systems is all to lead to H under normal pressure or low pressure (10-100Torr)2Cold wall quartz (rustless steel) reative cell
In carry out, underlayer temperature be 500-1200 DEG C, with radio frequency induction heating graphite base (substrate base is above graphite base), H2
Metallorganics are carried to vitellarium by the fluid supply bubbling of temperature-controllable.Molecular beam epitaxy (Molecular Beam Epitaxy,
MBE it is) that Semiconductor substrate is placed in ultrahigh vacuum cavity, with the Bu Tong difference that the monocrystalline material for needing growth is pressed element
It is placed in jeting furnace (also in cavity).The molecular flow ejected by each element for being heated separately to relevant temperature can be in above-mentioned lining
The superlattice structure of very thin (monoatomic layer level can be as thin as) monocrystal and several metabolies is grown on bottom.The method growth
Temperature is low, can strictly control the thickness component and doping content of epitaxial layer, but system complex, and the speed of growth is slower.
Fig. 9, execution step S4 are referred to again：The p-type gallium nitride layer 6 and the multiple quantum well light emitting layer 5 are etched, is formed
Sunk area 7, the sunk area 7 exposes the part surface of the n type gallium nitride layer 4.
Finally refer to Figure 10, execution step S5：P electrode 8 is made on the surface of p-type gallium nitride layer 6, in the depression
Region surface makes N electrode 9, obtains LED chip structure.
The light path schematic diagram and the present invention that Figure 11 and Figure 12 are respectively indicated as in the LED chip structure without the pore array is carried
Light path schematic diagram in the LED chip structure of the pore array (light path is represented using black arrow).It can be seen that, band of the present invention
There is reflection and refraction of the pore array in the LED chip structure of pore array to light to greatly improve the light extraction efficiency of LED.
The manufacture method of the LED chip structure of the present invention forms pore array using laser technology in Sapphire Substrate, using gas
Hole is different from sapphire refractive index to make the light extraction efficiency of LED be improved significantly, and increases LED chip external quantum efficiency.
And the method is not limited to plain film or graphical sapphire substrate.Simultaneously because the presence of pore can be reduced effectively in Sapphire Substrate
The stress of GaN epitaxial layer, improves the internal quantum efficiency of LED.Two aspect factors more than comprehensive, can greatly improve LED's
Luminous efficiency.
Embodiment two
The present invention also provides a kind of LED chip structure, and as shown in Figure 10, the LED chip structure includes：
Sapphire Substrate 1；The Sapphire Substrate 1 has been internally formed pore array 2；
It is sequentially formed in cushion 3, n type gallium nitride layer 4, multiple quantum well light emitting layer 5 and the p-type of the sapphire substrate surface
Gallium nitride layer 6；
Through the p-type gallium nitride layer 5 and the multiple quantum well light emitting layer 6 and expose the part of n type gallium nitride layer 4
Depression in the surface region；
The P electrode 8 on the surface of p-type gallium nitride layer 6 is formed at, the N electrode 9 on the sunk area surface is formed at.
Specifically, the pore array 2 may include one or more layers pore.Each layer pore can be in but be not limited to such as Fig. 4 to Fig. 6
In any one layout type.
As an example, in the pore array 2, the figure cycle is 0.5～10 μm.The altitude range of the pore is 0.5～5 μm,
Width range is 0.1～3 μm.The distance between the pore array and Sapphire Substrate upper surface scope is 1～200 μm.
In the LED chip structure of the present invention, due to the presence of the pore array, the light extraction efficiency of LED not only can be improved,
And the stress of GaN epitaxial layer can be reduced, the internal quantum efficiency of LED is improved.
In sum, LED chip structure of the invention and preparation method thereof, using laser technology gas is formed in Sapphire Substrate
Hole array, makes the light extraction efficiency of LED be improved significantly using pore is different from sapphire refractive index, increases LED core
Piece external quantum efficiency.And the method is not limited to plain film or graphical sapphire substrate.Simultaneously because pore in Sapphire Substrate
Presence can effectively reduce the stress of GaN epitaxial layer, improve the internal quantum efficiency of LED.Two aspect factors more than comprehensive, can be with
Greatly improve the luminous efficiency of LED.So, the present invention effectively overcomes various shortcoming of the prior art and has high industrial profit
With value.
The principle and its effect of above-described embodiment only illustrative present invention, it is of the invention not for limiting.It is any to be familiar with this skill
The personage of art all can carry out modifications and changes under the spirit and the scope without prejudice to the present invention to above-described embodiment.Therefore, such as
Those of ordinary skill in the art completed under without departing from disclosed spirit and technological thought all etc.
Effect modifications and changes, should be covered by the claim of the present invention.
Claims (10)
1. a kind of manufacture method of LED chip structure, it is characterised in that comprise the following steps：
S1：One Sapphire Substrate is provided；
S2：Using laser is from the Sapphire Substrate back side illuminaton and focuses on inside the Sapphire Substrate, described blue precious
Stone lining bottom is internally formed pore array；
S3：In the sapphire substrate surface successively grown buffer layer, n type gallium nitride layer, multiple quantum well light emitting layer and P
Type gallium nitride layer；
S4：The p-type gallium nitride layer and the multiple quantum well light emitting layer are etched, sunk area, the sunk area is formed
Expose the part surface of the n type gallium nitride layer；
S5：P electrode is made on the p-type gallium nitride layer surface, on the sunk area surface N electrode is made, obtained
LED chip structure.
2. the manufacture method of LED chip structure according to claim 1, it is characterised in that：The Sapphire Substrate is plain film
Substrate or patterned substrate.
3. the manufacture method of LED chip structure according to claim 1, it is characterised in that：The optical maser wavelength is 1064nm.
4. the manufacture method of LED chip structure according to claim 1, it is characterised in that：In the pore array, figure
Cycle is 0.5～10 μm.
5. the manufacture method of LED chip structure according to claim 1, it is characterised in that：The altitude range of the pore is
0.5～5 μm, width range is 0.1～3 μm.
6. the manufacture method of LED chip structure according to claim 1, it is characterised in that：The pore array includes one layer
Pore or multilamellar pore.
7. the manufacture method of LED chip structure according to claim 1, it is characterised in that：The pore array and the indigo plant
The distance between gem substrate top surface scope is 1～200 μm.
8. the manufacture method of LED chip structure according to claim 1, it is characterised in that：In step S3, adopt
MOCVD method or molecular beam epitaxy grow the cushion, n type gallium nitride layer, Multiple-quantum
Trap luminescent layer or p-type gallium nitride layer.
9. a kind of LED chip structure, it is characterised in that include：
Sapphire Substrate；The Sapphire Substrate has been internally formed pore array；
It is sequentially formed in cushion, n type gallium nitride layer, multiple quantum well light emitting layer and the p-type nitrogen of the sapphire substrate surface
Change gallium layer；
Through the p-type gallium nitride layer and the multiple quantum well light emitting layer and expose the n type gallium nitride layer segment table
The sunk area in face；
The P electrode on the p-type gallium nitride layer surface is formed at, the N electrode on the sunk area surface is formed at.
10. LED chip structure according to claim 9, it is characterised in that：The pore array includes one or more layers pore.
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