CN106571396A - Partial Silicon-on-Insulator (PSOI) thin film-LDMOS transistor with short drift region - Google Patents
Partial Silicon-on-Insulator (PSOI) thin film-LDMOS transistor with short drift region Download PDFInfo
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- 239000012212 insulator Substances 0.000 title abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 138
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 138
- 239000010703 silicon Substances 0.000 claims abstract description 138
- 239000000758 substrate Substances 0.000 claims abstract description 47
- 239000010409 thin film Substances 0.000 claims abstract description 33
- 210000000746 body region Anatomy 0.000 claims description 43
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 38
- 229910052760 oxygen Inorganic materials 0.000 claims description 38
- 239000001301 oxygen Substances 0.000 claims description 38
- 239000000463 material Substances 0.000 claims description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 19
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 230000005611 electricity Effects 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 150000003376 silicon Chemical class 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 27
- 230000000694 effects Effects 0.000 description 16
- 239000004065 semiconductor Substances 0.000 description 9
- 230000005684 electric field Effects 0.000 description 8
- 241000209094 Oryza Species 0.000 description 6
- 235000007164 Oryza sativa Nutrition 0.000 description 6
- 235000009566 rice Nutrition 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 230000007423 decrease Effects 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 238000007667 floating Methods 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910000939 field's metal Inorganic materials 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
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- 150000002500 ions Chemical class 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- VDGJOQCBCPGFFD-UHFFFAOYSA-N oxygen(2-) silicon(4+) titanium(4+) Chemical compound [Si+4].[O-2].[O-2].[Ti+4] VDGJOQCBCPGFFD-UHFFFAOYSA-N 0.000 description 1
- 230000037361 pathway Effects 0.000 description 1
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- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a Partial Silicon-on-Insulator (PSOI) thin film-LDMOS transistor with a short drift region, and belongs to the electronic components field; the transistor at least comprises the following elements: a substrate layer; an oxide layer with a silicon window on one side and a buried oxide layer on the other side; a thin film layer comprising a source zone, an integral silicon zone, a drift region, and a leakage zone; a top layer comprising a thin oxide layer, a thick oxide layer, a grid electrode, a source electrode and a drain electrode. The PSOI-thin film-LDMOS transistor is miniature, has the short drift region, is high in breakdown voltage, low in low conduction resistance, high in driving capability, and can be applied to an electronic circuit board.
Description
Technical field
The present invention relates to a kind of transistor, more particularly to a kind of ldmos transistor.
Background technology
The development trend of semiconductor power integrated circuit can be divided into both direction, and the first is to high pressure, high power characteristics
Direction is developed, and other direction is to the development of intelligent, miniaturization.In current communication system and communicating terminal low-power consumption, little
Under the requirement of type, for power integrated circuit, its key problem is exactly under the premise of enough high back-pressures and power is ensured, such as
What further reduces the size of power device, so as to compatible with traditional silicon integrated circuit and realize that technique is integrated.
For high pressure characteristics and high-power performance, boost device power control capacity is mainly utilized（Breakdown voltage and work
Electric current）And device parameter performance index（Conducting resistance, operating frequency and switching speed etc.）To lift semiconductor power device
Performance.Based on this, various high-voltage LDMOS structures are suggested, such as based on the LDMOS of ladder step oxygen buried layer, based on super junction
LDMOS, LDMOS based on carborundum etc..
On the other hand, using silicon on partial insulative layer（PSOI）Structure, can overcome LDMOS device floater effect and from
Heat effect, boost device breakdown voltage can also improve the heat dispersion of device.But, traditional PSOI structure LDMOS thin film
Layer is thicker, and thickness is typically greater than 1 micron.And in order to reduce surface field, improve breakdown voltage, the length of drift region is general
Even 100 microns more than 15 microns, cause the RESURF of LDMOS（Reduction surface field, REduced SURface Field,
RESURF）Effect is poor.So, using silicon LDMOS on partial insulative layer（PSOI）Technology, designs a kind of small size, short drift
The LDMOS device in area, is that power device is integrated, a miniaturization important channel.Cause and existing ic process compatibility,
In the enterprising improvement of structure and the optimization design of existing PSOI LDMOS, can make device that excellent breakdown potential is kept under small size
The performances such as pressure, operating current, conducting resistance.Therefore, the present invention promotes partly to lead to high voltage power device and the fusion of integrated circuit
Body power integrated circuit has positive role to intelligent, miniaturization.
The content of the invention
The purpose of the present invention is provided on a kind of small size, the partial insulative layer with short drift region for power integrated circuit
Silicon thin film lateral double-diffused metal-oxide-semiconductor transistor；Small size, short drift region are realized on the transistor arrangement, is had
The characteristics of having high-breakdown-voltage, low on-resistance, high driving ability.
The object of the present invention is achieved like this：Thin film silicon ldmos transistor on a kind of partial insulative layer of short drift region,
The transistor at least includes：
One substrate layer；
One oxide layer, a part are silicon window, and another part is oxygen buried layer；
One thin layer, including a source region, a silicon body region, a drift region, a drain region；
One top layer, including a thin oxide layer, a thick oxide layer, a gate electrode, a source electrode, a drain electrode.
Used as the further restriction of the present invention, the substrate layer is located at bottom, and material is silicon, and the doping content of substrate layer is about
For 2.5 × 1014Individual atom/cubic centimetre is to 1 × 1017Individual atom/cubic centimetre.
Used as the further restriction of the present invention, the doping content of the substrate layer is 5 × 1014Individual atom/cubic centimetre.
Used as the further restriction of the present invention, the silicon window is located on substrate layer, the doping of silicon window adjacent with oxygen buried layer
Type is identical with substrate layer, the doping content about 1 × 10 of silicon window13Individual atom/cubic centimetre is to 1 × 1017Individual atom/cube
Centimetre, the material of the oxygen buried layer is silicon dioxide, and the thickness of oxygen buried layer is 0.4 micron.
Used as the further restriction of the present invention, the doping content of the silicon window is 1 × 1013Individual atom/cubic centimetre to 5 ×
1014Individual atom/cubic centimetre.
Used as the further restriction of the present invention, the oxygen buried layer adjustable length, oxygen buried layer border are minimum far from silicon body region border
For 0.1 micron, it is 1.7 microns to the maximum.
Used as the further restriction of the present invention, the oxygen buried layer border is 0.3 micron far from silicon body region frontier distance.
Used as the further restriction of the present invention, the thin layer is located on silicon window and oxygen buried layer, and the material of thin layer is
Silicon, the thickness of thin layer is 0.2 micron.
Used as the further restriction of the present invention, the silicon body region is located on silicon window, between source region and drift region, silicon body region
Length be 0.5 micron, the doping type of silicon body region is identical with substrate layer, and the doping content of silicon body region is 1 × 1017Individual atom/
Cubic centimetre.
Used as the further restriction of the present invention, the drift region exceedes half region and is located on oxygen buried layer, remaining area
On silicon window, drift region is located between silicon body region and drain region, and the length of drift region is 3.5 microns, the doping class of drift region
Type is with substrate layer conversely, the doping content of drift region is 4 × 1016Individual atom/cubic centimetre is to 1 × 1017Individual atom/cube li
Rice.
Used as the further restriction of the present invention, the doping content of the drift region is 8 × 1016Individual atom/cubic centimetre.
Used as the further restriction of the present invention, the source region is located on silicon window, and adjacent with silicon body region, the length of source region is
0.7 micron, the doping type and substrate layer of source region is conversely, the doping content of source region is 2 × 1019Individual atom/cubic centimetre.
Used as the further restriction of the present invention, the drain region is located on oxygen buried layer, the length in drain region adjacent with drift region
For 0.7 micron, from substrate layer conversely, the doping content in drain region is different with drift region, the doping in drain region is dense for the doping type in drain region
Spend for 2 × 1019Individual atom/cubic centimetre.
Used as the further restriction of the present invention, the thin oxide layer is on silicon body region, source region, drift region, and exceedes
60% region is located on silicon body region, and respectively on source region, drift region, the material of thin oxide layer is two to remaining two side areas
Silicon oxide, the thickness of thin oxide layer is 20 nanometers.
Used as the further restriction of the present invention, the thick oxide layer is located at drift region, on drain region, and more than 80% region
On drift region, remaining area is located on drain region, and the material of thick oxide layer is silicon dioxide, and the thickness of thick oxide layer is
50 nanometers.
Used as the further restriction of the present invention, the gate electrode is located on thin oxide layer, is covered in drift region and body silicon
The close marginal area in area, the gate electrode of thin oxide layer are equal to field plate electrode, and the material of gate electrode is metal or many for doping
Crystal silicon, the field plate electrode of gate electrode are different from the ladder step field plate electrode of routine LDMOS.
Used as the further restriction of the present invention, the field plate electrode adjustable length above drift region, field plate electrode is in body
Silicon area can at most extend 1.6 microns to drift region direction.
Used as the further restriction of the present invention, field plate electrode is micro- for 0.4 to the extended distance in drift region direction in silicon body region
Rice.
Used as the further restriction of the present invention, the source electrode, drain electrode are located on source region and drain region respectively, source electricity
Pole, the material of drain electrode are metal.
Used as the further restriction of the present invention, the transistor is a horizontal double diffusion field metal oxide semiconductcor field effect
Answer transistor.
Used as the further restriction of the present invention, the transistor is the horizontal double diffusion field gold of a part of insulating barrier silicon-on
Category oxide semiconductor field effect transistor.
Silicon on a kind of undersized, partial insulative layer with short drift region proposed by the invention（Partial
Silicon-on-Insulator, PSOI）Thin film lateral double diffusion metal oxide semiconductor（Thin Film Lateral
Double-diffused Metal-Oxide-Semiconductor, TF-LDMOS）Transistor, in source-drain area, silicon body region（Ditch
Road area）, the length of drift region and substrate, material, doping type and doping content, thin film layer thickness, oxygen buried layer thickness etc. are identical
Under conditions of, and under conditions of top layer insulation oxide, electrode material parameter are all consistent, with silicon on traditional insulating barrier
LDMOS（Conventional Silicon-on-Insulator LDMOS, CSOI LDMOS）Compare；The present invention is carried
The TF-LDMOS transistors of the partial insulative layer silicon-on with short drift region for going out, field plate electrode can modulate silicon thin film body
The electric field intensity on surface, can be effectively reduced surface field（Reduced Surface Field, RESURF）, simultaneously because
The silicon window that PSOI is introduced so that substrate layer can also share portion voltage, can further improve the breakdown voltage of device
（Breakdown Voltage, BV）, make TF-LDMOS transistors that more excellent high-voltage performance is remained in that under small size.Separately
Outward, TF-LDMOS transistors of the invention additionally provide thin film silicon to the conduction pathway of substrate, can prevent hole floating
Accumulate on body silicon, so as to inhibit the Kink effects of TF-LDMOS well.（Kink effects are that SOI MOS devices are distinctive posts
Come into force and answer, particularly evident is showed to N ditches MOS device.Main cause is to obtain foot in high field region of the channel electrons near drain junction
Enough energy, produce electron-hole pair by ionization by collision, and these electronics quickly pass through channel region arrival under electric field action
Drain region increases leakage current；And the current potential that hole then moves to body silicon layer Zhong Shitigui floatings area is raised, body silicon-source ties just to be formed
To biasing, the increase of silicon body region current potential causes the reduction of device threshold voltage, under identical source-drain voltage, will have bigger leakage
Electric current is exported, and there occurs the phenomenon that output characteristic curve is bent upwards, i.e. referred to as kink effects.）.
Description of the drawings
It is described for convenience, by silicon LDMOS on traditional insulating barrier（Conventional Silicon-on-
Insulator LDMOS, CSOI LDMOS）, the present invention partial insulative layer on silicon（Partial Silicon-on-
Insulator, PSOI）Thin film lateral double diffusion metal oxide semiconductor（Thin Film Lateral Double-
Diffused Metal-Oxide-Semiconductor, TF-LDMOS）Transistor, is abbreviated as CSOI-LDMOS, TF respectively
PSOI-LDMOS.It is abbreviated as in description figure respectively：CSOI、TF PSOI.
Fig. 1 is the schematic cross-section of the present invention.
The longitudinal electric field of Fig. 2, TF PSOI-LDMOS and CSOI-LDMOS is distributed and bears potential profile（Left vertical
For electric field intensity, right vertical is the potential for bearing, and transverse axis is vertical scale for y）.
Fig. 3, TF PSOI-LDMOS and CSOI-LDMOS surface electric field distribution figures in the x-direction（The longitudinal axis is electric field intensity,
Transverse axis is breadth wise dimension for x）.
The breakdown voltage of Fig. 4, TF PSOI-LDMOS and the schematic diagram of field plate scaling relation（The longitudinal axis is breakdown voltage, transverse axis
It is pole plate breadth wise dimension for x）.
The breakdown voltage of Fig. 5, TF PSOI-LDMOS and drain region, the relation schematic diagram of substrate layer doping content（The longitudinal axis is to hit
Voltage is worn, upper transverse axis is substrate layer doping content, and lower transverse axis is drift doping concentration）.
The breakdown voltage of Fig. 6, TF PSOI-LDMOS and the relation schematic diagram of silicon window doping content（The longitudinal axis is breakdown voltage,
Transverse axis is silicon window doping content）.
The output curve diagram of Fig. 7, TF PSOI-LDMOS and CSOI-LDMOS（The longitudinal axis be drain terminal electric current, transverse axis drain terminal electricity
Pressure）.
Fig. 8, hole concentration distribution in the x-direction and distribution in the y-direction in bulk silicon region（The longitudinal axis is hole concentration, Fig. 8
（a）Transverse axis is breadth wise dimension for x, Fig. 8（b）Transverse axis is vertical scale for y）.
In figure, 1 substrate layer, 2 silicon windows, 3 oxygen buried layers, 4 source regions, 5 silicon body regions, 6 drift regions, 7 drain regions, 8 thin oxide layers, 9 grid
Electrode, 10 thick oxide layers, 11 source electrodes, 12 drain electrodes.
Specific embodiment
Thin film silicon ldmos transistor on the partial insulative layer of a kind of short drift region as shown in Figure 1, the transistor are at least wrapped
Include：
Substrate layer 1, substrate layer 1 are located at bottom, the P-type semiconductor single crystal silicon material that doping type is formed for acceptor impurity, substrate
The doping content of layer 1 about 2.5 × 1014Individual atom/cubic centimetre is to 1 × 1017Individual atom/cubic centimetre, substrate layer 1 is most
Good doping content is 5 × 1014Individual atom/cubic centimetre；
Oxide layer, a part be silicon window 2, silicon window 2 be located at substrate layer 1 on, it is adjacent with oxygen buried layer 3, the doping type of silicon window 2 with
Substrate layer 1 is identical, the doping content about 1 × 10 of silicon window 213Individual atom/cubic centimetre is to 1 × 1017Individual atom/cubic centimetre,
The material of oxygen buried layer 3 is silicon dioxide, and the thickness of oxygen buried layer 3 is 0.4 micron, and the doping content of silicon window 2 is 1 × 1013Individual atom/
Cubic centimetre is to 5 × 1014Individual atom/cubic centimetre；Another part is oxygen buried layer 3, adopts thickness for 0.7 micron of titanium dioxide
Silicon, is the silica material formed with silicon etching technology and deposition technology, 3 adjustable length of oxygen buried layer, and 3 border of oxygen buried layer is away from body silicon
5 border of area is minimum 0.1 micron, is 1.7 microns to the maximum, and 3 border of oxygen buried layer is 0.3 micron far from 5 frontier distance of silicon body region；
Thin layer, including source region 4, silicon body region 5, drift region 6, drain region 7, thin layer are located on silicon window 2 and oxygen buried layer 3, thin film
The material of layer is silicon, and the thickness of thin layer is 0.2 micron, and source region 4 is located on silicon window 2, the length of source region 4 adjacent with silicon body region 5
Spend for 0.7 micron, the doping type and substrate layer 1 of source region 4 is conversely, the doping content of source region 4 is 2 × 1019Individual atom/cube li
Rice, silicon body region 5 are located on silicon window 2, between source region 4 and drift region 6, the length of silicon body region 5 is 0.5 micron, and silicon body region 5 is mixed
Miscellany type is identical with substrate layer 1, and the doping content of silicon body region 5 is 1 × 1017Individual atom/cubic centimetre, drift region 6 exceed half
Region is located on oxygen buried layer 3, and remaining area is located on silicon window 2, and drift region 6 is located between silicon body region 5 and drain region 7, drift
The length in area 6 is 3.5 microns, using lithographic technique, with ion implanting and is picked into being formed, doping type and the lining of drift region 6
Bottom 1 is conversely, the doping content of drift region 6 is 4 × 1016Individual atom/cubic centimetre is to 1 × 1017Individual atom/cubic centimetre, drift
The optimum doping concentration for moving area 6 is 8 × 1016Individual atom/cubic centimetre, drain region 7 are located on oxygen buried layer 3, with 6 phase of drift region
Neighbour, the length in drain region 7 is 0.7 micron, and the doping type and substrate layer 1 in drain region 7 is conversely, doping content and the drift region 6 in drain region 7
Difference, the doping content in drain region 7 is 2 × 1019Individual atom/cubic centimetre；
Top layer, including thin oxide layer 8, thick oxide layer 10, gate electrode 9, source electrode 11, drain electrode 12, thin oxide layer 8 are located at body silicon
Area 5, source region 4, on drift region 6, and be located on silicon body region 5 more than 60% region, remaining two side areas be located at respectively source region 4,
On drift region 6, the material of thin oxide layer 8 is silicon dioxide, and the thickness of thin oxide layer 8 is 20 nanometers, and thick oxide layer 10 is located at
On drift region 6, drain region 7, and it is located on drift region 6 more than 80% region, remaining area is located on drain region 7, thick oxide layer
10 material is silicon dioxide, and the thickness of thick oxide layer 10 is 50 nanometers, and gate electrode 9 is located on thin oxide layer 8, is covered in drift
Area 6 and the close marginal area in silicon body region 5 are moved, the gate electrode 9 of thin oxide layer 8 is equal to field plate electrode, and the material of gate electrode 9 is
Metal is DOPOS doped polycrystalline silicon, and the field plate electrode of gate electrode 9 is different with the terraced field plate electrode that walks of routine LDMOS, positioned at drift region 6
The field plate electrode adjustable length of top, field plate electrode at most can extend 1.6 micron to 6 direction of drift region in silicon body region 5, field plate
Electrode extended distance from silicon body region 5 to 6 direction of drift region be 0.4 micron, source electrode 11, drain electrode 12 respectively be located at source region 4
On drain region 7, source electrode 11, the material of drain electrode 12 are metal.
With reference to Figure of description, the present invention will be further described.
The present invention is obtained based on three-dimensional Sentaurus TCAD software simulation studies, is served as a contrast in analog simulation research
Bottom and source are grounded, and grid adds grid voltage, add source-drain voltage between source-drain electrode.
As shown in Fig. 2 x point of the y-axis starting point for Fig. 1, positive for y-axis downwards；X point of the x-axis starting point for Fig. 1, is x-axis to the right
It is positive.The N-type drift region of TF PSOI-LDMOS and CSOI-LDMOS/drain junction breakdown voltage is respectively set as 65 volts and 33 volts.
Wherein the N-type drift region doping content of TF PSOI-LDMOS and CSOI-LDMOS is respectively 8 × 1016Individual atom/cubic centimetre
With 4 × 1016Individual atom/cubic centimetre, the doping content of substrate layer is 5 × 1014Individual atom/cubic centimetre, xw=-1.1 microns,
Xfp=-1.0 microns.No matter as can be seen that at SOI/ oxygen buried layers interface or in oxygen buried layer, the electric field of TF PSOI-LDMOS is bright
Aobvious is all higher than CSOI-LDMOS, shows that TF PSOI-LDMOS can bear higher voltage, with more preferable high pressure characteristics.
As shown in figure 3, the N-type drift region of TF PSOI-LDMOS and CSOI-LDMOS/drain junction breakdown voltage is set respectively
For 65 volts and 33 volts, at the same the N-type drift region/drain junction breakdown voltage that give also TF PSOI-LDMOS be set as 33 volts so as to
It is compared with CSOI-LDMOS.Because TF PSOI-LDMOS have silicon window and CSOI-LDMOS is without silicon window, TF PSOI-LDMOS
First peak of surface field be by bottom surface grid edge effect and silicon window is different from oxygen buried layer dielectric coefficient causes, and CSOI-
First peak of surface field of LDMOS is only to be caused by the grid edge effect of bottom surface, from figure 3, it can be seen that TF PSOI-
The surface field of LDMOS is more much higher than CSOI-LDMOS.From fig. 3 it can also be seen that in same drift region/drain junction breakdown voltage
Under, the surface field peak of the drain terminal of TF PSOI-LDMOS almost disappears, and the surface field peak of the drain terminal of CSOI-LDMOS is still
Exist.Show silicon window（PSOI structures）Drain terminal electric field can be effectively reduced, strengthen RESURF, so as to improve breakdown voltage.Separately
Outward, whether soi structure or PSOI structures, the surface field of first peak of surface field of TF PSOI-LDMOS than drain terminal
Peak is high, illustrates that RESURF effects are more difficult to realize in small size device and Uniform Doped region, needs in device structure design
It is optimized with technological design.
As shown in figure 4, wherein the N-type drift region doping content of TF PSOI-LDMOS is 8 × 1016Individual atom/cube li
The doping content of rice, silicon window and substrate layer is 5 × 1014Individual atom/cubic centimetre.As can be seen that Fig. 4（a）Breakdown potential be pressed with
One peak, is that breakdown voltage can keep higher value, exceed 64 volts in 0.4 micron of extremely -1.1 micrometer range in xfp.
And Fig. 4（b）Middle breakdown potential is pressed with two peaks, xw>After -0.6 micron, breakdown voltage is significantly reduced, and breakdown voltage is below 60
Volt.Two figures show that xfp and xw affect the RESURF effects of device strongly.Work as xw>After -0.9 micron, Fig. 4（a）Show xw
Highest breakdown voltage is given when=- 1.1 microns.Therefore, xw=- 1.3 ~ -0.9 micron is preferable scope, is set in device
Xw=- 1.1 can be chosen in meter（Optimum distance away from channel region border is 0.3 micron）And xfp=- 1.0 micron（Extend
The optimal distance in channel region border is 0.4 micron）As parameters optimization, to obtain higher breakdown voltage.
As shown in figure 5, xw=- 1.1 micron related to TF PSOI-LDMOS oxygen buried layers are wherein taken, it is related to field plate
Xfp=- 1.0 micron, the doping content of silicon window is 5 × 1014Individual atom/cubic centimetre.From fig. 5, it can be seen that drift region is most
Good doping content is 8 × 1016Individual atom/cubic centimetre, the optimum doping concentration of substrate layer is 5 × 1014Individual atom/cube li
Rice.The RESURF effects and surface field intensity of the doping content appreciable impact device of drift region, so as to affect breakdown voltage.Compared with
The doping content of high or relatively low drift region can all reduce breakdown voltage.When the doping content of substrate layer is more than 5 × 1014Individual original
During son/cubic centimetre, the carrier screening effect of substrate layer will hinder to exhaust to substrate and develop so as to cause punch through voltage decline.
As shown in fig. 6, xw=- 1.1 micron related to the oxygen buried layer of TF PSOI-LDMOS are wherein taken, it is related to field plate
Xfp=- 1.0 micron, the doping content of drift region is 8 × 1016Individual atom/cubic centimetre, the doping content of substrate layer is 5
×1014Individual atom/cubic centimetre.From fig. 6, it can be seen that when the doping content of substrate layer is 5 × 1014Individual atom/cubic centimetre
When, the doping content of silicon window is equal to or less than 5 × 1014During individual atom/cubic centimetre, voltage decline is hardly caused punch through；But
It is if the doping content of silicon window increases above 5 × 1014During individual atom/cubic centimetre, breakdown voltage will decline.Reason is to work as silicon
When the doping content of window is too high, silicon forms carriers concentration is higher, and exhausting mainly is carried out in silicon window, will hinder to exhaust to lining
Bottom is developed, so as to cause punch through voltage decline.Therefore, the optimum doping concentration scope of silicon window is 1 × 1013Individual atom/cube li
Rice is to 5 × 1014Individual atom/cubic centimetre.
As shown in Figure 7, it can be seen that under same source-drain voltage, curved journey on the output curve diagram of TF PSOI-LDMOS
Degree is more much smaller than CSOI-LDMOS, and Kink effects mainly appear on CSOI-LDMOS devices, in TF PSOI-LDMOS devices
On almost occur without Kink effects.Its reason is, the LDMOS device of PSOI structures near drain region produced by highfield ionization
Hole be suppressed when being injected into floating silicon window.As the silicon window of TF PSOI-LDMOS is between membrane silicon layer and substrate layer,
These injection holes for entering into silicon window will be imported into the substrate of ground connection, so as to form hole accumulation, and then inhibit
The generation of Kink effects.
As shown in figure 8, wherein the doping content of drift region is 4 × 1016Individual atom/cubic centimetre, takes xw=0, and xfp=
0, grid voltage is 1.5 volts, and source-drain voltage is 8.5 volts.Can see, accumulation of the hole in CSOI-LDMOS devices silicon body region is remote high
In TF PSOI-LDMOS, show that the silicon window of TF PSOI-LDMOS devices can reduce the accumulation in hole, and by these holes
-- silicon window -- substrate layer from silicon body region, so as to restrained effectively Kink effects.
Above-described embodiment is the invention is not limited in, on the basis of technical scheme disclosed by the invention, the skill of this area
Art personnel are according to disclosed technology contents, it is not necessary to which performing creative labour just can make one to some of which technical characteristic
A little to replace and deform, these are replaced and deform within the scope of the present invention.
Claims (19)
1. thin film silicon ldmos transistor on a kind of partial insulative layer of short drift region, it is characterised in that the transistor is at least wrapped
Include：
One substrate layer；
One oxide layer, a part are silicon window, and another part is oxygen buried layer；
One thin layer, including a source region, a silicon body region, a drift region, a drain region；
One top layer, including a thin oxide layer, a thick oxide layer, a gate electrode, a source electrode, a drain electrode.
2. thin film silicon ldmos transistor on the partial insulative layer of short drift region according to claim 1, it is characterised in that
The substrate layer is located at bottom, and material is silicon, the doping content about 2.5 × 10 of substrate layer14Individual atom/cubic centimetre to 1 ×
1017Individual atom/cubic centimetre.
3. thin film silicon ldmos transistor on the partial insulative layer of short drift region according to claim 2, it is characterised in that
The doping content of the substrate layer is 5 × 1014Individual atom/cubic centimetre.
4. thin film silicon ldmos transistor on the partial insulative layer of short drift region according to claim 1, it is characterised in that
The silicon window is located on substrate layer, and adjacent with oxygen buried layer, the doping type of silicon window is identical with substrate layer, the doping content of silicon window
About 1 × 1013Individual atom/cubic centimetre is to 1 × 1017Individual atom/cubic centimetre, the material of the oxygen buried layer is silicon dioxide,
The thickness of oxygen buried layer is 0.4 micron.
5. thin film silicon ldmos transistor on the partial insulative layer of short drift region according to claim 4, it is characterised in that
The doping content of the silicon window is 1 × 1013Individual atom/cubic centimetre is to 5 × 1014Individual atom/cubic centimetre.
6. thin film silicon ldmos transistor on the partial insulative layer of short drift region according to claim 4, it is characterised in that
The oxygen buried layer adjustable length, minimum 0.1 micron far from silicon body region border of oxygen buried layer border, is 1.7 microns to the maximum.
7. thin film silicon ldmos transistor on the partial insulative layer of short drift region according to claim 6, it is characterised in that
The oxygen buried layer border is 0.3 micron far from silicon body region frontier distance.
8. thin film silicon ldmos transistor on the partial insulative layer of short drift region according to claim 1, it is characterised in that
The thin layer is located on silicon window and oxygen buried layer, and the material of thin layer is silicon, and the thickness of thin layer is 0.2 micron.
9. thin film silicon ldmos transistor on the partial insulative layer of short drift region according to claim 8, it is characterised in that
The silicon body region is located on silicon window, between source region and drift region, and the length of silicon body region is 0.5 micron, the doping class of silicon body region
Type is identical with substrate layer, and the doping content of silicon body region is 1 × 1017Individual atom/cubic centimetre.
10. thin film silicon ldmos transistor on the partial insulative layer of short drift region according to claim 8, it is characterised in that
The drift region exceed half region be located at oxygen buried layer on, remaining area be located at silicon window on, drift region be located at silicon body region and
Between drain region, the length of drift region is 3.5 microns, and the doping type and substrate layer of drift region is conversely, the doping content of drift region
For 4 × 1016Individual atom/cubic centimetre is to 1 × 1017Individual atom/cubic centimetre.
Thin film silicon ldmos transistor on the partial insulative layer of 11. short drift regions according to claim 10, its feature exist
In the doping content of the drift region is 8 × 1016Individual atom/cubic centimetre.
Thin film silicon ldmos transistor on the partial insulative layer of 12. short drift regions according to claim 8, it is characterised in that
The source region is located on silicon window, adjacent with silicon body region, and the length of source region is 0.7 micron, the doping type and substrate layer of source region
Conversely, the doping content of source region is 2 × 1019Individual atom/cubic centimetre.
Thin film silicon ldmos transistor on the partial insulative layer of 13. short drift regions according to claim 8, it is characterised in that
The drain region is located on oxygen buried layer, adjacent with drift region, and the length in drain region is 0.7 micron, the doping type and substrate in drain region
Conversely, the doping content in drain region is different from drift region, the doping content in drain region is 2 × 10 to layer19Individual atom/cubic centimetre.
Thin film silicon ldmos transistor on the partial insulative layer of 14. short drift regions according to claim 1, it is characterised in that
The thin oxide layer is on silicon body region, source region, drift region, and is located on silicon body region more than 60% region, remaining two lateral areas
Respectively on source region, drift region, the material of thin oxide layer is silicon dioxide, and the thickness of thin oxide layer is 20 nanometers in domain.
Thin film silicon ldmos transistor on the partial insulative layer of 15. short drift regions according to claim 1, it is characterised in that
The thick oxide layer is on drift region, drain region, and is located on drift region more than 80% region, and remaining area is located at drain region
On, the material of thick oxide layer is silicon dioxide, and the thickness of thick oxide layer is 50 nanometers.
Thin film silicon ldmos transistor on the partial insulative layer of 16. short drift regions according to claim 1, it is characterised in that
The gate electrode is located on thin oxide layer, is covered in drift region and the close marginal area in silicon body region, the grid electricity of thin oxide layer
Pole is equal to field plate electrode, and the material of gate electrode is metal or is DOPOS doped polycrystalline silicon, field plate electrode and the routine LDMOS of gate electrode
Ladder step field plate electrode it is different.
Thin film silicon ldmos transistor on the partial insulative layer of 17. short drift regions according to claim 16, its feature exist
In the field plate electrode adjustable length above drift region, field plate electrode can at most extend to drift region direction in silicon body region
1.6 micron.
Thin film silicon ldmos transistor on the partial insulative layer of 18. short drift regions according to claim 17, its feature exist
It it is 0.4 micron to the extended distance in drift region direction in silicon body region in, field plate electrode.
Thin film silicon ldmos transistor on the partial insulative layer of 19. short drift regions according to claim 1, it is characterised in that
The source electrode, drain electrode are located on source region and drain region respectively, and source electrode, the material of drain electrode are metal.
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| CN113013228A (en) * | 2021-02-24 | 2021-06-22 | 上海华力集成电路制造有限公司 | Method for improving LDMOS performance |
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| US20030190766A1 (en) * | 2002-04-08 | 2003-10-09 | Micron Technology, Inc. | Process for making a silicon-on-insulator ledge and structures achieved thereby |
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