CN106557440A - A kind of system and method for realizing logic analyser super large storage depth - Google Patents
A kind of system and method for realizing logic analyser super large storage depth Download PDFInfo
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- CN106557440A CN106557440A CN201611076227.XA CN201611076227A CN106557440A CN 106557440 A CN106557440 A CN 106557440A CN 201611076227 A CN201611076227 A CN 201611076227A CN 106557440 A CN106557440 A CN 106557440A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
Abstract
The present invention discloses a kind of system and method for realizing logic analyser super large storage depth, and the system includes logic analyser hardware circuit and logic analyser control module；Logic analyser hardware circuit is nursed one's health network by front end signal and carries out pretreatment to outside measured signal, and then Jing FPGA units are sampled to pretreated signal and planned as a whole to control and data stream transmitting is analyzed and display to logic analyser control module by usb interface unit；Logic analyser control module is realized for sampled data being uploaded directly into computer/mobile device internal memory.The present invention is by being designed to hardware device and control software part, allow the internal memory of computer or mobile device as the sampling memory of logic analyser using, it is achieved thereby that the storage depth that remote ultra-traditional design can be provided, super large storage depth can make logic analyser easily tackle the collection analysises work of big data quantity, and the smart machine R＆D work increasingly to popularize provides great convenience.
Description
Technical field
The invention belongs to logic analyser design field, and in particular to a kind of logic analyser super large storage depth realized
System and method.
Background technology
Logic analyser is a kind of instrument dedicated for gathering and analyzing digital signal, can be with certain frequency to quilt
Survey signal to be sampled, logical zero or logical one are converted into according to the magnitude of voltage of sampled point then, then these are continuous
" 0/1 " be linked to be digital waveform, further analyze to be made according to waveform, help technical staff pinpoint the problems, record
Data, critique system etc..
Logic analyser has two most important parameters：Sample rate and storage depth.Sample rate is to measured signal
Sample frequency, i.e. each second need to be to how many sampling points of measured signal averaged acquisition；When storage depth refers to that a sampling operation is completed
The maximum number of samples that can be collected altogether.Sample rate determines the time precision of collection, and the more high then time precision of sample rate is higher；
Storage depth determines the maximum time length that continuous acquisition can be carried out to measured signal, depth it is bigger can collection analysises
Data volume is bigger.
Now with the rapid popularization of all kinds of smart machines so that first floor system design also becomes increasingly complex, corresponding bottom
The data volume transmitted between each chip of layer or each module is just increasing, when these data of collection analysises are needed --- this
Exactly the maximum ample scope for abilities of logic analyser, just proposes bigger demand, because at least needing completely to adopt to storage depth
Total data in transmitting procedure of collection could provide analysis foundation to search BUG, system optimization etc..
But on current market main flow logic analyser, either stand alone type（Standalone）, still need to make with reference to computer
It is split type（Virtual type）, its storage depth directly depends on the size of its self-contained storing devices capacity, adopts mostly at present
It is SRAM or special fifo chips etc., storage depth is mostly general also to the sampling time between several MB, is converted in tens KB
That between several ms, and product is completed once design in tens us, its storage depth cannot just change, and this for once compared with
Being far from being enough for the signal transmission of big data quantity, leading in smart machine research and development so as to significantly limit logic analyser
The application of the aspect such as domain and big data quantity collection analysises.
The content of the invention
The technical problem to be solved is, for the defect such as storage depth in prior art is little, to propose a kind of real
The system and method for existing logic analyser super large storage depth, allows the internal memory of computer or mobile device as logic analyser
Sampling memory using, it is achieved thereby that the storage depth that remote ultra-traditional design can be provided, expands logic analyser
Range of application.
Present invention achieves such a design：The internal memory of computer or mobile device is made to deposit as the sampling of logic analyser
Reservoir using, specifically：
The present invention proposes a kind of system for realizing logic analyser super large storage depth：Including logic analyser hardware circuit and with
Its computer/mobile device end logic analyser control module connected by usb bus；The logic analyser hardware circuit bag
Include front end signal conditioning network, FPGA unit and usb interface unit；Front end signal conditioning network is carried out to outside measured signal
Pretreatment, FPGA unit are sampled to pretreated signal and are planned as a whole to control and spread data by usb interface unit
It is defeated to be analyzed and display to logic analyser control module；The logic analyser control module includes the bottom being sequentially connected with
USB drive modules, receiving cache queue module and data processing display module, the bottom USB drive modules and USB interface
Unit is connected, and realizes for sampled data being uploaded directly into computer/mobile device internal memory, expands logic analyser storage depth.
Further, the FPGA unit includes front-end sampling module, FIFO buffer modules and plans as a whole control logic mould
Block, the front-end sampling module is to sample to signal parallel, and Jing FIFO buffer modules caching, the pool control logic mould
Block receives the order that usb interface unit is issued, and is resolved to specific control logic, realizes the pool work of each intermodule.
Further, the usb interface unit adopts EZ-USB-FX2/FX3 chips, including high-speed transitions interface and control
Command processing module, the high-speed transitions module is to convert parallel data into the serial data on usb bus.
Further, the usb interface unit is connected with FPGA unit by its programmable GPIF interface, to realize filling
The bandwidth provided using USB interface is provided.
Further, the ram cell realization that the FIFO buffer modules are embedded using FPGA, to reach most efficient side
Formula.
Further, the data bandwidth that the front-end sampling module is produced is less than usb bus valid data transmission bandwidth, with
Realize keeping in the data that front-end sampling is come when usb bus are unable to secured transmission of payload data, again by number when can transmitting
According to being transported in bus.
Further, the capacity of the ram cell that the capacity of the FIFO buffer modules is embedded less than the fpga chip,
The capacity of such as optional FIFO buffer modules is 256Kb, preferably to keep the seriality of data transfer, even if there is other to set
Also it is unlikely to make data-transmission interruptions during standby shared same USB passages, so as to improve the scope of application and Consumer's Experience of equipment.
Further, the logic analyser control module also includes the user's control being connected with bottom USB drive modules
Interface module, the various controls at following hair family and setting command.
The present invention also proposes a kind of method for realizing logic analyser super large storage depth in addition：Comprise the following steps：A、
Logic analyser is connected by usb bus with computer/mobile device end, logic analyser hardware circuit is carried out to measured signal
After front-end sampling and pretreatment, sampled data is transported on usb interface unit by FIFO buffer modules, computer/movement sets
Standby end logic analyser control module receiving data；When B, logic analyser control module receiving data, buffered using queue-type
Pattern, processing procedure are as follows：
（1）Open up 4 groups of relief areas；
（2）Relief area is connected to bottom USB drive modules and drives layer receiving queue；
（3）In judging queue, whether data complete once to fill, if completing, execution step（4）, if it is not, then continuing to；
（4）Sampled data is read out, parallel execution of steps（5）And step（6）；
（5）Queue is reconnected to, execution step is circulated（3）To step（5）；
（6）UI interface display results are processed and are supplied to by data processing display module to sampled data.On the one hand protect
Card USB device drives layer always to have available space ceaselessly to fill data（Drive layer not by the shadow of application layer software time delay
Ring）, so as to the transmission for ensureing sampled data will not be interrupted, after on the other hand producing one group of valid data in queue, control
Module can process the data simultaneously, so as to control the carrying out of sampling process.
Compared with prior art, advantages of the present invention and good effect are：
The present invention is designed by the hardware device to logic analyser and control software part, makes computer or mobile device
Internal memory can be used as the sampling memory of logic analyser, it is achieved thereby that the storage that remote ultra-traditional design can be provided
Depth, the storage depth of super large can make logic analyser easily tackle the collection analysises work of big data quantity, be more and more general
And smart machine R＆D work provide great convenience.
Description of the drawings
Fig. 1 is the system architecture diagram described in the embodiment of the present invention 1；
Fig. 2 is FIFO buffer modules schematic diagram described in the embodiment of the present invention 1；
Fig. 3 is the logic analyser control module process chart described in the embodiment of the present invention 2.
Specific embodiment
In order to be more clearly understood from the above objects, features and advantages of the present invention, below in conjunction with the accompanying drawings and implement
The present invention will be further described for example.Many details are elaborated in the following description in order to fully understand the present invention,
But, the present invention can also be implemented using other modes described here are different from, therefore, the present invention is not limited to following public affairs
The specific embodiment opened.
PC its internal memory main flow for considering up till now is deposited capacity and has reached more than 4GB, main flow flat board and mobile phone
Memory size have also exceeded 2GB, and the update cycle of this kind of consumer-elcetronics devices is very short, its main flow memory size with
As Moore's Law is quickly increasing, averagely will double within each 18 months, from from the perspective of this development, its internal memory holds
Amount is almost infinite.Present invention achieves such a design：The internal memory of computer or mobile device is made as logic analyser
Sampling memory using, specifically：
Embodiment 1, Fig. 1 is referred to, the present embodiment proposes a kind of system for realizing logic analyser super large storage depth：Including logic
Analyser hardware circuit and pass through computer/mobile device end logic analyser control module that usb bus are connected with which；It is described to patrol
Collecting analyser hardware circuit includes front end signal conditioning network, FPGA unit and usb interface unit；Front end signal nurses one's health network
Pretreatment is carried out to outside measured signal, FPGA unit is sampled to pretreated signal and planned as a whole to control and by USB
Data stream transmitting is analyzed and display by interface unit to logic analyser control module；The logic analyser control module
Including the bottom USB drive modules, receiving cache queue module and the data processing display module that are sequentially connected with, the bottom
USB drive modules are connected with usb interface unit, and sampled data is uploaded directly into computer/mobile device internal memory by realization, and expansion is patrolled
Collect analyser storage depth.
In order to realize that sampled data is uploaded directly into the operation of computer/mobile device end memory, need to complete following several
The key Design of individual aspect：
1st, in hardware circuit FIFO design：
The FPGA unit includes front-end sampling module, FIFO buffer modules and plans as a whole control logic module, and the front end is adopted
Egf block is to sample to signal parallel, and Jing FIFO buffer modules caching, and the pool control logic module receives USB interface
The order that unit is issued, is resolved to specific control logic, realizes the pool work of each intermodule.
Because the valid data transmission on usb bus is not continuously, but what subpackage was carried out, and period can also
It is mingled with some necessary controlling transmission bags, it is ensured that sampled data continuously transmits and do not interrupt and be accomplished by designing a kind of FIFO bufferings
The data that front-end sampling is come can be kept in when usb bus are unable to secured transmission of payload data by device, again will when can transmitting
Data are transported in bus, as long as so ensureing that the data bandwidth that front-end sampling module is produced is less than USB valid data transmission belts
It is wide；And the capacity of FIFO buffer modules then needs to meet necessary bus time delay, several us generally need to be only reached, the FIFO delays
The capacity of die block is so that less than available RAM capacity in the fpga chip, as principle, capacity is scheduled on by the present embodiment
256Kbits, is to remain larger design capacity, or other reasonable values, so can preferably keep data to pass
Defeated seriality, even if being also unlikely to make data-transmission interruptions when there is miscellaneous equipment to share same USB passages, sets so as to improve
The standby scope of application and Consumer's Experience.Realize that the most efficient modes of FIFO are that, using FPGA embedded ram cell, the design is selected
This chip of XC3S200A, designed FIFO parts control principle refer to Fig. 2.
2nd, usb interface unit in hardware circuit（The preferred USB2.0/3.0 interface units of the present embodiment）, realize that string is simultaneously at a high speed
Conversion：
FPGA after the parallel sampling and caching for completing signal needs this parallel data is converted to the serial number on usb bus
According to can just upload to computer, usb interface unit described in the present embodiment adopts EZ-USB-FX2/FX3 chips（Correspond respectively to
USB2.0/3.0 interfaces）, including high-speed transitions interface and control command processing module, the high-speed transitions module is to by parallel
Data are converted to the serial data on usb bus.And pass through its programmable GPIF interface（That is " the GPIF interface lists in Fig. 2
Unit "）To realize the efficient connection with FPGA, so as to the bandwidth for making full use of USB2.0/3.0 interfaces to be provided.End reaction is arrived
User using it is upper be exactly " sample rate@port number " performance indications（The accessible highest sample rate i.e. under certain port number）,
Following performance can be provided under USB2.0 patterns（Passage is abbreviated as into CH in following parameter）：100M@3CH、50M@6CH、32M@
9CH、16M@16CH；Following performance can be provided under USB3.0 patterns：500M@6CH、400M@8CH、200M@16CH、100M@
32CH。
3rd, the pool control logic in hardware circuit：
FPGA is in addition to providing above-mentioned FIFO and Interface design, in addition it is also necessary to plan as a whole the work of each intermodule, logical analyses instrument control
Molding block also includes the user control interface module being connected with bottom USB drive modules, receives the order that USB interface is issued, will
Which resolves to specific control logic, and such as sample rate, sampling depth, passage enable etc. are arranged（As the sampling frequency dividing in Fig. 2 with
Fault processing unit etc.）；Produce adjustable threshold voltage benchmark；Gather various system modes and report computer etc..
Embodiment 2, the system according to embodiment 1, it is also proposed that a kind of logic analyser super large storage depth realized
Method, logic analyser hardware circuit are carried out to measured signal after front-end sampling and pretreatment, are buffered by one-level high speed FIFO
Module is transported to sampled data on USB2.0/3.0 interfaces, and on the one hand computer/mobile device end control module needs continuously not
Disconnected reads out the data flow, on the other hand needs to be analyzed data flow, reaches, and shows
On UI interfaces, control module is also responsible for the various controls of receive user and setting command simultaneously to complete specific function.
Specifically include following steps：A, logic analyser is connected by usb bus with computer/mobile device end, logic
Analyser hardware circuit carries out front-end sampling and pretreatment to measured signal（Control, adjusting thresholds etc. are triggered such as）Afterwards, pass through
One-level high speed FIFO buffer module is transported to sampled data on USB2.0/3.0 interfaces, computer/mobile device end logical analyses
Instrument control module receives the data that logic analyser is uploaded；When B, logic analyser control module receiving data, using queue-type
Buffer mode, due to current computer operating system（Including Windows/Linux/MacOS）It is not reality truly
When system, so the data transfer in control software aspect just has larger time delay unavoidably, and data are in the mistake for reading
Also need to carry out necessary process in journey, to control the stopping of sampling and the display of data etc..
So logic analyser control module can not be using single when the data that logic analyser hardware circuit is transmitted are received
One " read --- process " pattern, and need using queue-type buffer mode as shown in Figure 3, processing procedure is as follows：（1）Open
4 groups of relief areas are warded off, such as the present embodiment preferably opens up the relief area of 4 groups of 1MB, naturally it is also possible to be other modes, this programme pair
Open up group number and size is not limited；（2）Relief area is connected to bottom USB drive modules and drives layer receiving queue；（3）Judge team
In row, whether data complete once to fill, if completing, execution step（4）, if it is not, then continuing to；4）Sampled data is entered
Row reads, parallel execution of steps（5）And step（6）；（5）Queue is reconnected to, execution step is circulated（3）To step（5）；
（6）UI interface display results are processed and are supplied to by data processing display module to sampled data.On the one hand ensure USB
Device drive layer always has available space ceaselessly to fill data（Layer is driven not affected by application layer software time delay）, so as to
Ensure that the transmission of sampled data will not be interrupted, after on the other hand one group of valid data being produced in queue, control module can be with
Process the data simultaneously, so as to control the carrying out of sampling process.
The present invention is by split type（Virtual type）The creative system design of logic analyser, it is hard by logic analyser
The mode of the software of part equipment+run on computer or on mobile device realizes making the internal memory of computer or mobile device as logic
The sampling memory of analyser is using, it is achieved thereby that the storage depth that remote ultra-traditional design can be provided, can at present
The effect of at least Radix Achyranthis Bidentatae is reached, and so that storage depth can equally be received benefits in the case of without the need for any upgrading is done to equipment
In Moore's Law.
The logic analyser realized using the present invention can provide the user the storage depth of super large, and also deposit in future
In the possibility of infinite update, the update along with user in the future to its computer or mobile device, logic analyser storage are deep
Degree also can and then at double increase, this be traditional design logic analyser it is incomparable, with extensive popularization and application
Value.
The above, is only presently preferred embodiments of the present invention, is not the restriction for making other forms to the present invention, is appointed
What those skilled in the art possibly also with the disclosure above technology contents changed or be modified as equivalent variations etc.
Effect embodiment is applied to other fields, but every without departing from technical solution of the present invention content, according to the technical spirit of the present invention
Any simple modification, equivalent variations and the remodeling made to above example, still falls within the protection domain of technical solution of the present invention.
Claims (9)
1. a kind of system for realizing logic analyser super large storage depth, it is characterised in that：Including logic analyser hardware circuit
And pass through computer/mobile device end logic analyser control module that usb bus are connected with which；
The logic analyser hardware circuit includes front end signal conditioning network, FPGA unit and usb interface unit；Believe front end
Number conditioning network carries out pretreatment to outside measured signal, and FPGA unit sample to pretreated signal and planned as a whole to control
And data stream transmitting is analyzed and display to logic analyser control module by usb interface unit；
Bottom USB drive modules that the logic analyser control module includes being sequentially connected with, receiving cache queue module and
Data processing display module, the bottom USB drive modules are connected with usb interface unit, and sampled data is directly uploaded by realization
To computer/mobile device internal memory, expand logic analyser storage depth.
2. system according to claim 1, it is characterised in that：The FPGA unit includes that front-end sampling module, FIFO delay
Die block and pool control logic module, the front-end sampling module is to sample to signal parallel, and Jing FIFO buffering moulds
Block is cached, and the control logic module of planning as a whole receives the order that usb interface unit is issued, and is resolved to specific control and is patrolled
Volume, realize the pool work of each intermodule.
3. system according to claim 1, it is characterised in that：The usb interface unit adopts EZ-USB-FX2/FX3 cores
Piece, including high-speed transitions interface and control command processing module, the high-speed transitions module is to convert parallel data into USB
Serial data in bus.
4. system according to claim 3, it is characterised in that：The usb interface unit is connect by its programmable GPIF
Mouth is connected with FPGA unit.
5. system according to claim 1, it is characterised in that：The FIFO buffer modules are mono- using the RAM that FPGA is embedded
Unit realizes.
6. system according to claim 5, it is characterised in that：The data bandwidth that the front-end sampling module is produced is less than
Usb bus valid data transmission bandwidth.
7. system according to claim 6, it is characterised in that：The capacity of the FIFO buffer modules is less than the FPGA
The capacity of the embedded ram cell of chip.
8. the system according to any one of claim 1-7, it is characterised in that：The logic analyser control module also includes
The user control interface module being connected with bottom USB drive modules, the various controls at following hair family and setting command.
9. the method that system described in a kind of foundation claim 1 realizes logic analyser super large storage depth, it is characterised in that bag
Include following steps：
A, logic analyser is connected by usb bus with computer/mobile device end, logic analyser hardware circuit is to tested letter
After number carrying out front-end sampling and pretreatment, sampled data is transported on usb interface unit by FIFO buffer modules, logic point
Analyzer control module receiving data；
When B, logic analyser control module receiving data, using queue-type buffer mode, processing procedure is as follows：
（1）Open up 4 groups of relief areas；
（2）Relief area is connected to bottom USB drive modules and drives layer receiving queue；
（3）In judging queue, whether data complete once to fill, if completing, execution step（4）, if it is not, then continuing to；
（4）Sampled data is read out, parallel execution of steps（5）And step（6）；
（5）Queue is reconnected to, execution step is circulated（3）To step（5）；
（6）UI interface display results are processed and are supplied to by data processing display module to sampled data.
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| CN106557440B (en) | 2019-08-16 |
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