Invention content
It is an object of the invention to overcome the deficiencies of the prior art and provide a kind of electrographic recordings with dual seizure function
Instrument captures same data source according to the dual time base gear of user setting, while using different sample rates, with meet user for
Observe the diversified demand of waveform.
In order to realize the above goal of the invention, it includes acquisition mould that the present invention, which has the electrographic recording instrument of dual seizure function,
Block, central control module, trigger module, channel data selecting module, main waveform snap shot module, main Waveform caching module, capture
Waveform snap shot module, capture waveform front end caching and conversion module, memory control module, capture waveform rear end caching and conversion
Module, external memory, host computer, display screen, wherein central control module, trigger module, channel data selecting module, main wave
Shape snap shot module, main Waveform caching module, capture waveform snap shot module, capture waveform front end caching and conversion module, memory
Control module, capture waveform rear end caching are realized with conversion module in FPGA;
Acquisition module remembers that the number of channels of acquisition module is N, sample rate χ will be acquired for being acquired to data source
To N circuit-switched data streams be sent to channel selecting module;
The trigger parameter that central control module is used to receive host computer transmission is transmitted to trigger module, receives host computer and sends
Channel position n be transmitted to channel selecting module, receive the snap shot coefficient ε that host computer is sent1It is transmitted to main waveform snap shot module,
Receive the snap shot coefficient ε that host computer is sent2It is transmitted to capture waveform snap shot module, receives the main waveform write operation that host computer is sent
Instruction is transmitted to main Waveform caching module, and the instruction of capture waveform write operation and capture waveform read operation for receiving host computer transmission refer to
Order is transmitted to memory central control module, wherein capture waveform write operation instruction includes to write initial address, pre-trigger depth
Predepth and rear triggering depth postdepth;Main Wave data Data is read from main Waveform caching modulei2It is transmitted to upper
Machine writes full marking signal from memory central control module reception capture Wave data and is transmitted to host computer, after capture waveform
End caching receives capture Wave data with conversion module and is transmitted to host computer;
Trigger module is used to receive trigger condition from host computer, and corresponding trigger signal occurs and is sent to memory control mould
Block;
Channel selecting module receives channel position n, the channel n of gated acquisition module of central control module forwarding, receives
Its gathered data Data is simultaneously sent to main waveform snap shot module and capture waveform snap shot module;
Main waveform snap shot module receives the snap shot coefficient ε that central control module is sent1, gathered data Data is taken out
Point obtains main Wave data Datai1It is sent to main Waveform caching module;
Main Waveform caching module receives main Wave data Data after receiving main waveform write operation instructioni1It is cached;
It captures waveform snap shot module and receives the snap shot coefficient ε that central control module is sent2, gathered data Data is taken out
Point obtains capture Wave data Dataj1, it is sent to capture waveform front end caching and conversion module;
Capture waveform front end caching after receiving capture waveform write operation instruction, receives capture waveform number with conversion module
According to Dataj1It is cached, and is converted to the clock of external memorizer, the data Data that will be converted toj2Output is to depositing
Reservoir control module;
Memory control module receives the capture waveform write operation signal of central control module forwarding, according to writing initial address
The data Data that will be receivedj2External memorizer is written;The trigger signal that trigger module is sent is received, is judged whether to data
Dataj2It is triggered, if do not triggered, is not made any operation, if triggering, latch the triggering address tri_ of capture waveform
Addr continues that postdepth data are written to external memorizer, and then sending capture waveform to central control module writes full scale
Will signal;The capture waveform read operation signal for receiving central control module forwarding, calculates the reading initial address of external memory
Since begin_addr=tri_addr-predepth read α reading initial address from mass storage2A data are made
For data Dataj3It is sent to capture waveform rear end caching and conversion module;
Waveform rear end caching is captured to be used for data Data with conversion modulej3It is cached, and is converted to FIFO's
It reads under clock, the data Data that will be converted toj4It exports to memory control module central control module;
External memory is used to store the data Data of capture waveformj2;
Host computer receive channel selecting serial number n input by user, it is slow when base gear TiWith it is fast when base gear Tj, calculate main wave
Shape snap shot coefficient ε1With capture waveform snap shot coefficient ε2, wherein main waveform snap shot coefficient ε1Calculation formula it is as follows:
Wherein, α indicates that the data point that display screen shows that the main waveform of a frame needs, β indicate that display screen shows the lattice of main waveform
Number;
Capture waveform snap shot coefficient ε2Computational methods it is as follows:
It is solved to obtain applicable equivalent sampling rate χ according to following formula2With sampling number α2Combination:
χ2=α2/(β*Tj)
s.t.χ2≤χ,α2< δ
Wherein, α2Indicate that the sampling number of capture waveform, δ indicate the storage depth of external memorizer;
As needed in applicable equivalent sampling rate χ2With sampling number α2Combination in select one group, then calculate capture
Waveform snap shot coefficient ε2=χ/χ2;
The main waveform snap shot coefficient ε that host computer will be calculated1With capture waveform snap shot coefficient ε2It is sent to center control mould
Block, and send main waveform write operation signal and capture waveform write operation signal, capture waveform write operation letter to central control module
Number include writing initial address, pre-trigger depth predepth and rear triggering depth postdepth, wherein predepth+
Postdepth=α2;
Whenever host computer receives the main Wave data of a screen of central control module forwarding, i.e. α1A main Wave data, α1Table
Show the sampling number of main waveform, be then sent to display screen and shown, then judges whether that receiving central control module turns
The capture waveform of hair writes full marking signal, if it is, capture waveform read operation signal is sent to central control module, in reception
The capture Wave data of control module feedback is entreated, display screen is sent into and is shown, otherwise do not make any operation;
Display screen is used to the main Wave data to receiving and captures Wave data show.
There is the present invention electrographic recording instrument of dual seizure function, base gear when user selectes two by host computer to calculate
It obtains two different snap shot coefficients and is issued to corresponding module simultaneously, the waveform number with storage will be acquired under base gear when slow
According to as main Wave data, same data source is acquired with the Wave data of storage as capture using under base gear when fast
Wave data is shown main waveform and capture waveform by host computer simultaneously.
The present invention has the following technical effects:
(1) use the present invention that can be independently adjustable dual time base gear, to meet diversification of the user for observation waveform
Demand;
(2) in the present invention, base (low speed sample rate) obtains when main waveform uses slow, and main waveform scrolling display is convenient for user
It observes the trend of waveform variation, and captures base (i.e. high-speed sampling rate) when waveform uses fast and obtain, it can be according to trigger signal
Burst phenomenon in middle capture data source and details;
(3) present invention in main waveform and capture waveform while handle and transmission during, according to it is slow when base under
Main waveform and it is fast when base under capture waveform storage with processing time difference, judge in the transmission intercal of the main waveform of every frame
Whether the capture waveform in memory is filled with, and to which capture waveform is read out and be transmitted again, ensure that the company of two-way waveform
It is continuous and stable;
(4) for the present invention in realization " dual seizure " function, acquisition and storage for main waveform use electrographic recording instrument
Common acquisition function module, largely save FPGA internal logic resources.
Embodiment
Fig. 1 is a kind of specific implementation mode structure chart for the electrographic recording instrument that the present invention has dual seizure function.Such as Fig. 1 institutes
Show, it includes acquisition module 1, central control module 2, trigger module 3, channel that the present invention, which has the electrographic recording instrument of dual seizure function,
Data selecting module 4, main waveform snap shot module 5, main Waveform caching module 6, capture waveform snap shot module 7, capture waveform front end
Caching and conversion module 8, memory control module 9, capture waveform rear end caching and conversion module 10, external memory 11, on
Position machine 12, display screen 13, wherein central control module 2, trigger module 3, channel data selecting module 4, main waveform snap shot module
5, main Waveform caching module 6, capture waveform snap shot module 7, capture waveform front end caching and conversion module 8, memory control mould
Block 9, capture waveform rear end caching are with conversion module 10 in FPGA (Field-Programmable Gate Array, i.e. scene
Programmable gate array) in realize.Next each module is described in detail respectively.
Acquisition module 1 is for being acquired data source, and the number of channels of note acquisition module 1 is N, and sample rate χ will be adopted
The N circuit-switched data streams collected are sent to channel data selecting module.Acquisition module 1 uses the ADC collection plates on 128 tunnels in the present embodiment
Card, data bit width 16bit, sample rate 100MS/s.
Transfer of the central control module 2 for controlling information and date between host computer 12 and other each modules, including:
It receives the trigger parameter that host computer 12 is sent and is transmitted to trigger module 3, receive the channel position n that host computer 12 is sent
It is transmitted to channel data selecting module 4, receives the snap shot coefficient ε that host computer 12 is sent1It is transmitted to main waveform snap shot module 5, is connect
Receive the snap shot coefficient ε that host computer 12 is sent2It is transmitted to capture waveform snap shot module 7, the main waveform that host computer 12 is sent is received and writes
Operational order is transmitted to main Waveform caching module 6, receives the instruction of capture waveform write operation and capture waveform that host computer 12 is sent
Read operation instruction be transmitted to memory central control module 2, wherein capture waveform write operation instruction comprising write initial address, it is pre- touch
Send out depth predepth and rear triggering depth postdepth;
Main Wave data Data is read from main Waveform caching module 6i2It is transmitted to host computer 12, mould is controlled from memory center
The reception capture Wave data of block 2 writes full marking signal and is transmitted to host computer 12, from capture waveform rear end caching and conversion module 10
It receives capture Wave data and is transmitted to host computer 12.
Trigger module 3 is used to receive the trigger parameter of the forwarding of central control module 2, generates corresponding trigger signal and is sent to
Memory control module 9.
Channel data selecting module 4 receives the channel position n that central control module 2 forwards, the channel of gated acquisition module 1
N receives its gathered data Data and is sent to main waveform snap shot module 5 and capture waveform snap shot module 7.
Main waveform snap shot module 5 receives the snap shot coefficient ε that central control module 2 is sent1, gathered data Data is taken out
Point obtains main Wave data Datai1It is sent to main Waveform caching module 6.
Main Waveform caching module 6 receives main Wave data Data after receiving main waveform write operation instructioni1Delayed
It deposits.Due to the rolling mode under base when the sampling, storage and display of main waveform in the present invention are operated in slow, it is desirable to be able to when writing
The module of reading caches waveform, therefore main Waveform caching module 6 realized using the FIFO inside FPGA.Reading and writing data bit wide, which is arranged, is
ε, ε are the bit wide of data Data, are 16bit in the present embodiment, the storage depth of FIFO is arranged in the case where saving resource.
It captures waveform snap shot module 7 and receives the snap shot coefficient ε that central control module 2 is sent2, gathered data Data is carried out
Snap shot obtains capture Wave data Dataj1, it is sent to capture waveform front end caching and conversion module 8.
Capture waveform front end caching after receiving capture waveform write operation instruction, receives capture waveform with conversion module 8
Data Dataj1It is cached, and is converted to the clock of external memorizer, the data Data that will be converted toj2Output is extremely
Memory control module 9.Similarly, capture waveform front end caching also uses the FIFO inside FPGA to realize with conversion module 8, if
It is ε to set read-write bit wide, is 16bit in the present embodiment, to occupy minimum logical resource as the storage depth of rule setting FIFO.It enables
The read port clock of FIFO connects Dataj1Synchronised clock, be 100Mhz in the present embodiment, the write port clock connection of FIFO is deposited
The user clock of reservoir is 200Mhz in the present embodiment, to realize cross clock domain conversion of the data to external memorizer.
Memory control module 9 is used to carry out write operation control, data monitoring and read operation to external memorizer to control, tool
Hold in vivo as follows:
Memory control module 9 receives the capture waveform write operation signal that central control module 2 forwards, according to writing initially
The data Data that location will receivej2External memorizer is written;
Memory control module 9 receives the trigger signal that trigger module 3 is sent, and judges whether to data Dataj2It is touched
Hair, if do not triggered, do not make any operation, if triggering, latch capture waveform triggering address tri_addr, continue to
Postdepth data are written in external memorizer, and then sending capture waveform to central control module 2 writes full marking signal;
Storage control module receives the capture waveform read operation signal that central control module 2 forwards, and calculates external memory
11 reading initial address begin_addr=tri_addr-predepth, since reading initial address from mass storage
Read α2A data, as data Dataj3It is sent to capture waveform rear end caching and conversion module 10.
Waveform rear end caching is captured to be used for data Data with conversion module 10j3It is cached, and is converted to FIFO
Reading clock under, the data Data that will be converted toj4It exports to central control module 2.Similarly, capture waveform rear end caching with
Conversion module 10 also uses the FIFO inside FPGA to realize, setting read-write bit wide is ε, is set as rule using occupying minimum logical resource
Set the storage depth of FIFO.FIFO read port clocks connect the user clock of external memory, the connection of FIFO write port clocks
Dataj3Synchronised clock, with realize data to memory cross clock domain convert.
External memory 11 is used to store the data Data of capture waveformj2.Select external memorizer for type in the present embodiment
Number be IS61VPS51218A SSRAM, memory capacity 512k*18bit.
Host computer 12 is used to calculate the relevant parameter of dual seizure, and the data of dual seizure are handled and shown, has
Hold in vivo and includes:
Host computer 12 receive channel selecting serial number n input by user, trigger parameter, it is slow when base gear TiWith it is fast when base gear
Tj, main waveform snap shot coefficient and capture waveform snap shot coefficient are calculated, computational methods difference is as follows:
● main waveform snap shot coefficient
Note display screen 13 shows that the main waveform of a frame needs α data point, total β lattice, then the sampling time of a frame waveform is
β*Ti, then the time interval of two points is t on display screen 131=(β * TiThe display sample rate of)/α, main waveform are χ1=[α/(β *
Ti)], i.e., when base gear value can not be divided evenly when selection, choose χ1For approximate integer value, base when so as to calculate current
Main waveform snap shot coefficient under gear
13 1 frame waveform of display screen needs 1000 data points in the present embodiment, totally 10 lattice, per 100 points of lattice, therefore is arranged
Maximum storage depth is 1kpts.Base parameter table when Fig. 2 is main waveform in the present embodiment.As shown in Fig. 2, when base 200ms/
Under div, 2 time interval t of display1=(200ms*10)/1000=2ms, display sample rate χ1=1/2ms=500S/
S, so as to calculate snap shot coefficient ε1=100M/500=2 × 105。
● capture waveform snap shot coefficient
Remember that the storage depth of external memorizer is δ, wherein δ > > α.The sample rate χ of acquisition module 1 is capture waveform sampling
The upper limit of rate, therefore in the present invention, the base gear T when calculating fastjUnder equivalent sampling rate and sampling number must assure that two
Condition:
(a) ensure equivalent sampling rate as possible no more than χ the higher the better.
(b) ensure sampling number α2Less than currently stored depth δ.
Due to equivalent sampling rate χ2With sampling number α2Relational expression be χ2=α2/(β*Tj)α2=χ2*β*Tj, therefore basis
Following formula solves to obtain applicable equivalent sampling rate χ2With sampling number α2Combination:
χ2=α2/(β*Tj)
s.t.χ2≤χ,α2< δ
As needed in applicable equivalent sampling rate χ2With sampling number α2Combination in select one group, ordinary priority selection
Equivalent sampling rate χ2Maximum combination.Then capture waveform snap shot coefficient ε is calculated2=χ/χ2。
Fig. 3 is base parameter table when capturing waveform in the present embodiment.As shown in figure 3, the present embodiment setting capture waveform five
The storage depth of base gear is respectively 5kpts, 10kpts, 50kpts, 100kpts, 500kpts when a, and 100M samples for highest
Rate.Storage depth 100kpts, when base 10 μ s/div under, first determine equivalent sampling rate χ2For 100MS/s, then sampled point is calculated
Number is α2=(10 μ s*10) * 100M=10kpts, to calculate snap shot coefficient ε2=100M/100M=1, i.e. not snap shot;For another example
Storage depth 100kpts, when base 500 μ s/div under, if using highest sample rate 100M as equivalent sampling rate χ2, then sampling number
α2=(500 μ s*10) * 100M=500kpts are more than currently stored depth 100kpts, therefore first determine that sampling number is
100kpts calculates equivalent sampling rate χ2=100k/ (500 μ s*10)=20MS/s, to calculate snap shot coefficient ε2=100M/20M
=5, the snap shot coefficient 5 of calculating is sent to FPGA by host computer 12 by controller, and FPGA is by the data under 100M sample rates
DATAi15 carry out extracted at equal intervals data are divided by, form data DATA after snap shotj2With useful signal validj2, other when
Base gear and so on.As can be seen from FIG. 3, base gear has same equivalent sample rate when certain, therefore is caught for what is got
Obtain Wave data can at part free switching between base gear, consequently facilitating user observes interested waveform details.
Host computer 12 is by channel selecting serial number n, trigger parameter, the main waveform snap shot coefficient ε being calculated1With capture waveform
Snap shot coefficient ε2It is sent to central control module 2, and main waveform write operation signal and capture waveform are sent to central control module 2
Write operation signal, capture waveform write operation signal include write initial address, pre-trigger depth predepth and after trigger depth
Postdepth, wherein predepth+postdepth=α2.In general, in order to make in capture waveform trigger address it is corresponding
Data are located among display screen 13, enable predepth=α2/2。
Whenever host computer 12 receives the main Wave data of a screen of the forwarding of central control module 2, i.e. α1A main Wave data,
α1It indicates the sampling number of main waveform, is then sent to display screen 13 and is shown, then judge whether to receive central control
The capture waveform that module 2 forwards writes full marking signal, if it is, sending capture waveform read operation letter to central control module 2
Number, the capture Wave data that central control module 2 is fed back is received, display screen 13 is sent into and is shown, otherwise do not make any operation.
That is, host computer 12 is judged as currently whether having corresponding catch when carrying out main Wave data display every time
Wave data is obtained, if so, then reading and showing, is shown if it is not, reading the main Wave data of next frame, continues to sentence
It is disconnected whether to have corresponding capture Wave data, it so recycles, until user stops the operation of electrographic recording instrument.
Display screen 13 is used to the main Wave data to receiving and captures Wave data show.In general, it shows
Screen 13 can carry out snap shot before being shown to main Wave data and capture Wave data according to sampling number and display points.
Technical solution in order to better illustrate the present invention has the present invention work of the electrographic recording instrument of dual seizure function
It is briefly described as flow.After host computer 12 calculates snap shot coefficient according to the when base of user setting, it is issued to by controller
Main waveform snap shot module 5 carries out signal acquisition, channel data selecting module with capture waveform snap shot module 7, then acquisition module 1
The serial number of corresponding channel is sent to main waveform snap shot module 5 according to the channel position being arranged in host computer 12 and capture waveform is taken out
Point module 7.Main waveform snap shot module 5 and capture waveform snap shot module 7 carry out snap shot according to respective snap shot coefficient, are carried out at the same time
Caching.Main Wave data is buffered in main Waveform caching module 6, and reading feeding host computer 12 by controller is continuously displayed.
Capture Wave data is buffered in capture waveform front end caching and conversion module 8, and the clock to capturing Wave data is converted to outside
Then the clock of memory 11 stores capture Wave data to external memory 11 under the control of memory control module 9.
It deposits the trigger parameter generation trigger signal that trigger module 3 is arranged according to user in host computer 12 and is sent to memory control module
9, memory control module 9 is monitored capture Wave data, current triggering address is latched if being triggered, and monitor
Data volume in capture Wave data write-in external memory 11 passes through central control module 2 if triggering depth after reaching
Capture waveform, which is sent, to host computer 12 writes full marking signal.After host computer 12 often shows the main waveform of a screen, then judge whether to receive
Capture waveform writes full marking signal, if it is not, not making any operation, the main waveform of next screen is directly displayed, if so, then leading to
It crosses central control module 2 and issues capture waveform write operation signal, capture Wave data is read from external memory 11, through capture
It after waveform rear end caching and conversion module 10 carry out caching and clock conversion, is sent into host computer 12 and is shown, thus realization pair
The dual seizure of data source is shown.
Although the illustrative specific implementation mode of the present invention is described above, in order to the technology of the art
Personnel understand the present invention, it should be apparent that the present invention is not limited to the range of specific implementation mode, to the common skill of the art
For art personnel, if various change the attached claims limit and determine the spirit and scope of the present invention in, these
Variation is it will be apparent that all utilize the innovation and creation of present inventive concept in the row of protection.