CN106531810B - 一种分立的功率mos场效应管及其制造方法 - Google Patents

一种分立的功率mos场效应管及其制造方法 Download PDF

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CN106531810B
CN106531810B CN201611206763.7A CN201611206763A CN106531810B CN 106531810 B CN106531810 B CN 106531810B CN 201611206763 A CN201611206763 A CN 201611206763A CN 106531810 B CN106531810 B CN 106531810B
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谭在超
罗寅
丁国华
邹望杰
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Xi'an Kaiwei Semiconductor Co ltd
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET

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Abstract

本发明公开了一种分立的功率mos场效应管及其制造方法,在功率mos场效应管成型过程中,首先在外延层中形成源区,对成型的源区进行接触孔腐蚀,接触孔区域进行P+注入与原有P+区衔接形成P+区,然后进行金属淀积形成金属层,最终得到金属层与源区的N+和P+接触,工艺过程中减少了原有工艺过程中两次光刻腐蚀分别形成N+和P+的光刻过程,从而将功率MOS制造流程减少一次光刻,从而简化制造流程,降低生产成本,采用刻硅技术缩短了P+到金属层接触的路径,从而减小了寄生P+电阻,进而可抑制寄生NPN管的开启,有利于提高雪崩击穿耐量,采用先形成源区,再对成型的源区进行接触孔腐蚀,避免了由于N+浓度远高于P+浓度导致在接触孔光刻后的P+注入无法形成的麻烦。

Description

一种分立的功率mos场效应管及其制造方法
技术领域
本发明涉及半导体功率器件,特别是涉及一种分立的功率mos场效应管及其制造方法。
背景技术
传统的分立的功率mos场效应管制造方法通常包含7层光刻终端环光刻、有源区光刻、多晶硅光刻、N+光刻、接触孔光刻、金属光刻和钝化层光刻共7层光刻,而在N+注入时需要使用N+光刻来确定N+注入区域,否则,不该被注入的P+区域会被注入N+,由于通常N+浓度远高于P+浓度,这就会导致在接触孔光刻后的P+注入无法形成,则无法形成P+接触区域,工艺繁琐且不易形成,如图1所示。功率MOS的制造技术复杂度以及成本高低主要取决于光刻层次的多少,光刻层次多,则制造流程复杂,成本较高,反之,则制造流程简化,成本较低。
发明内容
本发明的目的在于提供一种分立的功率mos场效应管及其制造方法,以克服现有技术的不足。
为达到上述目的,本发明采用如下技术方案:
一种分立的功率mos场效应管的制造方法,具体包括以下步骤:
步骤1),首先对衬底外延层外侧进行氧化,再进行终端工艺形成终端;
步骤2),然后在外延层中形成源区;
步骤3),通过接触孔光刻选择要形成接触孔的区域,并进行接触孔腐蚀;
步骤4),接触孔区域进行P+注入与原有P+区衔接形成P+区,然后进行金属淀积形成金属层,最终得到金属层与源区的N+和P+接触。
进一步的,具体的,步骤1)中,对衬底外延层外侧进行氧化后依次进行终端环光刻、终端环注入、终端环推进、场氧化后形成终端。
进一步的,步骤2)中,在需要形成源区的外延层中进行有源区光刻,然后进行有源区腐蚀,然后在待形成源区两侧进行JFET注入和栅氧生长,然后进行多晶硅淀积和多晶硅掺杂,然后对多晶硅淀积后区域进行多晶硅光刻和多晶硅刻蚀,然后依次进行Pbody注入、Pbody推进、N+注入、P+注入、BPSG淀积、BPSG回流最终形成源区。
进一步的,步骤3)中,进行接触孔腐蚀时对其他区域使用光刻胶进行保护,不被腐蚀,在接触孔腐蚀时,先将表面的介质层腐蚀掉,然后通过对硅的腐蚀,将N+区硅腐蚀掉至P+区。
进一步的,步骤4)后将器件的源极引出,金属层在接触孔底部与P+接触,将器件的衬底引出,并且与源极短接在一起。
进一步的,衬底为N型衬底。
一种功率mos场效应管,包括衬底以及衬底上的外延层,外延层上的沟道区内设有源区,外延层上依次设有栅极、层间介质和金属层,源区中的N+和P+均与金属层接触。
进一步的,所述衬底为N型衬底。
进一步的,具体的金属层底部与P+接触,金属层两侧与N+侧壁接触,其中N+底线与P+上线平齐。
进一步的,源区两侧设有JFET注入层。
与现有技术相比,本发明具有以下有益的技术效果:
本发明一种分立的功率mos场效应管及其制造方法,在功率mos场效应管成型过程中,首先在外延层中形成源区,对成型的源区进行接触孔腐蚀,接触孔区域进行P+注入与原有P+区衔接形成P+区,然后进行金属淀积形成金属层,最终得到金属层与源区的N+和P+接触,工艺过程中减少了原有工艺过程中两次光刻腐蚀分别形成N+和P+的光刻过程,从而将功率MOS制造流程减少一次光刻,从而简化制造流程,降低生产成本,采用刻硅技术缩短了P+到金属层接触的路径,从而减小了寄生P+电阻,进而可抑制寄生NPN管的开启,有利于提高雪崩击穿耐量,采用先形成源区,再对成型的源区进行接触孔腐蚀,避免了由于N+浓度远高于P+浓度导致在接触孔光刻后的P+注入无法形成,则无法形成P+接触区域的麻烦。
附图说明
图1为现有mos场效应管结构示意图。
图2为本发明mos场效应管结构示意图。
图3为本发明mos场效应管进行接触孔腐蚀前结构示意图。
图4为本发明mos场效应管进行接触孔腐蚀后结构示意图。
图5为本发明mos场效应管进行接触孔区域进行P+注入后结构示意图。
其中,1、栅极;2、层间介质;3、金属层;4、外延层;5、JFET注入层。
具体实施方式
下面结合附图对本发明做进一步详细描述:
一种分立的功率mos场效应管的制造方法,具体包括以下步骤:
步骤1),首先对衬底外延层外侧进行氧化,再进行终端工艺形成终端;
具体的,对衬底外延层外侧进行氧化后依次进行终端环光刻、终端环注入、终端环推进、场氧化后形成终端;
其中衬底为N型衬底;
步骤2),然后在外延层中形成源区;
在需要形成源区的外延层中进行有源区光刻,然后进行有源区腐蚀,然后在待形成源区两侧进行JFET注入和栅氧生长,然后进行多晶硅淀积和多晶硅掺杂,然后对多晶硅淀积后区域进行多晶硅光刻和多晶硅刻蚀,然后依次进行Pbody注入、Pbody推进、N+注入、P+注入、BPSG淀积、BPSG回流最终形成源区;
步骤3),通过接触孔光刻选择要形成接触孔的区域,并进行接触孔腐蚀;
并对其他区域使用光刻胶进行保护,不被腐蚀,在接触孔腐蚀时,先将表面的介质层腐蚀掉,然后通过对硅的腐蚀,将N+区硅腐蚀掉至P+区,
步骤4),接触孔区域进行P+注入与原有P+区衔接形成P+区,然后进行金属淀积形成金属层,最终得到金属层与源区的N+和P+接触。
最终将器件的源极引出,介质层金属在接触孔底部与P+接触,将器件的衬底引出,并且与源极短接在一起,具体形成过程如图3至图5所示。
如图2所示,一种分立的功率mos场效应管,包括N型衬底以及N型衬底上的外延层,外延层上通过Pbody注入推进形成的沟道区,外延层上依次设有多晶硅形成的栅极、BPSG淀积形成的层间介质和金属层,外延层上通过N+注入形成源区,源区中的N+和P+均与金属层接触,金属层底部与P+接触,金属层两侧与N+侧壁接触,源区Pbody两侧设有JFET注入层,其中N+底线与P+上线平齐。

Claims (4)

1.一种分立的功率mos场效应管的制造方法,其特征在于,具体包括以下步骤:
步骤1),首先对衬底外延层外侧进行氧化,再进行终端工艺形成终端;对衬底外延层外侧进行氧化后依次进行终端环光刻、终端环注入、终端环推进、场氧化后形成终端;
步骤2),然后在外延层中形成源区;在需要形成源区的外延层中进行有源区光刻,然后进行有源区腐蚀,然后在待形成源区两侧进行JFET注入和栅氧生长,然后进行多晶硅淀积和多晶硅掺杂,然后对多晶硅淀积后区域进行多晶硅光刻和多晶硅刻蚀,然后依次进行Pbody注入、Pbody推进、N+注入、P+注入、BPSG淀积、BPSG回流最终形成源区;
步骤3),通过接触孔光刻选择要形成接触孔的区域,并进行接触孔腐蚀;进行接触孔腐蚀时对其他区域使用光刻胶进行保护,不被腐蚀,在接触孔腐蚀时,先将表面的介质层腐蚀掉,然后通过对硅的腐蚀,将N+区硅腐蚀掉至P+区;N+区和P+区间隔;
步骤4),接触孔区域进行P+注入与原有P+区衔接形成P+区,然后进行金属淀积形成金属层,最终得到金属层与源区的N+和 P+接触;后将器件的源极引出,金属层在接触孔底部与P+接触,将器件的衬底引出,并且与源极短接在一起;所述衬底为N型衬底;具体的金属层底部与P+接触,金属层两侧与N+侧壁接触,其中N+底线与P+上线平齐。
2.一种根据权利要求1所述制造方法得到的功率mos场效应管,其特征在于,包括衬底以及衬底上的外延层,外延层上的沟道区内设有源区,外延层上依次设有栅极、层间介质和金属层,源区中的N+和P+均与金属层接触。
3.根据权利要求2所述功率mos场效应管,其特征在于,所述衬底为N型衬底。
4.根据权利要求2所述功率mos场效应管,其特征在于,源区两侧设有JFET注入层。
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