CN106527402A - FPGA debugging conversion equipment, system and method - Google Patents
FPGA debugging conversion equipment, system and method Download PDFInfo
- Publication number
- CN106527402A CN106527402A CN201611109445.9A CN201611109445A CN106527402A CN 106527402 A CN106527402 A CN 106527402A CN 201611109445 A CN201611109445 A CN 201611109445A CN 106527402 A CN106527402 A CN 106527402A
- Authority
- CN
- China
- Prior art keywords
- debugging
- fpga
- instruction
- data
- main frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B23/00—Testing or monitoring of control systems or parts thereof
- G05B23/02—Electric testing or monitoring
- G05B23/0205—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults
- G05B23/0218—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults characterised by the fault detection method dealing with either existing or incipient faults
- G05B23/0256—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults characterised by the fault detection method dealing with either existing or incipient faults injecting test signals and analyzing monitored process response, e.g. injecting the test signal while interrupting the normal operation of the monitored system; superimposing the test signal onto a control signal during normal operation of the monitored system
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/24—Pc safety
- G05B2219/24065—Real time diagnostics
Abstract
The present invention provides FPGA debugging conversion equipment, a system and a method. A parallel interface is connected with a debugging host through a parallel bus. A serial interface is connected with a to-be-debugged target FPGA device through a serial bus. An instruction processor receives a first debugging instruction sent from the debugging host and acquires debugging data corresponding to the first debugging instruction. After that, the debugging data are converted into serial signal format data and the serial signal format data are sent to the to-be-debugged target FPGA device. In this way, the conventional process that a single signal line is controlled to convert debugging data into serial signal format data in the analog serial timing manner based on the software of the debugging host is not conducted. According to the invention, the debugging data are transmitted to the FPGA debugging conversion equipment and then the debugging data are processed and converted into serial signal format data by the format conversion chip of the FPGA debugging conversion equipment. After that, the obtained serial signal format data are sent to the to-be-debugged target FPGA device. Therefore, the bandwidth of the parallel bus is fully utilized, and the data transmission speed between the debugging host and the FPGA debugging conversion equipment is improved. The requirements of FPGA debugging are better met.
Description
Technical field
The present invention relates to FPGA (Field-Programmable Gate Array, field programmable gate array) field,
Specifically related to a kind of FPGA debugging conversion equipment, system and method.
Background technology
, used as a kind of semi-custon logic circuit, powerful because of which, the construction cycle is short for FPGA, the advantage such as can change repeatedly,
It is widely used in communication, industry control, video, among the field such as security protection or even defence and military.For FPGA, field-programmable
Property be one of maximum advantage, meanwhile, in the development process of FPGA, debugged also particularly significant to FPGA, and with collection
Into the fast development of circuit engineering, the integrated level of fpga chip also more and more higher, fpga chip debugging difficulty are also increasing, because
This needs FPGA producers to provide at a high speed, reliable FPGA programmings, debugging apparatus.
Common, FPGA producers can provide USB interface-based FPGA commissioning devices, but because USB use ranges are wide, behaviour
The reason for making simple, and be easy for storage device etc., easily causes and divulges a secret.In order to solve the problems, such as that USB interface is easily divulged a secret,
FPGA producers can provide the commissioning device based on parallel bus, control single signal using software particular by debugging main frame
Line simulates the mode of serial sequential, tune-up data is converted into serial signal formatted data, then is sent to tune by parallel bus
Examination equipment carries out level conversion, and serial signal formatted data after level conversion is handed down to target FPGA to be debugged by commissioning device
Device is debugged.But as tune-up data is to control single holding wire by software on debugging main frame to simulate serial sequential
Mode is converted into serial signal formatted data, which results in send data to commissioning device transmission speed it is very slow, no
The bandwidth of parallel bus can be made full use of, it is difficult to meet the debugging demand of FPGA, for this provide one kind can improve debug main frame and
The new FPGA commissioning devices of the data transmission bauds between commissioning device are just extremely necessary.
The content of the invention
The main technical problem to be solved in the present invention is to provide a kind of FPGA debugging conversion equipment, system and method, can carry
High data transmission bauds, better meets FPGA debugging demands.
To solve above-mentioned technical problem, the present invention provides a kind of FPGA and debugs conversion equipment, and the FPGA debugging conversion sets
It is standby to include：Form conversion chip, the form conversion chip include the parallel interface being connected with debugging main frame by parallel bus,
The serial line interface being connected with target FPGA device to be debugged by universal serial bus, and instruction processing unit；
The instruction processing unit is used to receive the first debugging instruction that the debugging main frame is sent by the parallel interface,
And obtain the corresponding tune-up data of first debugging instruction；And for the tune-up data is converted into serial signal form
Data are handed down to the target FPGA device to be debugged by the serial line interface.
Further, the instruction processing unit comprising parallel bus controller, instruction parser, series bus controller with
And data buffer；
The parallel bus controller is used for the first modulation instructions received from the parallel interface and is handed down to described
Instruction parser；
The instruction parser is instructed for parsing to first modulation instructions and being sent to the debugging main frame
Resolution response；
The data buffer is used to receiving and preserving the tune that the debugging main frame is issued according to the instruction resolution response
Examination data；
The series bus controller for read from the data buffer tune-up data and be converted to correspondence
Serial signal formatted data after the target FPGA device to be debugged is handed down to by the serial line interface.
Further, the parallel bus controller be additionally operable to receive from the parallel interface the second modulation instructions simultaneously
It is handed down to the instruction parser；And for service data is extracted from the data buffer and parallel signal lattice are converted into
Formula is sent to the debugging main frame by the parallel interface；
The instruction parser is additionally operable to receive second debugging instruction from the debugging main frame by the parallel interface, and
The data acquisition instruction that obtains will be carried out parsing to second debugging instruction and be handed down to the series bus controller；
The series bus controller is handed down to after being additionally operable to for data acquisition instruction to be converted into serial signal form
The serial line interface of the target FPGA device connection to be debugged, and the target FPGA device to be debugged is received according to the number
The service data fed back by the universal serial bus is instructed according to obtaining, and the service data is stored in into the data buffer
In.
Further, the parallel bus controller is additionally operable to receiving first debugging instruction and the second debugging instruction
Before, receive the 3rd debugging instruction from the parallel interface and be handed down to the instruction parser；
The instruction parser is additionally operable to parse the 3rd modulation instructions, obtains project to be configured and configuration
Data；The project to be configured is configured according to the configuration data.
Further, the universal serial bus includes two buses of JTAG and SPI, and the serial line interface includes JTAG and SPI
Dual serial interface, the series bus controller include JTAG and SPI dual serial bus control units；
3rd debugging instruction includes universal serial bus type indication information；
The instruction parser for according to the bus type configured information from JTAG the and SPI dual serials bus
One is selected in controller and enters line activating.
Further, the parallel interface includes standard parallel interface and expanded function parallel interface；3rd debugging
Instruction includes parallel interface type configured information；
The instruction parser is additionally operable to carry out the 3rd modulation instructions parsing and obtains the interface type indicate letter
Breath, and it is sent to the parallel bus controller；
The parallel bus controller for according to the interface type configured information enable the standard parallel interface and
One in expanded function parallel interface.
Further, the parallel bus controller be additionally operable to receive from it is described debugging main frame the 3rd debugging refer to
Before order, after electricity on FPGA debugging conversion equipments, the standard parallel interface is enabled.
Further, the FPGA debugging conversion equipment also includes the first level buffer device and second electrical level buffer；
The first level buffer device for by it is described debugging main frame send each debugging instruction and tune-up data level
The operation level that the FPGA debugs conversion equipment is converted to, and for the FPGA to be debugged the data of conversion equipment feedback
Level conversion be it is described debugging main frame operation level；
The second electrical level buffer is handed down to target FPGA to be debugged for the FPGA is debugged conversion equipment
The level conversion of the serial signal formatted data of device is the operation level of the target FPGA device to be debugged, and for inciting somebody to action
The level conversion of the service data that the target FPGA device to be debugged sends is the work electricity of the FPGA debugging conversion equipment
It is flat.
Present invention also offers a kind of FPGA debugs converting system, the FPGA debugging converting system includes：Debugging main frame
And any of the above-described kind of FPGA debugs conversion equipment；
The debugging main frame is connected by the parallel interface that parallel bus and the FPGA debug conversion equipment, and to described
Parallel interface issues the first debugging instruction and tune-up data corresponding with first debugging instruction；
The instruction processing unit of FPGA debugging conversion equipment receive the debugging main frame issue the first debugging instruction and
Tune-up data corresponding with first debugging instruction, and the tune-up data is converted into into serial signal formatted data by institute
The serial line interface for stating FPGA debugging conversion equipments is handed down to target FPGA device to be debugged.
Present invention also offers a kind of FPGA debugs conversion method, the FPGA debugging conversion method is applied to above-mentioned FPGA
On debugging conversion equipment, including：
The parallel interface that the FPGA debugs conversion equipment is connected with debugging main frame by parallel bus, and form is turned
The serial line interface for changing chip is connected with target FPGA device to be debugged by universal serial bus；
The FPGA debugging conversion equipment is received the debugging main frame and is referred to by the first debugging that the parallel interface sends
Order, and obtain the corresponding tune-up data of first debugging instruction；
The tune-up data is converted into serial signal formatted data and by the string by the FPGA debugging conversion equipments
Line interface is handed down to the target FPGA device to be debugged.
Beneficial effect
The present invention provides a kind of FPGA debugging conversion equipment, system and method, including form conversion chip, form conversion core
Piece includes parallel interface, serial line interface and instruction processing unit.Wherein, parallel interface is by parallel bus and debugging main frame
Connection；Serial line interface is connected with target FPGA device to be debugged by universal serial bus；Instruction processing unit receives debugging main frame and passes through
The first debugging instruction that parallel interface sends, and the corresponding tune-up data of the first debugging instruction is obtained, tune-up data is converted into
Serial signal formatted data is handed down to target FPGA device to be debugged by serial line interface.So no longer be debugging main frame on by
The serial signal formatted data that tune-up data is converted into by way of controlling single holding wire and simulating serial sequential by software, and
It is that tune-up data is transferred on FPGA debugging conversion equipments, the form conversion chip of conversion equipment is debugged to debugging number by FPGA
It is converted to serial signal formatted data and is sent to target FPGA device to be debugged according to process is carried out.This just takes full advantage of simultaneously
The bandwidth of row bus, improves the data transmission bauds between debugging main frame and FPGA debugging conversion equipments, better meets
FPGA debugs demand.
Description of the drawings
Fig. 1 is the FPGA debugging conversion system structure schematic diagrams that the embodiment of the present invention one is provided；
Fig. 2 is a kind of instruction processing unit structural representation that the embodiment of the present invention one is provided；
Fig. 3 is another instruction processing unit structural representation that the embodiment of the present invention one is provided；
Fig. 4 is a kind of FPGA debugging conversion equipment structure chart that the embodiment of the present invention one is provided；
Fig. 5 is the instruction format schematic diagram that the embodiment of the present invention one is provided；
Fig. 6 is a kind of FPGA debugging conversion method schematic flow sheet that the embodiment of the present invention two is provided；
Fig. 7 is that a kind of handling process to the first debugging instruction and corresponding data that the embodiment of the present invention two is provided is illustrated
Figure；
Fig. 8 is a kind of handling process schematic diagram to the second debugging instruction that the embodiment of the present invention two is provided；
Fig. 9 is a kind of handling process schematic diagram to the 3rd debugging instruction that the embodiment of the present invention two is provided.
Specific embodiment
Accompanying drawing is combined below by specific embodiment to be described in further detail the present invention.
Embodiment one
Fig. 1 is referred to, Fig. 1 debugs conversion system structure schematic diagram for the FPGA provided in the present embodiment, including FPGA is adjusted
Preliminary operation exchange device 1 and debugging main frame 2, wherein：
FPGA debugging conversion equipments 1 include form conversion chip 11, and form conversion chip 11 includes：Parallel interface 111, refer to
Make processor 112, and serial line interface 113.Wherein, parallel interface 111 is connected with debugging main frame 2 by parallel bus；And go here and there
Line interface 113 can be connected with target FPGA device to be debugged by universal serial bus, so as to debugging converting system and treat in FPGA
Communication connection is set up between debugging target FPGA device, FPGA debugging is carried out.It should be appreciated that the form in the present embodiment
Conversion chip 11 can adopt fpga chip.
Instruction processing unit 112 is used to receive the first debugging instruction that debugging main frame 2 is sent by parallel interface 111, and obtains
Take the corresponding tune-up data of the first debugging instruction；And for tune-up data is converted into serial signal formatted data by serial
Interface 113 is handed down to target FPGA device to be debugged.
Specifically, referring to Fig. 2, instruction processing unit 112 also include parallel bus controller 1121, instruction parser 1122,
Series bus controller 1123 and data buffer 1124.Then debug main frame 2 the first tune is sent to FPGA debugging conversion equipments 1
After examination instruction, parallel bus controller 1121 can receive first debugging instruction transmitted via parallel interface 111, and should
First debugging instruction is handed down to instruction parser 1122.Instruction parser 1122 can be parsed to the first modulation instructions, and to
Debugging main frame 2 sends corresponding instruction resolution response.Debugging main frame 2 after the instruction resolution response for feeding back is received, meeting
Tune-up data is issued to FPGA debugging conversion equipments 1 according to instruction resolution response, now data buffer 1124 can be received and be deposited
Store up the tune-up data.Series bus controller 1123 can read the tune-up data from data buffer 1124, and will read
To tune-up data be converted to corresponding serial signal formatted data, target FPGA to be debugged is handed down to by serial line interface 113
Device.
In the present embodiment, instruction processing unit 112 can (First Input First Output, first enter elder generation according to FIFO
Dequeue) execution method process to debugging each first modulation instructions that issue of main frame 2.For example, FPGA debugging conversion sets
Standby 1 is subsequently received the first modulation instructions A, the first modulation instructions B and the first modulation instructions C that debugging main frame 2 is issued, then instruction solution
Parser 1122 is carried out parsing Parallel debugging main frame 2 to the first modulation instructions A first and sends A instruction resolution responses, hereafter just can be according to
It is secondary that first modulation instructions B and the first modulation instructions C are carried out parsing Parallel debugging main frame 2 transmission B instruction resolution responses and C successively
Instruction resolution response.Hereafter data buffer 1124 can receive successively and store debugging 2 order of main frame send with first adjust
System instruction corresponding tune-up data A, tune-up data B and tune-up data C, and by series bus controller 1123 from data buffer
Sequentially extract in 1124 and be sent to target FPGA device to be debugged successively.
It should be appreciated that being each device of instruction processing unit 112 in above-mentioned example respectively according to the execution side of FIFO
Method performs its function, in fact, each device can also be located after first modulation instructions are disposed completely again
Next first modulation instructions are managed, for example, instruction parser 1122 carries out parsing Parallel debugging master to the first modulation instructions A first
Machine 2 sends A instruction resolution responses, extracts corresponding tune-up data in series bus controller 1123 from data buffer 1124
A after being sent to target FPGA device to be debugged, instruction parser 1122 just the first modulation instructions B can be parsed and to
Debugging main frame 2 sends B instruction resolution responses, in the same manner, extracts right in series bus controller 1123 from data buffer 1124
The tune-up data B that answers after being sent to target FPGA device to be debugged, instruction parser 1122 just can be to the first modulation instructions C
Carry out parsing 2 transmission C instruction resolution responses of Parallel debugging main frame.Specifically, in series bus controller 1123 from data buffer storage
After corresponding tune-up data is extracted in device 1124 and being sent to target FPGA device to be debugged, the information that can be sent completely is informed
Instruction parser 1122 this first modulation instructions are disposed completely.
In the present embodiment, debugging main frame 2 can be to send the second modulation instructions to FPGA debugging conversion equipments 1, and second adjusts
Instruction processed can obtain service data from target FPGA device to be debugged with control format conversion chip 11 and feed back to debugging master
Machine 2.
Specifically, debug main frame 2 the second modulation instructions, parallel bus controller are sent to FPGA debugging conversion equipments 1
1121 receive second modulation instructions transmitted via parallel interface 111, and are handed down to instruction parser 1122；Instruction parser
After 1122 receive second debugging instruction, second debugging instruction will be parsed, the instruction of the data acquisition that obtains and under
Issue series bus controller 1123；The data acquisition for receiving instruction can be converted into serial signal by series bus controller 1123
The serial line interface 113 of target FPGA device connection to be debugged is handed down to after form, then mesh to be debugged is informed via serial line interface 113
Mark FPGA device needs which service data fed back, and now target FPGA device to be debugged can pass through according to the data acquisition instruction
Universal serial bus back-to-back running data, these service datas are slow via being stored in data after the reception of series bus controller 1123
In storage 1124；Hereafter parallel bus controller 1121 can extract required service data from data buffer 1124 and turn
Change parallel signal form into and debugging main frame 2 is sent to by parallel interface 111.
It should be appreciated that series bus controller 1123 receives service data and is stored in data buffer storage in the present embodiment
In device 1124, can be specifically series bus controller 1123 according to the clock frequency in universal serial bus, according to the rising of clock
Data are got by edge or trailing edge, preserve into data buffer 1124.It is to be further understood that data buffer 1124 can be with
Including reading data buffer and to write data buffer two, specifically, can debugging main frame 2 issue data and be stored in and write data
In buffer, so that FPGA debugging conversion equipments 1 write corresponding tune-up data in target FPGA device to be debugged；Can be by
The data write that target FPGA device to be debugged sends is read in data buffer, reads for debugging main frame 2.
In the present embodiment, FPGA debugs conversion equipment 1 and is receiving the first debugging instruction and the second tune that debugging main frame 2 is issued
Before examination instruction, the 3rd modulation instructions can also be received, it is right that the 3rd modulation instructions can be realized with control format conversion chip 11
FPGA debugs the configuration of conversion equipment 1.
Specifically, parallel interface 111 can receive debugging before the first debugging instruction and the second debugging instruction is received
The 3rd modulation instructions that main frame 2 is issued, and the debugging instruction is sent to into parallel bus controller 1121, then via parallel bus
Controller 1121 is handed down to instruction parser 1122；Instruction parser 1122 can be parsed to the 3rd modulation instructions, so as to
Project to be configured and configuration data are obtained, and configuration project are treated further according to configuration data and are configured.It should be noted that this
Treat configuration project to carry out configuration be completed by instruction parser 1122 according to configuration data in embodiment, it is also possible to
It is to be completed by other devices.
Specifically, in the present embodiment, universal serial bus includes JTAG (Joint Test Action Group, joint test work
Make group) and two buses of SPI (Serial Peripheral Interface, Serial Peripheral Interface (SPI)), serial line interface 113 also wraps
JTAG and SPI dual serial interfaces are included, series bus controller 1123 includes JTAG and SPI dual serial bus control units.Its
In, JTAG serial line interfaces are corresponding with jtag bus, and jtag bus are corresponding with JTAG series bus controllers；SPI serial line interfaces with
Spi bus correspondence, spi bus are corresponding with SPI series bus controllers.
Now, universal serial bus type indication information should be included in the 3rd debugging instruction, instruction parser 1122 can be with
One is selected according to the bus type configured information from JTAG and SPI dual serial bus control units and enter line activating.Should manage
Solution, in the present embodiment, the setting of dual serial bus control unit is separate and mutual exclusion, i.e., in instruction parser
After 1122 one series bus controller of activation, another series bus controller cannot work.A serial is activated
After bus control unit, only its corresponding one group of universal serial bus and serial line interface can work, and another series bus controller
Corresponding one group of universal serial bus and serial line interface no longer work.For example, instruction parser 1122 is according to bus type configured information
JTAG series bus controllers are have activated, now FPGA debugging conversion equipment 1 passes through JTAG serial line interfaces and JTAG serials are total
Line is connected with target FPGA device to be debugged, and the information such as tune-up data or data acquisition instruction is via JTAG series bus controllers
Be converted to JTAG serial signal forms and be sent to target FPGA device to be debugged, and it is corresponding be SPI serial line interfaces, SPI
Bus and SPI series bus controllers do not work.
In the present embodiment, tune-up data is converted to JTAG serial signal forms by activation JTAG series bus controllers, can
To realize configuration and debugging to target FPGA device to be debugged；Tune-up data is converted to by activation SPI series bus controllers
SPI serial signal forms, can configure to the FLASH (flash memory) of target FPGA device to be debugged, realize target to be debugged
Automatically the function of loading after electricity on FPGA device.
In the present embodiment, parallel interface 111 can (Standard Parallel Port, standard parallel connect including SPP
Mouthful) and two kinds of ECP (Extended Capabilities Port, expanded function parallel interface), SPP and ECP can share one
Individual parallel bus, now should include parallel interface type configured information in the 3rd debugging instruction, instruction parser 1122 exists
Interface type configured information is obtained after parsing to the 3rd modulation instructions, and the interface type configured information is sent to parallel total
Lane controller 1121, parallel bus controller 1121 from SPP and ECP select one further according to interface type configured information and open
With.So due to being carried out data transmission by SPP, speed is carried out data transmission by ECP up to 65KB/s, and speed even more may be used
To reach 200KB/s, compare prior art and the side that single holding wire simulates serial sequential is controlled by software on debugging main frame
Formula is then forwarded to FPGA debugging conversion equipments after tune-up data is converted into serial signal form for, main frame and FPGA are debugged
Data transmission bauds between debugging conversion equipment can at least lift 8 times.
It should be appreciated that as SPP is universal parallel interface, its compatibility is good, as long as debugging main frame 2 is supported to connect parallel
Mouth can be used, therefore parallel bus controller 1121 can enable SPP after electricity on FPGA debugging conversion equipments 1
It is operated, makes to first pass through SPP mode and communicated between debugging main frame 2 and FPGA debugging conversion equipments 1.This post debugging main frame
To itself, whether 2 can support that ecp mode is detected, if supporting, then can issue to FPGA debugging conversion equipments 1 and include
Interface type switches to the 3rd modulation instructions of ECP, then parallel bus controller 1121 can be incited somebody to action by a series of Handshake Protocols
Interface switches to ECP by SPP, makes to be communicated by ECP between debugging main frame 2 and FPGA debugging conversion equipments 1；If not propping up
Hold, then the 3rd modulation instructions comprising parallel interface type configured information can not be issued (i.e. simultaneously to FPGA debugging conversion equipments 1
Line interface type indication information is sky), or can issue comprising the 3rd tune for being continuing with SPP to FPGA debugging conversion equipments 1
System instruction, then parallel bus controller 1121 does not control the switching between parallel interface.It should be appreciated that in debugging main frame 2
Support ecp mode when, debugging main frame 2 can also by issue the 3rd modulation instructions comprising parallel interface type configured information come
Control FPGA debugging conversion equipments 1 switch between SPP and ECP.
In the present embodiment, instruction processing unit 112 can also include command register 1125, referring to Fig. 3, command register
1125 can be used for preserving the various debugging instructions that debugging main frame 2 debugs the transmission of conversion equipment 1 to FPGA, and in command register
After 1125 preserve debugging instruction, instruction parser 1122 can obtain corresponding debugging instruction from command register 1125 and carry out
Parsing, and operated accordingly.
In the present embodiment, referring to Fig. 4, FPGA debugging conversion equipments 1 can also include 12 He of the first level translation buffer
Second electrical level translation buffer 13, wherein：First level translation buffer 12 is for will the debugging each debugging instruction that sends of main frame 2
And the level conversion of tune-up data is the operation level that FPGA debugs conversion equipment 1, and for FPGA is debugged conversion equipment 1
The level conversion of the service data of the target FPGA device to be debugged of feedback is to debug the operation level of main frame 2；Second electrical level turns
Buffer 13 is changed for FPGA debugging conversion equipments 1 to be handed down to the serial signal formatted data of target FPGA device to be debugged
Level conversion is the operation level of target FPGA device to be debugged, and the operation for target FPGA device to be debugged is sent
The level conversion of data is the operation level that FPGA debugs conversion equipment 1.
In the present embodiment, FPGA debugging conversion equipment 1 can also include connecting line and winding displacement, wherein, connecting line can be with
For FPGA debugging conversion equipments 1 are connected with debugging main frame 2, specifically, connecting line can be buffered by the first level conversion
Form conversion chip 11 and debugging main frame 2 are connected by device 12 and parallel bus；Winding displacement can be used for for FPGA debugging conversion equipment 1
It is connected with target FPGA device to be debugged, specifically, winding displacement can pass through second electrical level translation buffer 13 and universal serial bus will
Form conversion chip 11 and target FPGA device to be debugged connection.
In the present embodiment, connecting line can adopt DB25 connecting lines, and level translation buffer can be slow using 74HC244
Rush device to realize level conversion function, it should be appreciated that connecting line and level translation buffer specifically can be with from device
Selected according to equipment actual requirement.
In the present embodiment, the debugging instruction that debugging main frame 2 is issued can at least be one of following five kinds of instruction formats, referring to
Fig. 5, only can issue debugging instruction with " Command " form of first row, and what now debugging main frame 2 was issued is only that debugging refers to
Order, the post debugging main frame 2 of 1122 parsing of instruction parser will not issue corresponding data again, FPGA debugging conversion equipments 1 according only to
The debugging instruction that debugging main frame 2 is issued is operated, for example, debug the situation that main frame 2 issues the 3rd debugging instruction；Debugging main frame 2
The form that can also be constituted with " Command " of second row+" Wdata " or " Command "+" Wlen "+" Wdata " of the 3rd row
The form of composition issues debugging instruction, after the debugging instruction parsing that 1122 pairs of debugging main frames 2 of instruction parser are issued, debugging master
Machine 2 can issue the tune-up data corresponding with debugging instruction before, and now FPGA debugging conversion equipment 1 will be with regular length or non-
Regular length preserves tune-up data into data buffer 1124, for example, debug the situation that main frame 2 issues the first debugging instruction；
Debugging main frame 2 can with " Command " of the form that constituted with " Command " of the 4th row+" Rdata " or the 5th row+
The form that " Rlen "+" Rdata " is constituted issues debugging instruction, the debugging instruction that 1122 pairs of debugging main frames 2 of instruction parser are issued
After parsing, the service data for extracting the service data or on-fixed length of the target FPGA device to be debugged of regular length sends
Give debugging main frame 2, such as the second debugging instruction.
It should be noted that the debugging instruction that debugging main frame 2 is issued in the present embodiment can also be to universal serial bus clock frequency
Rate is modified, for example, debug main frame 2 and can issue the 3rd debugging instruction comprising universal serial bus clock frequency modification information, go here and there
Row bus change the serial sequential of itself further according to universal serial bus clock frequency modification information.
It should be noted that can be according to FIFO's for all debugging instructions that debugging main frame 2 is issued in the present embodiment
Execution method is processed.For example, FPGA debugging conversion equipment is subsequently received the first modulation instructions A, that debugging main frame issues
Two modulation instructions B and the 3rd modulation instructions C, then instruction processing unit 112 successively to the first modulation instructions A, the second modulation instructions B and
3rd modulation instructions C process.
FPGA debugging conversion equipments and system that the present embodiment is provided, FPGA debugging conversion equipments include form conversion core
Piece, form conversion chip include parallel interface, serial line interface and instruction processing unit.Wherein, parallel interface is by parallel total
Line is connected with debugging main frame；Serial line interface is connected with target FPGA device to be debugged by universal serial bus；Instruction processing unit is received
The first debugging instruction that debugging main frame is sent by parallel interface, and the corresponding tune-up data of the first debugging instruction is obtained, will adjust
Examination data conversion is handed down to be debugged target FPGA device by serial line interface into serial signal format data.So no longer be
Serial letter tune-up data being converted into by software through the mode for controlling single holding wire simulation serial sequential on debugging main frame
Number formatted data, but tune-up data is transferred on FPGA debugging conversion equipments, the form for debugging conversion equipment by FPGA turns
Change chip process is carried out to tune-up data and be converted to serial signal formatted data and be sent to target FPGA device to be debugged.Should
When being understood by, the transmission speed carried out data transmission by universal serial bus is very big, can meet the debugging need to FPGA completely
Ask, and the transmission of tune-up data is carried out by way of parallel interface, the bandwidth of parallel bus can be made full use of, thus carried
High data transmission bauds between debugging main frame and FPGA debugging conversion equipments, preferably meets FPGA debugging demands.
Embodiment two
Referring to a kind of FPGA debugging conversion method schematic flow sheet that Fig. 6, Fig. 6 are provided for the present embodiment, wrap in this method
FPGA debugging conversion equipments are included, FPGA debugging conversion equipments include form conversion chip, FPGA debugging conversion method flow process bags
Include：
S601:The parallel interface of form conversion chip is connected with debugging main frame by parallel bus；
S602:The serial line interface of form conversion chip is connected with target FPGA device to be debugged by universal serial bus；
So just establish between debugging main frame, FPGA debugging conversion equipments and target FPGA device to be debugged
Communication connection.
S603:The first debugging instruction that debugging main frame is sent by the parallel interface is received, and obtains the first debugging and referred to
Make corresponding tune-up data；
S604:Tune-up data is converted into into serial signal formatted data and target to be debugged is handed down to by serial line interface
FPGA device.
It should be noted that the form conversion chip 11 in the present embodiment can be fpga chip.
In the present embodiment, step S603 receives the first debugging instruction that debugging main frame is sent by parallel interface, and obtains
The corresponding tune-up data of first debugging instruction includes, referring to Fig. 7：
S701:Reception is parsed from the first modulation instructions of parallel interface, and Parallel debugging main frame sends instruction parsing
Response；
S702:Debugging main frame is received according to the tune-up data for instructing resolution response to issue and is preserved.
In the present embodiment, can be according to the execution of FIFO (First Input First Output, First Input First Output)
Method is processed to debugging each first modulation instructions that main frame is issued, i.e., after being disposed to previous first modulation instructions
Next first modulation instructions are being processed.
In the present embodiment, debugging main frame can be to send the second modulation instructions to FPGA debugging conversion equipments, and second modulates
Instruction can obtain service data from target FPGA device to be debugged with control format conversion chip and feed back to debugging main frame, have
Body flow process referring to Fig. 8, including：
S801：Reception is parsed from the second modulation instructions of parallel interface, obtains data acquisition instruction；
S802:It is handed down to what is be connected with target FPGA device to be debugged after changing data acquisition instruction into serial signal form
Serial line interface；
S803:Receive target FPGA device to be debugged and the service data fed back by universal serial bus is instructed according to data acquisition
And preserve；
S804:Extract service data and be converted into parallel signal form and debugging main frame is sent to by parallel interface.
It should be appreciated that step S803 receives target FPGA device to be debugged according to data acquisition instruction in the present embodiment
By the service data preservation of universal serial bus feedback can be specifically：According to the clock frequency in universal serial bus, according to clock
Rising edge or trailing edge the service data for receiving is got, preserve into the data buffer of form conversion chip.Should also
When being understood by, data buffer can include reading data buffer and write data buffer two, specifically, will can debug
Main frame issues data and is stored in be write in data buffer, waits to adjust so that corresponding tune-up data is write by FPGA debugging conversion equipments
In examination target FPGA device；The data write that target FPGA device to be debugged can be sent is read in data buffer, for adjusting
Examination main frame reads.
In the present embodiment, FPGA debugs conversion equipment and is receiving the first debugging instruction and the second debugging that debugging main frame is issued
Before instruction, the 3rd modulation instructions can also be received, the 3rd modulation instructions can be realized adjusting FPGA with control format conversion chip
The configuration of preliminary operation exchange device, idiographic flow referring to Fig. 9, including：
S901:Reception is parsed from the 3rd debugging instruction of parallel interface, obtains project to be configured and configuration number
According to；
S902:Configuration project is treated according to configuration data to be configured.
Specifically, in the present embodiment, form conversion chip also includes series bus controller, while universal serial bus can be wrapped
Include two buses of JTAG and SPI, serial line interface can include JTAG and SPI dual serial interfaces, series bus controller can be with
Including JTAG and SPI dual serial bus control units.Wherein, JTAG serial line interfaces are corresponding with jtag bus, jtag bus with
JTAG series bus controllers correspondence；SPI serial line interfaces are corresponding with spi bus, spi bus and SPI series bus controllers pair
Should.
Now, carrying out configuration to universal serial bus, serial line interface and series bus controller according to step S902 includes：It is right
3rd debugging instruction carries out parsing and obtains universal serial bus type indication information (i.e. configuration data), according to bus type configured information
One is selected from JTAG and SPI dual serial bus control units and enters line activating, then activate a bus control unit controls which
Corresponding universal serial bus, serial line interface are operated, so as to realize to universal serial bus, serial line interface and series bus controller
Configuration.
It should be appreciated that in the present embodiment, the setting of JTAG and SPI dual serial bus control units is separate
And mutual exclusion, i.e., after a series bus controller is activated, another series bus controller cannot work.Activate
After one series bus controller, only its corresponding one group of universal serial bus and serial line interface can work, and another serial is total
The corresponding one group of universal serial bus of lane controller and serial line interface no longer work.
In the present embodiment, tune-up data can be converted to JTAG serial signal lattice by activation JTAG series bus controllers
Formula, it is possible to achieve the configuration and debugging to target FPGA device to be debugged；Activation SPI series bus controllers can will debug number
According to SPI serial signal forms are converted to, the FLASH (flash memory) of target FPGA device to be debugged can be configured, realize treating
Automatically the function of loading after electricity on debugging target FPGA device.
Specifically, in the present embodiment, parallel interface can include SPP and two kinds of ECP, now, according to step S902 to simultaneously
Line interface carries out configuration to be included：Parsing is carried out to the 3rd debugging instruction and obtains interface type configured information (i.e. configuration data), root
One enabled according to interface type configured information in SPP and ECP is operated, and another does not work.
More specifically, as SPP is universal parallel interface, its compatibility is good, as long as debugging main frame just supports parallel interface
Conversion equipment can be debugged by SPP and FPGA and set up communication connection, ECP is expanded function parallel interface, its compliance
It is higher, need debugging main frame to have corresponding hardware supported, but its data transmission bauds is faster.Therefore debugging main frame is adjusted with FPGA
SPP can be first passed through to be communicated between preliminary operation exchange device, to itself, whether this post debugging main frame can support that ecp mode is carried out
Detection, if supporting, then can issue the 3rd modulation instructions to FPGA debugging conversion equipments, then FPGA debugging conversion equipment root
Interface is switched to into ECP by SPP by a series of Handshake Protocols according to the configuration data in the 3rd modulation instructions, make debugging main frame with
Communicated by ECP between FPGA debugging conversion equipments；If not supporting, can not give out a contract for a project under FPGA debugging conversion equipments
The 3rd modulation instructions containing parallel interface type configured information (i.e. parallel interface type configured information is sky), or can be to FPGA
Debugging conversion equipment is issued comprising the 3rd modulation instructions for being continuing with SPP information.It should be appreciated that supporting in debugging main frame
During ecp mode, debugging main frame can also be controlled by issuing the 3rd modulation instructions comprising parallel interface type configured information
FPGA debugging conversion equipments switch between SPP and ECP.
In the present embodiment, debugging main frame and FPGA debugging conversion equipments are carried out data transmission by SPP, and speed is reachable
65KB/s, is carried out data transmission by ECP, and speed more can be to reach 200KB/s, is compared prior art and is led on debugging main frame
Cross software control single holding wire simulation serial sequential mode tune-up data is converted into into serial signal form after retransmit
For to FPGA debugging conversion equipments, the data transmission bauds debugged between main frame and FPGA debugging conversion equipments can at least be carried
Rise 8 times.
In the present embodiment, the 3rd debugging instruction that debugging main frame is issued can also include universal serial bus clock frequency modification letter
Breath, after parsing being carried out to the 3rd debugging instruction and obtains universal serial bus clock frequency modification information, universal serial bus is according to the string
Row bus clock frequency modification information changes the serial sequential of itself.
In the present embodiment, debugging main frame can also issue status inquiry instruction, FPGA debugging to FPGA debugging conversion equipments
Oneself state can be fed back to debugging main frame after receiving the instruction by conversion equipment.
The FPGA debugging conversion methods that the present embodiment is provided, by by the form conversion chip of FPGA debugging conversion equipments
Parallel interface be connected with debugging main frame by parallel bus, serial line interface is by universal serial bus and target FPGA device to be debugged
Connection, realizes FPGA debugging conversion equipments and the communication between debugging main frame and target FPGA device to be debugged, FPGA debugging
Conversion equipment receives the first debugging instruction that debugging main frame is sent by parallel interface again, and it is corresponding to obtain the first debugging instruction
Tune-up data, then tune-up data is converted into into serial signal formatted data, target FPGA to be debugged is handed down to by serial line interface
Device.So no longer it is on debugging main frame will to debug number by software through the mode for controlling single holding wire simulation serial sequential
According to the serial signal formatted data being converted into, but tune-up data is transferred on FPGA debugging conversion equipments, is debugged by FPGA
The form conversion chip of conversion equipment carries out process and is converted to serial signal formatted data and is sent to waiting to adjust to tune-up data
Examination target FPGA device.It should be appreciated that the transmission speed carried out data transmission by universal serial bus is very big, can expire completely
Debugging demand of the foot to FPGA, and the transmission of tune-up data is carried out by way of parallel interface, can make full use of parallel total
The bandwidth of line, which improves the data transmission bauds between debugging main frame and FPGA debugging conversion equipments, preferably meets
Debugging demand to FPGA.
Above content is with reference to specific embodiment further description made for the present invention, it is impossible to assert this
It is bright to be embodied as being confined to these explanations.For general technical staff of the technical field of the invention, do not taking off
On the premise of present inventive concept, some simple deduction or replace can also be made, should all be considered as belonging to the protection of the present invention
Scope.
Claims (10)
1. a kind of FPGA debugs conversion equipment, including form conversion chip, and the form conversion chip is included by parallel bus
The parallel interface being connected with debugging main frame, the serial line interface being connected with target FPGA device to be debugged by universal serial bus, and
Instruction processing unit；
The instruction processing unit is used to receive the first debugging instruction that the debugging main frame is sent by the parallel interface, and obtains
Take the corresponding tune-up data of first debugging instruction；And for the tune-up data is converted into serial signal formatted data
The target FPGA device to be debugged is handed down to by the serial line interface.
2. FPGA as claimed in claim 1 debugs conversion equipment, it is characterised in that the instruction processing unit includes parallel bus
Controller, instruction parser, series bus controller and data buffer；
The parallel bus controller is used for the first modulation instructions received from the parallel interface and is handed down to the instruction
Resolver；
The instruction parser is parsed for parsing to first modulation instructions and sending instruction to the debugging main frame
Response；
The data buffer is used to receiving and preserving the debugging number that the debugging main frame is issued according to the instruction resolution response
According to；
The series bus controller is for reading the tune-up data and be converted to corresponding string from the data buffer
The target FPGA device to be debugged is handed down to by the serial line interface after row signal format data.
3. FPGA as claimed in claim 2 debugs conversion equipment, it is characterised in that
The parallel bus controller is additionally operable to the second modulation instructions received from the parallel interface and is handed down to the finger
Make resolver；And pass through for corresponding service data is extracted from the data buffer and parallel signal form is converted into
The parallel interface is sent to the debugging main frame；
The instruction parser is additionally operable to receive second debugging instruction from the debugging main frame by the parallel interface, and will be right
Second debugging instruction carries out parsing the data acquisition instruction for obtaining and is handed down to the series bus controller；
The series bus controller is handed down to described after being additionally operable to for data acquisition instruction to be converted into serial signal form
The serial line interface of target FPGA device to be debugged connection, and receive the target FPGA device to be debugged and obtained according to the data
The service data that instruction fetch is fed back by the universal serial bus, and the service data is stored in the data buffer.
4. FPGA as claimed in claim 3 debugs conversion equipment, it is characterised in that the parallel bus controller is additionally operable to
Before receiving first debugging instruction and the second debugging instruction, receive from the parallel interface the 3rd debugging instruction and under
Issue the instruction parser；
The instruction parser is additionally operable to parse the 3rd modulation instructions, obtains project to be configured and configuration number
According to；The project to be configured is configured according to the configuration data.
5. FPGA as claimed in claim 4 debugs conversion equipment, it is characterised in that the universal serial bus include jtag bus and
Spi bus, the serial line interface include JTAG serial line interfaces and SPI serial line interfaces, and the series bus controller includes JTAG
Series bus controller and SPI series bus controllers；
3rd debugging instruction includes universal serial bus type indication information；
The instruction parser is for going here and there from the JTAG series bus controllers and SPI according to the bus type configured information
One is selected in row bus controller and enters line activating.
6. FPGA as claimed in claim 4 debugs conversion equipment, it is characterised in that the parallel interface includes that standard parallel connects
Mouth and expanded function parallel interface；3rd debugging instruction includes parallel interface type configured information；
The instruction parser is additionally operable to carry out parsing to the 3rd modulation instructions obtain the interface type configured information, and
It is sent to the parallel bus controller；
The parallel bus controller is for enabling the standard parallel interface and extension according to the interface type configured information
One in function parallelization interface.
7. FPGA as claimed in claim 6 debugs conversion equipment, it is characterised in that the parallel bus controller is additionally operable to
Received before the 3rd debugging instruction of the debugging main frame, after electricity on FPGA debugging conversion equipments, enable
The standard parallel interface.
8. FPGA debugging conversion equipments as described in claim 1-7, it is characterised in that also including the first level buffer device and the
Two level buffer devices；
The first level buffer device for by it is described debugging main frame send each debugging instruction and tune-up data level conversion
The operation level of conversion equipment is debugged for the FPGA, and for the FPGA to be debugged the electricity of the data of conversion equipment feedback
Flat turn is changed to the operation level of the debugging main frame；
The second electrical level buffer is handed down to the target FPGA device to be debugged for the FPGA is debugged conversion equipment
Serial signal formatted data level conversion be the target FPGA device to be debugged operation level, and for will be described
The level conversion of the service data that target FPGA device to be debugged sends is the operation level that the FPGA debugs conversion equipment.
9. a kind of FPGA debugs converting system, including：Debugging main frame and the debugging of the FPGA as described in any one of claim 1-7
Conversion equipment；
The debugging main frame be connected by the parallel interface that parallel bus and the FPGA debug conversion equipment, and to it is described parallel
Interface issues the first debugging instruction and tune-up data corresponding with first debugging instruction；
The instruction processing unit of FPGA debugging conversion equipment receive the debugging main frame issue the first debugging instruction and with institute
The corresponding tune-up data of the first debugging instruction is stated, and the tune-up data is converted into into serial signal formatted data by described
The serial line interface of FPGA debugging conversion equipments is handed down to target FPGA device to be debugged.
10. a kind of FPGA debugs conversion method, it is characterised in that the FPGA debugging being applied to as described in any one of claim 1-7
On conversion equipment, including：
The parallel interface that the FPGA debugs conversion equipment is connected with debugging main frame by parallel bus, and the FPGA is adjusted
The serial line interface of preliminary operation exchange device is connected with target FPGA device to be debugged by universal serial bus；
The FPGA debugging conversion equipment receives the first debugging instruction that the debugging main frame is sent by the parallel interface, and
Obtain the corresponding tune-up data of first debugging instruction；
The tune-up data is converted into serial signal formatted data and by the serial interface by the FPGA debugging conversion equipment
Mouth is handed down to the target FPGA device to be debugged.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611109445.9A CN106527402A (en) | 2016-12-02 | 2016-12-02 | FPGA debugging conversion equipment, system and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611109445.9A CN106527402A (en) | 2016-12-02 | 2016-12-02 | FPGA debugging conversion equipment, system and method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106527402A true CN106527402A (en) | 2017-03-22 |
Family
ID=58341371
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611109445.9A Pending CN106527402A (en) | 2016-12-02 | 2016-12-02 | FPGA debugging conversion equipment, system and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106527402A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108989730A (en) * | 2018-08-08 | 2018-12-11 | 京东方科技集团股份有限公司 | Video format conversion method and its device, field programmable gate array |
| CN109669729A (en) * | 2018-12-26 | 2019-04-23 | 杭州迪普科技股份有限公司 | A kind of starting bootstrap technique of processor |
| CN111858205A (en) * | 2020-06-30 | 2020-10-30 | 浪潮(北京)电子信息产业有限公司 | Chip debugging method and system |
| CN112685248A (en) * | 2020-12-24 | 2021-04-20 | 北京浪潮数据技术有限公司 | Intelligent network card monitoring log obtaining method and device, electronic equipment and storage medium |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0733976A1 (en) * | 1995-03-23 | 1996-09-25 | Canon Kabushiki Kaisha | Chip select signal generator |
| US7043568B1 (en) * | 1998-11-12 | 2006-05-09 | Klingman Edwin E | Configuration selection for USB device controller |
| CN201075248Y (en) * | 2007-08-27 | 2008-06-18 | 中国石油天然气集团公司 | USB interface real-time data acquisition controller |
| CN102968364A (en) * | 2012-11-16 | 2013-03-13 | 中国航天科技集团公司第九研究院第七七一研究所 | Universal debugging interface-based SoC (System on Chip) hardware debugger |
| CN103605629A (en) * | 2013-10-30 | 2014-02-26 | 上海交通大学 | Multi-target multi-CPU (central processing unit) high-reliability processing device for mine hoist |
| CN105550119A (en) * | 2016-01-29 | 2016-05-04 | 中国人民解放军国防科学技术大学 | Simulation device based on JTAG protocol |
| CN105808396A (en) * | 2016-03-04 | 2016-07-27 | 浙江大华技术股份有限公司 | Chip debugging device, debugging method and SOC (System of Chip) chip system |
-
2016
- 2016-12-02 CN CN201611109445.9A patent/CN106527402A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0733976A1 (en) * | 1995-03-23 | 1996-09-25 | Canon Kabushiki Kaisha | Chip select signal generator |
| US7043568B1 (en) * | 1998-11-12 | 2006-05-09 | Klingman Edwin E | Configuration selection for USB device controller |
| CN201075248Y (en) * | 2007-08-27 | 2008-06-18 | 中国石油天然气集团公司 | USB interface real-time data acquisition controller |
| CN102968364A (en) * | 2012-11-16 | 2013-03-13 | 中国航天科技集团公司第九研究院第七七一研究所 | Universal debugging interface-based SoC (System on Chip) hardware debugger |
| CN103605629A (en) * | 2013-10-30 | 2014-02-26 | 上海交通大学 | Multi-target multi-CPU (central processing unit) high-reliability processing device for mine hoist |
| CN105550119A (en) * | 2016-01-29 | 2016-05-04 | 中国人民解放军国防科学技术大学 | Simulation device based on JTAG protocol |
| CN105808396A (en) * | 2016-03-04 | 2016-07-27 | 浙江大华技术股份有限公司 | Chip debugging device, debugging method and SOC (System of Chip) chip system |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108989730A (en) * | 2018-08-08 | 2018-12-11 | 京东方科技集团股份有限公司 | Video format conversion method and its device, field programmable gate array |
| CN108989730B (en) * | 2018-08-08 | 2021-01-22 | 京东方科技集团股份有限公司 | Video format conversion method and device and field programmable gate array |
| CN109669729A (en) * | 2018-12-26 | 2019-04-23 | 杭州迪普科技股份有限公司 | A kind of starting bootstrap technique of processor |
| CN111858205A (en) * | 2020-06-30 | 2020-10-30 | 浪潮(北京)电子信息产业有限公司 | Chip debugging method and system |
| CN111858205B (en) * | 2020-06-30 | 2022-07-08 | 浪潮(北京)电子信息产业有限公司 | Chip debugging method and system |
| CN112685248A (en) * | 2020-12-24 | 2021-04-20 | 北京浪潮数据技术有限公司 | Intelligent network card monitoring log obtaining method and device, electronic equipment and storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106527402A (en) | FPGA debugging conversion equipment, system and method | |
| CN105550119B (en) | A kind of simulator based on JTAG protocol | |
| CN106502932B (en) | Method based on interconnecting interface and its write operation and read operation between layered | |
| CN101908289A (en) | Dynamic real-time interactive programming learning system for teaching | |
| CN202261268U (en) | Analog device of transponder information receiving system and testing system thereof | |
| CN104735387A (en) | Method and device for achieving multi-channel MIPI synchronous transmission | |
| CN105808396A (en) | Chip debugging device, debugging method and SOC (System of Chip) chip system | |
| CN102006200A (en) | Debugging processing method, debugging processing system and single board | |
| WO2016184170A1 (en) | Smi interface device debugging apparatus and method, and storage medium | |
| CN105120235A (en) | Industrial image collection system based on USB 3.0 interface, and image collection processing method of industrial image collection system | |
| CN104243083B (en) | A kind of data mapping method, device and electronic equipment | |
| CN103226534A (en) | Isolated type high-speed data acquisition card | |
| CN104378574B (en) | VGA IMAQs and compression storage device based on SoPC | |
| CN109407574A (en) | Output-controlling device and its method may be selected in a kind of multibus | |
| CN108107351A (en) | Adjustment method, debugger and the system of JTAG debuggers | |
| CN104077200A (en) | Individual testing device for CPCI (Compact Peripheral Component Interconnect) module separated from main engine | |
| CN105354166B (en) | Robot and the data transmission method being applicable in | |
| CN104793371B (en) | Error condition detection means and method during a kind of MIPI modules point screen | |
| CN104865717B (en) | Adaptive error handling method in MIPI module screen tests | |
| CN103402115B (en) | System for verifying high-speed image compressing code stream based on system on chip | |
| CN205121274U (en) | Serial ports stipulations message signal testing terminal row | |
| CN107346295A (en) | A kind of data transmission cable and data transmission method | |
| CN208596371U (en) | Multicore JTAG debugging proxy system based on PCIE in conjunction with FPGA | |
| CN107908562A (en) | A kind of method and device of the multimedia resource playing function of test application program | |
| CN205142402U (en) | Industry image acquisition system based on USB3. 0 interface |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170322 |
|
| RJ01 | Rejection of invention patent application after publication |