CN111858205A - Chip debugging method and system - Google Patents
Chip debugging method and system Download PDFInfo
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- CN111858205A CN111858205A CN202010614657.2A CN202010614657A CN111858205A CN 111858205 A CN111858205 A CN 111858205A CN 202010614657 A CN202010614657 A CN 202010614657A CN 111858205 A CN111858205 A CN 111858205A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/06—Clock generators producing several clock signals
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
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Abstract
The application discloses a chip debugging method, which is applied to a chip provided with a main clock and a debugging clock, and comprises the following steps: after receiving a main clock operation instruction, operating the chip based on the main clock, monitoring instant operation data of the chip based on the main clock and storing the instant operation data into a preset storage area; after the main clock stops, storing the instant running data of the currently monitored chip into a storage area based on the debugging clock; when a data export instruction is received, exporting the data in the storage area based on the debugging clock for chip debugging. By the scheme, the instant operation data of the chip is effectively acquired through the double clocks, and the chip debugging is realized. The application also provides a chip debugging system which has corresponding technical effects.
Description
Technical Field
The present invention relates to the field of debug technologies, and in particular, to a method and a system for debugging a chip.
Background
With the development of chips, the structure of the chip is more and more complex, and higher requirements are put forward for hardware debugging work. When debugging hardware, the difficulty is the opacity inside the chip. That is, when a problem occurs, the chip hardware cannot perform single step debugging like software, cannot check the memory condition, and even cannot set a breakpoint to stop the hardware.
The current scheme mainly realizes chip debugging in a Joint Test Action Group (JTAG) manner, which is a technology based on a scan path method. In this way, the state of each flip-flop in the circuit can only be read from the outside of the chip, and whether the flip-flop works normally or not can be observed through a simple scan chain design. The JTAG method has the advantage of simple design, but the amount of data read each time is very small, and no real-time data can be obtained, and during actual debugging, as the chip becomes increasingly complex, real-time running data is often needed to implement debugging.
In summary, how to effectively acquire the real-time running data of the chip to achieve chip debugging is a technical problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide a chip debugging method and a chip debugging system, which are used for effectively acquiring the real-time running data of a chip to realize chip debugging.
In order to solve the technical problems, the invention provides the following technical scheme:
a chip debugging method applied to a chip provided with a master clock and a debugging clock comprises
After a main clock operation instruction is received, operating the chip based on the main clock, monitoring instant operation data of the chip based on the main clock, and storing the instant operation data into a preset storage area;
After the master clock stops, storing the currently monitored instant operation data of the chip into the storage area based on the debugging clock;
when a data export instruction is received, exporting the data in the storage area based on the debugging clock for chip debugging.
Preferably, after the master clock is stopped, storing the currently monitored real-time running data of the chip into the storage area based on the debug clock, including:
and stopping the running of the main clock after receiving a main clock stop instruction, and storing the currently monitored instant running data of the chip into the storage area based on the debugging clock.
Preferably, after the master clock is stopped, storing the currently monitored real-time running data of the chip into the storage area based on the debug clock, including:
and stopping the operation of the main clock when the operation of the chip fails, and storing the currently monitored instant operation data of the chip into the storage area based on the debugging clock.
Preferably, the storage area is a storage area in a board-level off-chip storage device.
Preferably, monitoring and storing the instant operation data of the chip to a preset storage area based on the master clock includes:
monitoring instant operation data of the chip based on the main clock, storing the instant operation data into a preset storage area, and adding attribute information of the data stored into the storage area during storage;
correspondingly, storing the currently monitored real-time running data of the chip into the storage area based on the debug clock comprises:
storing the currently monitored instant operation data of the chip into the storage area based on the debugging clock, and adding the attribute information of the data stored into the storage area during storage.
A chip debugging system is applied to a chip provided with a main clock and a debugging clock, and comprises:
the monitoring module is used for monitoring the instant operation data of the chip based on the master clock and sending the instant operation data to the data recording module when the master clock runs, and sending the instant operation data of the chip monitored currently to the data recording module based on the debugging clock after the master clock stops;
the data recording module is used for storing the instant operation data of the chip sent by the monitoring module into a preset storage area based on the master clock when the master clock runs, and storing the instant operation data of the chip sent by the monitoring module into the preset storage area based on the debugging clock after the master clock stops; when a data export instruction is received, exporting the data in the storage area based on the debugging clock so as to debug a chip;
And the clock switching control module is used for enabling the master clock to run the chip based on the master clock after receiving the master clock running instruction, and enabling the debugging clock after the master clock is stopped.
Preferably, the clock switching control module is specifically configured to:
after receiving a master clock run instruction, enabling the master clock to run the chip based on the master clock,
stopping the operation of the master clock and enabling the debug clock after receiving a master clock stop instruction.
Preferably, the clock switching control module is specifically configured to:
after receiving a master clock running instruction, enabling the master clock to run the chip based on the master clock;
and when the operation of the chip fails, stopping the operation of the main clock and starting the debugging clock.
Preferably, the storage area is a storage area in a board-level off-chip storage device.
Preferably, the data recording module is further configured to:
when the real-time running data of the chip sent by the monitoring module is stored in a preset storage area, adding attribute information of the data stored in the storage area.
The technical scheme provided by the embodiment of the invention is applied to a chip provided with a main clock and a debugging clock, and the breakpoint is realized through double clocks, so that the scheme of the invention can read the instant running data for debugging. Specifically, after a master clock running instruction is received, the chip is run based on the master clock, and the instant running data of the chip is monitored based on the master clock and stored in a preset storage area, that is, each functional module in the chip is enabled to run normally under the master clock. After the main clock stops, each functional module generating the instant operation data in the chip stops working, at the moment, the debugging clock works, namely the instant operation data of the currently monitored chip is stored in the storage area based on the debugging clock, and then when a data export instruction is passed, the data in the storage area is exported based on the debugging clock so as to debug the chip. It can be seen that after the main clock is stopped, the storage and the derivation of the instant running data are realized through the debugging clock, and each functional module generating the instant running data in the chip cannot generate new instant running data because the main clock is stopped, that is, the scheme of the application realizes a breakpoint through the double clocks, that is, the hardware is suspended, so that the single step debugging can be performed. After the instant running data at the breakpoint moment is derived, the main clock is operated again, so that each functional module of the chip can be operated, and the debugging process is continued. In summary, according to the scheme of the application, through the design of the double clocks, the instant operation data of the chip can be effectively acquired, and the chip debugging is realized.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a flowchart illustrating a method for debugging a chip according to the present invention;
fig. 2 is a schematic structural diagram of a chip debug system according to the present invention.
Detailed Description
The core of the invention is to provide a chip debugging method, which can effectively acquire the instant operation data of the chip through the design of double clocks to realize the chip debugging.
In order that those skilled in the art will better understand the disclosure, the invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a flowchart of an implementation of a chip debugging method according to the present invention, where the chip debugging method is applied to a chip with a master clock and a debug clock, and includes the following steps:
step S101: and after receiving the main clock operation instruction, operating the chip based on the main clock, monitoring the instant operation data of the chip based on the main clock and storing the instant operation data into a preset storage area.
Specifically, the chip of the present application is provided with a master clock and a debug clock, and can be switched arbitrarily. In addition, each functional module in the chip may run depending on the master clock, and as for the debug clock, the debug clock only needs to be used to execute the functions of step S102 and step S103 of the present application, that is, only part of the functions in the chip may be used in the debug clock of the present application.
The main clock operation instruction can be input by a worker through a related interface, namely, each functional module of the chip works, and when the chip operates, the instant operation data of the chip can be monitored based on the main clock and stored in a preset storage area. The master clock is the clock that the chip was originally set to.
It should be noted that, the specific content of the real-time operation data of the chip to be monitored in the present application may be set and adjusted according to actual needs. For example, a chip usually has a plurality of functional modules, such as a functional module a, a functional module B, a functional module C, and a functional module D, and it is assumed that there is data interaction between any two functional modules. For example, in one specific embodiment, the real-time operation data of the monitored chip includes data exchanged between any two functional modules, that is, in this example, 6 monitoring nodes may be provided. For another example, in another specific implementation scenario, for a certain type of chip, there are also a function module a, a function module B, a function module C, and a function module D, but when debugging the chip, for example, only attention needs to be paid to interaction data between the function module a and the function module B, and interaction data between the function module B and the function module C, and then 2 monitoring nodes are set in this example.
It can be understood that, since the chip continuously operates, the real-time operation data of the chip is also continuously generated, and therefore, in practical applications, when the step S101 is executed, the real-time operation data of the chip may be monitored according to a set monitoring period, and then stored in a preset storage area.
When the real-time running data of the chip is stored in the storage area, there may be a plurality of data writing manners, for example, after the monitoring period comes, the real-time running data monitored in the current round is written into the storage area, and when the next monitoring period comes, the original data is overwritten with the new real-time running data. For another example, data writing may be performed in a sequential writing manner or a cyclic writing manner. That is, data writing is performed from the start address of the storage area until the space of the storage area is used up, and then overlay data writing is performed again from the start address. The size of the storage area may be set according to actual needs.
Step S102: and after the master clock is stopped, storing the instant running data of the currently monitored chip into a storage area based on the debugging clock.
In order to realize hardware halt, namely single step debugging can be carried out, the scheme of the application stores the instant running data of the currently monitored chip into the storage area based on the debugging clock after the main clock is stopped.
After the main clock is stopped, the current real-time running data of the chip can be monitored by the monitoring module but is not usually written into the storage area, and the main clock is stopped at the moment. When the chip is debugged, the worker often needs the instant operation data at the moment when the main clock stops, so that the instant operation data of the chip at the moment when the main clock stops is stored in the storage area through the debugging clock in the scheme of the application, that is, when the step S102 is executed through the debugging clock, the functional module generating the instant operation data in the chip is in a stop operation state, and the chip does not generate new instant operation data at this time.
In practical applications, the triggering condition for the master clock to stop may be various. For example, in an embodiment of the present invention, step S102 may specifically include:
and stopping the running of the main clock after receiving the main clock stopping instruction, and storing the instant running data of the currently monitored chip into a storage area based on the debugging clock.
In this embodiment, the worker may send a master clock stop instruction to the chip to stop the operation of the master clock, that is, in this embodiment, the worker may actively stop the operation of the master clock according to actual needs. In practical application, a worker can stop the main clock at any required time according to debugging requirements, and further obtain the instant running data of the chip at the time.
In an embodiment of the present invention, step S102 may specifically include:
and stopping the operation of the main clock when the operation of the chip fails, and storing the currently monitored instant operation data of the chip into a storage area based on the debugging clock.
In this embodiment, after the chip normally operates based on the master clock, once the operation of the chip fails, the operation of the master clock can be immediately and automatically stopped, and usually, when the quality of the chip is tested, a worker can acquire the instant operation data of the chip at the time of the occurrence of the failure, so as to perform debugging by using the data.
And it is understood that the trigger condition of the master clock stop described in the above two embodiments may exist at the same time, that is, the operation of the master clock may be stopped after receiving the master clock stop instruction or when the operation of the chip fails. In other embodiments, more trigger conditions for stopping the master clock may be set as needed, and the implementation of the present invention is not affected.
Step S103: when a data export instruction is received, exporting the data in the storage area based on the debugging clock for chip debugging.
Since the real-time running data of the chip monitored after the main clock is stopped is stored in the storage area based on the debug clock, when the data export instruction is passed, the data in the storage area can be exported based on the debug clock to debug the chip.
Moreover, it can be understood that, in practical applications, there may be a case where the master clock needs to be stopped and enabled many times, that is, after step S103 is executed, the master clock may be re-enabled through a master clock running instruction, that is, the operations of steps S101 to S103 may be repeated for several times until a worker obtains instant running data of each required breakpoint, so as to implement chip debugging. The break point described herein is the instant running data generated at a time after the master clock stops.
The storage area described in the present application may be a storage area inside a chip, and in an embodiment of the present invention, the storage area may be set as a storage area in an off-chip storage device on board, which is advantageous for storing a large amount of information, considering that a large amount of information may need to be recorded in some occasions. The specific storage type and model of the off-board storage device can be selected according to actual conditions.
Further, in an embodiment of the present invention, in order to enable a worker to easily know what the content of the data of each portion stored in the storage area is, the step S101 described above of monitoring the real-time running data of the chip based on the master clock and storing the real-time running data into the preset storage area may specifically be:
monitoring instant operation data of a chip based on a main clock, storing the instant operation data into a preset storage region, and adding attribute information of the data stored into the storage region during storage;
correspondingly, the step S102 of storing the currently monitored real-time running data of the chip into the storage area based on the debug clock may specifically be:
And storing the instant operation data of the currently monitored chip into the storage area based on the debugging clock, and adding the attribute information of the data stored into the storage area during storage.
The specific items of the attribute information may also be set and adjusted according to actual situations, for example, for the real-time operation data monitored in any one monitoring period, the specific items may include a timestamp generated by the real-time operation data, a size of the data amount, and respective sources of each part in the real-time operation data, that is, the specific items are used to indicate which functional module each part of the data is generated by. Correspondingly, when the instant running data of the currently monitored chip is stored in the storage area based on the debugging clock, the attribute information of the data can be added.
The technical scheme provided by the embodiment of the invention is applied to a chip provided with a main clock and a debugging clock, and the breakpoint is realized through double clocks, so that the scheme of the invention can read the instant running data for debugging. Specifically, after a master clock running instruction is received, the chip is run based on the master clock, and the instant running data of the chip is monitored based on the master clock and stored in a preset storage area, that is, each functional module in the chip is enabled to run normally under the master clock. After the main clock stops, each functional module generating the instant operation data in the chip stops working, at the moment, the debugging clock works, namely the instant operation data of the currently monitored chip is stored in the storage area based on the debugging clock, and then when a data export instruction is passed, the data in the storage area is exported based on the debugging clock so as to debug the chip. It can be seen that after the main clock is stopped, the storage and the derivation of the instant running data are realized through the debugging clock, and each functional module generating the instant running data in the chip cannot generate new instant running data because the main clock is stopped, that is, the scheme of the application realizes a breakpoint through the double clocks, that is, the hardware is suspended, so that the single step debugging can be performed. After the instant running data at the breakpoint moment is derived, the main clock is operated again, so that each functional module of the chip can be operated, and the debugging process is continued. In summary, according to the scheme of the application, through the design of the double clocks, the instant operation data of the chip can be effectively acquired, and the chip debugging is realized.
Corresponding to the above method embodiments, the embodiments of the present invention further provide a chip debug system, which can be referred to in correspondence with the above.
The chip debugging system is applied to a chip provided with a master clock and a debugging clock, and can refer to fig. 2, and includes:
the monitoring module 201 is used for monitoring the instant operation data of the chip based on the master clock and sending the instant operation data to the data recording module when the master clock runs, and sending the instant operation data of the currently monitored chip to the data recording module based on the debugging clock after the master clock stops;
the data recording module 202 is configured to store, based on the master clock, the instant operation data of the chip sent by the monitoring module into a preset storage region when the master clock is running, and store, based on the debug clock, the instant operation data of the chip sent by the monitoring module into the preset storage region after the master clock is stopped; when a data export instruction is received, exporting data in the storage area based on a debugging clock so as to debug the chip;
and the clock switching control module 203 is used for enabling the master clock to run the chip based on the master clock after receiving the master clock running instruction, and enabling the debugging clock after the master clock is stopped.
In an embodiment of the present invention, the clock switching control module 203 is specifically configured to:
after receiving the master clock running instruction, enabling the master clock to run the chip based on the master clock,
the operation of the master clock is stopped after receiving the master clock stop instruction, and the debug clock is enabled.
In an embodiment of the present invention, the clock switching control module 203 is specifically configured to:
after receiving the master clock running instruction, enabling the master clock to run the chip based on the master clock,
and when the operation of the chip fails, stopping the operation of the main clock and starting the debugging clock.
In one embodiment of the present invention, the storage area is a storage area in a board-level off-chip storage device.
In an embodiment of the present invention, the data recording module 202 is further configured to:
when the instant operation data of the chip sent by the monitoring module is stored in a preset storage area, adding the attribute information of the data stored in the storage area.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The principle and the implementation of the present invention are explained in the present application by using specific examples, and the above description of the embodiments is only used to help understanding the technical solution and the core idea of the present invention. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
Claims (10)
1. A chip debugging method is applied to a chip provided with a main clock and a debugging clock, and comprises the following steps:
After a main clock operation instruction is received, operating the chip based on the main clock, monitoring instant operation data of the chip based on the main clock, and storing the instant operation data into a preset storage area;
after the master clock stops, storing the currently monitored instant operation data of the chip into the storage area based on the debugging clock;
when a data export instruction is received, exporting the data in the storage area based on the debugging clock for chip debugging.
2. The chip debugging method of claim 1, wherein storing the currently monitored real-time running data of the chip into the storage area based on the debugging clock after the master clock is stopped comprises:
and stopping the running of the main clock after receiving a main clock stop instruction, and storing the currently monitored instant running data of the chip into the storage area based on the debugging clock.
3. The chip debugging method of claim 1, wherein storing the currently monitored real-time running data of the chip into the storage area based on the debugging clock after the master clock is stopped comprises:
And stopping the operation of the main clock when the operation of the chip fails, and storing the currently monitored instant operation data of the chip into the storage area based on the debugging clock.
4. The chip debugging method of claim 1, wherein the storage area is a storage area in a board-level off-chip storage device.
5. The chip debugging method of any one of claims 1 to 4, wherein monitoring and storing the instant operation data of the chip into a preset storage area based on the master clock comprises:
monitoring instant operation data of the chip based on the main clock, storing the instant operation data into a preset storage area, and adding attribute information of the data stored into the storage area during storage;
correspondingly, storing the currently monitored real-time running data of the chip into the storage area based on the debug clock comprises:
storing the currently monitored instant operation data of the chip into the storage area based on the debugging clock, and adding the attribute information of the data stored into the storage area during storage.
6. A chip debugging system, which is applied to a chip provided with a master clock and a debugging clock, comprises:
The monitoring module is used for monitoring the instant operation data of the chip based on the master clock and sending the instant operation data to the data recording module when the master clock runs, and sending the instant operation data of the chip monitored currently to the data recording module based on the debugging clock after the master clock stops;
the data recording module is used for storing the instant operation data of the chip sent by the monitoring module into a preset storage area based on the master clock when the master clock runs, and storing the instant operation data of the chip sent by the monitoring module into the preset storage area based on the debugging clock after the master clock stops; when a data export instruction is received, exporting the data in the storage area based on the debugging clock so as to debug a chip;
and the clock switching control module is used for enabling the master clock to run the chip based on the master clock after receiving the master clock running instruction, and enabling the debugging clock after the master clock is stopped.
7. The chip debugging system of claim 6, wherein the clock switching control module is specifically configured to:
After receiving a master clock run instruction, enabling the master clock to run the chip based on the master clock,
stopping the operation of the master clock and enabling the debug clock after receiving a master clock stop instruction.
8. The chip debugging system of claim 6, wherein the clock switching control module is specifically configured to:
after receiving a master clock running instruction, enabling the master clock to run the chip based on the master clock;
and when the operation of the chip fails, stopping the operation of the main clock and starting the debugging clock.
9. The chip debugging system of claim 6, wherein the storage area is a storage area in a board-level off-chip storage device.
10. The chip debugging system of any one of claims 6 to 9, wherein the data logging module is further configured to:
when the real-time running data of the chip sent by the monitoring module is stored in a preset storage area, adding attribute information of the data stored in the storage area.
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