CN106487374A - A kind of High Speed Analog voltage signal buffer, chip and communication terminal - Google Patents
A kind of High Speed Analog voltage signal buffer, chip and communication terminal Download PDFInfo
- Publication number
- CN106487374A CN106487374A CN201611270447.6A CN201611270447A CN106487374A CN 106487374 A CN106487374 A CN 106487374A CN 201611270447 A CN201611270447 A CN 201611270447A CN 106487374 A CN106487374 A CN 106487374A
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- transistor
- high speed
- voltage signal
- speed analog
- analog voltage
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
Abstract
The invention discloses a kind of High Speed Analog voltage signal buffer, chip and communication terminal.The High Speed Analog voltage signal buffer includes multiple resistance, multiple transistors, two current sources and an operational amplifier.The present invention adopts special dynamic bias method of adjustment, operating current of the voltage buffer when input signal changes can be substantially improved, and keep its operating current less when input signal is not changed in, so as to the operating rate of voltage buffer on the premise of overall power is not lifted, is substantially improved.
Description
Technical field
The present invention relates to a kind of analog voltage signal buffer, more particularly to a kind of using the realization of dynamic bias method of adjustment
High Speed Analog voltage signal buffer, also relate to include the chip of the High Speed Analog voltage signal buffer and communication eventually
End, belongs to Analogous Integrated Electronic Circuits technical field.
Background technology
In Analogous Integrated Electronic Circuits, analog voltage signal buffer is one of the most widely used circuit module, its master
Act on and be to complete the buffering to weak voltage signals so that faint voltage signal can be transmitted to heavier load circuit
On.
Fig. 1 is shown in prior art, one typical analog voltage signal buffer (hereinafter referred to as voltage buffer)
Basic structure.It is mainly entered by a difference, operational amplifier (hereinafter referred to as operational amplifier) structure of Single-end output
Become, the negative input end of operational amplifier forms unit gain negative feedback structure, the positive input of operational amplifier with output end short circuit
The input as voltage buffer is held, the output of operational amplifier as the output end of voltage buffer, its allomeric function is
The voltage signal of output end follows input end signal to change.
In the prior art, in order to drive larger load circuit, generally using operation amplifier in raising voltage buffer
The method of the operating current of device is realized, but can so increase the power consumption of voltage buffer.For example in Application No.
201410359994.6 Chinese patent application in, Tsing-Hua University provide a kind of analog voltage buffer with high frequency compensation
Circuit.It includes：Principal voltage buffer；Main laod network connected with principal voltage buffer；High frequency compensation, high frequency compensation
Circuit is connected with principal voltage buffer, and high frequency compensation includes：Secondary voltage buffer；Connected with secondary voltage buffer time negative
Contained network network, secondary voltage buffer are connected with principal voltage buffer by time laod network, and wherein, in low frequency or direct current, high frequency is mended
Repay circuit and impact is not constituted on principal voltage buffer, high frequency compensation carries out electric current benefit to principal voltage buffer in high frequency
Repay.Compensation electric current can be fed through principal voltage buffer to compensate the load current effect of main laod network in high frequency by the circuit
Current compensation is carried out, raising voltage buffer is linear under high frequency input, extends bandwidth of operation.
Content of the invention
Primary technical problem to be solved by this invention is to provide a kind of High Speed Analog voltage signal buffer.
Another technical problem to be solved by this invention is that providing one kind includes the High Speed Analog voltage signal buffer
Chip and communication terminal.
In order to realize foregoing invention purpose, the present invention adopts following technical proposals：
According to embodiments of the present invention in a first aspect, provide a kind of High Speed Analog voltage signal buffer, including multiple electricity
Resistance, multiple transistors, two current sources and an operational amplifier；Wherein,
The grid of the first transistor and transistor seconds connects the output of the High Speed Analog voltage signal buffer respectively
End and input, the source electrode of the first transistor and transistor seconds are all connected to the drain electrode of the 7th transistor, the first transistor and
The drain electrode of transistor seconds is connected respectively to the drain electrode of third transistor and the 4th transistor；
The drain and gate of the 7th transistor is connected respectively to positive input terminal and the output end of operational amplifier, the 7th crystal
The source ground of pipe；
The source electrode of third transistor and the 4th transistor is all connected with power supply, and first resistor is connected on the grid of third transistor
And drain electrode between, second resistance is connected between the grid of the 4th transistor and drain electrode, third transistor and the 4th transistor
Grid is shorted together；
The grid of the 5th transistor and the 6th transistor connects the drain electrode of third transistor and the 4th transistor respectively, and the 5th
The source electrode of transistor and the 6th transistor is all connected with power supply, and the drain electrode of the 5th transistor and the 6th transistor connects the tenth crystalline substance respectively
Body pipe and the drain electrode of the 11st transistor；
Tenth transistor and the source grounding of the 11st transistor, the grid of the tenth transistor and the 11st transistor are short
It is connected together and is connected to the drain electrode of the tenth transistor；The drain electrode of the 6th transistor and the 11st transistor is all connected with the high speed
The output end of analog voltage signal buffer；
The grid of the 8th transistor and the 9th transistor connects the output of the High Speed Analog voltage signal buffer respectively
End and input, the drain electrode of the 8th transistor and the 9th transistor are all connected with power supply, the source of the 8th transistor and the 9th transistor
Pole is grounded by the first current source and the second current source respectively；
3rd resistor is connected between the source electrode of the 8th transistor and the negative input end of operational amplifier, the 4th resistant series
Between the source electrode and the negative input end of operational amplifier of the 9th transistor.
Wherein more preferably, the operational amplifier forms two-layer configuration, and the first order is five pipe Full differential operational amplifiers, adopts
Common mode feedback circuit is formed with diode connected mode, to stablize the output common mode voltage of the first order；The second level is dual input list
Export structure, forms voltage buffer.
Wherein more preferably, when the voltage buffer is in quiescent operation, the grid of the first transistor and transistor seconds
Source voltage difference is equal to the 8th transistor and the gate source voltage of the 9th transistor is poor.
Wherein more preferably, equivalently-sized when the first transistor and transistor seconds and the 8th transistor and the 9th transistor
When, the static working current of the first order is equal to the output current of the current source, and the static working current of the second level is brilliant by the 3rd
The mirror of body pipe, the 4th transistor, the 5th transistor and the 6th transistor determines.
Second aspect according to embodiments of the present invention, provides a kind of IC chip, which includes above-mentioned high speed
Analog voltage signal buffer.
The third aspect according to embodiments of the present invention, provides a kind of communication terminal, which includes above-mentioned High Speed Analog
Voltage signal buffer.
Compared with prior art, High Speed Analog voltage signal buffer provided by the present invention is inclined using special dynamic
Method of adjustment is put, operating current of the voltage buffer when input signal changes can be substantially improved, and not be had in input signal
Keep its operating current less during change, so as to the work of voltage buffer on the premise of overall power is not lifted, is substantially improved
Make speed.
Description of the drawings
Fig. 1 is the basic structure schematic diagram of a typical analog voltage signal buffer in prior art；
Fig. 2 is the circuit theory diagrams of High Speed Analog voltage signal buffer provided by the present invention.
Specific embodiment
The technology contents of the present invention are described in further detail with specific embodiment below in conjunction with the accompanying drawings.
As shown in Fig. 2 High Speed Analog voltage signal buffer provided by the present invention is mainly by resistance R1～R4, transistor
(preferably metal-oxide-semiconductor) M1～M11, I1～I2 and operational amplifier A 1 of current source constitute, and the concrete connection between them is closed
System is described as follows：The grid of transistor M1 and M2 is respectively connecting to output end V of this High Speed Analog voltage signal bufferoutWith
Input VinOn, the source electrode of transistor M1 and M2 is all connected to the drain electrode of transistor M7, and the drain electrode of transistor M1 and M2 connects respectively
It is connected in the drain electrode of transistor M3 and M4；The drain and gate of transistor M7 is connected respectively to the positive input terminal of operational amplifier A 1
And output end, the source electrode of transistor M7 is connected on ground wire；The source electrode of transistor M3 and M4 is connected on power vd D, resistance
R1 is connected between the grid of transistor M3 and drain electrode, and resistance R2 is connected between the grid of transistor M4 and drain electrode, transistor
The grid of M3 and M4 is shorted together；The grid of transistor M5 and M6 is respectively connecting to the drain electrode of transistor M3 and M4, transistor
The source electrode of M5 and M6 is connected on power vd D, and the drain electrode of transistor M5 and M6 is respectively connecting to the leakage of transistor M10 and M11
Pole；The source electrode of transistor M10 and M11 is connected on ground wire, and the grid of transistor M10 and M11 is shorted together and is connected to
In the drain electrode of M10；The drain electrode of transistor M6 and M11 is connected to output end V of this High Speed Analog voltage signal bufferoutOn；
The grid of transistor M8 and M9 is connected respectively to output end V of this High Speed Analog voltage signal bufferoutWith input VinOn,
The drain electrode of transistor M8 and M9 is connected to the source electrode of power vd D, transistor M8 and M9 and is connected by current source I1 and I2 respectively
To ground wire；Resistance R3 is connected between the negative input end of the source electrode of transistor M8 and operational amplifier A 1, and resistance R4 is connected on
Between the negative input end of the source electrode of transistor M9 and operational amplifier A 1.
The operation principle of the High Speed Analog voltage signal buffer is as follows：The periphery electricity connected by operational amplifier A 1
Road, makes the operational amplifier A 1 define two-layer configuration：The first order is five pipe Full differential operational amplifiers, and which adopts diode to connect
The mode of connecing forms simple common mode feedback circuit, to stablize the output common mode voltage of the first order.Resistance is added in order to improve gain
R1 and R2, so for differential output voltage, the grid of transistor M3 and M4 is the equal of virtual earth point, therefore transistor M3
With M4 performance more like current source.The second level is dual input list export structure, forms voltage buffer.When voltage buffer is in
During quiescent operation, due to the degenerative effect of unit gain, there is Vout=Vin, now due to the effect of inner feedback loop, crystal
The gate source voltage difference V of pipe M1, M2gsV poor equal to the gate source voltage of transistor M8, M9gs.When transistor M1, M2 and transistor M8,
M9 equivalently-sized when, the static working current of the first order is equal to the output of current source (I1=I2), and the static state of the second level
Operating current is determined by the mirror of transistor M3, M4 and transistor M5, M6.Assume when voltage buffer is stable, Vout=
Vin=VCM, the drain terminal voltage of transistor M7 is VCM—Vgs, therefore the gate source voltage difference of transistor M1 and M2 be Vgs, with crystal
Pipe M8 is identical with M9, and therefore when voltage buffer is in static state, the first level structure Zhong Mei road electric current is all identical with I1.Work as VinEnd
When there is a step signal upwards, VinTerminal voltage is changed into VCM+ Δ V, now VoutEnd is also not changed in, therefore in dynamic partially
In the presence of putting loop, the drain terminal voltage of M7 is changed into VCM- Vgs+ Δ V/2, so the gate source voltage difference of M1 is changed into Vgs- Δ V/2,
And the gate source voltage difference of M2 is changed into Vgs+ Δ V/2, therefore M1 branch current disappear, and there is instantaneous large-current in M2 branch road, then due to
The mirror image effect of the second level, M11 do not have electric current, and M6 flows through very big electric current, therefore by V in the short timeoutValue is charged to VCM+Δ
V so that VoutWith VinEqual again, it is VCM+ Δ V, and now the electrical leakage voltage of transistor M7 is changed into VCM+ Δ V-Vgs, therefore
The gate source voltage difference of M1 and M2 reverts to Vgs, operating current withdraws the membership static offset value I1.
In one embodiment of the invention, resistance R1～R4 is preferably the Chip-R of 30K Ω, current source I1's and I2
Operating current is preferably 12uA.Through it is experimentally confirmed that the High Speed Analog voltage signal buffer drives 80pF electric capacity to become from 0.8V
Change and take less than 200ns to 2.4V and average operating current about 220 μ A, offset voltage is about ± 5mV, static working current
About 140 μ A, Instantaneous Situation electric current average out to 2mA.It can thus be seen that High Speed Analog voltage signal buffering provided by the present invention
Device by using dynamic bias method of adjustment only when input signal changes its operating current can just become big several times, and defeated
Enter operating current after signal stops change and less quiescent value is return, greatly improve on the basis of relatively low average power consumption is kept
Buffer speed of the analog voltage signal buffer to variable signal, it is achieved thereby that very high dynamic driving ability.
High Speed Analog voltage signal buffer shown in above-described embodiment can be used in chip and (for example simulate integrated
Circuit chip) in.For the concrete structure of the High Speed Analog voltage signal buffer in the Analogous Integrated Electronic Circuits chip, here is just
No longer detail one by one.
In addition, above-mentioned High Speed Analog voltage signal buffer is can be used in communication terminal, as the integrated electricity of simulation
The important component part on road.Communication terminal mentioned here refers to support GSM, EDGE, TD_ used in mobile environment
The computer equipment of multiple communication standards such as SCDMA, TDD_LTE, FDD_LTE, including mobile phone, notebook computer, flat board
Computer, vehicle-mounted computer etc..Additionally, technical scheme provided by the present invention is also applied for the field of other Analogous Integrated Electronic Circuits applications
Close, such as communication base station etc..
Above High Speed Analog voltage signal buffer provided by the present invention, chip and communication terminal are carried out detailed
Explanation.For one of ordinary skill in the art, on the premise of without departing substantially from true spirit to it done any
Obvious change, all will constitute to infringement of patent right of the present invention, will undertake corresponding legal liabilities.
Claims (6)
1. a kind of High Speed Analog voltage signal buffer, it is characterised in that including multiple resistance, multiple transistors, two current sources
With an operational amplifier；Wherein,
The grid of the first transistor and transistor seconds connect respectively the High Speed Analog voltage signal buffer output end and
The source electrode of input, the first transistor and transistor seconds is all connected to the drain electrode of the 7th transistor, the first transistor and second
The drain electrode of transistor is connected respectively to the drain electrode of third transistor and the 4th transistor；
The drain and gate of the 7th transistor is connected respectively to positive input terminal and the output end of operational amplifier, the 7th transistor
Source ground；
The source electrode of third transistor and the 4th transistor is all connected with power supply, and first resistor is connected on the grid of third transistor and leakage
Between pole, second resistance is connected between the grid of the 4th transistor and drain electrode, the grid of third transistor and the 4th transistor
It is shorted together；
The grid of the 5th transistor and the 6th transistor connects the drain electrode of third transistor and the 4th transistor, the 5th crystal respectively
The source electrode of pipe and the 6th transistor is all connected with power supply, and the drain electrode of the 5th transistor and the 6th transistor connects the tenth transistor respectively
Drain electrode with the 11st transistor；
Tenth transistor and the source grounding of the 11st transistor, the grid short circuit of the tenth transistor and the 11st transistor exist
Together and it is connected to the drain electrode of the tenth transistor；The drain electrode of the 6th transistor and the 11st transistor is all connected with the High Speed Analog
The output end of voltage signal buffer；
The grid of the 8th transistor and the 9th transistor connect respectively the High Speed Analog voltage signal buffer output end and
Input, the drain electrode of the 8th transistor and the 9th transistor are all connected with power supply, and the source electrode of the 8th transistor and the 9th transistor divides
Tong Guo not the first current source and the second current source ground connection；
3rd resistor is connected between the source electrode of the 8th transistor and the negative input end of operational amplifier, and the 4th resistant series are
Between the source electrode of nine transistors and the negative input end of operational amplifier.
2. High Speed Analog voltage signal buffer as claimed in claim 1, it is characterised in that：
The operational amplifier forms two-layer configuration, and the first order is five pipe Full differential operational amplifiers, using diode connection side
Formula forms common mode feedback circuit, to stablize the output common mode voltage of the first order；The second level is dual input list export structure, forms electricity
Compression buffer.
3. High Speed Analog voltage signal buffer as claimed in claim 2, it is characterised in that：
When the voltage buffer is in quiescent operation, the gate source voltage difference of the first transistor and transistor seconds is equal to the 8th
The gate source voltage of transistor and the 9th transistor is poor.
4. High Speed Analog voltage signal buffer as claimed in claim 2, it is characterised in that：
When the first transistor and transistor seconds and the 8th transistor and the 9th transistor equivalently-sized when, the static state of the first order
Operating current is equal to the output current of the current source, the static working current of the second level by third transistor, the 4th transistor,
The mirror of the 5th transistor and the 6th transistor determines.
5. a kind of IC chip, it is characterised in that include in the IC chip any one in Claims 1 to 4
High Speed Analog voltage signal buffer described in.
6. a kind of communication terminal, it is characterised in that include in Claims 1 to 4 described in any one in the communication terminal
High Speed Analog voltage signal buffer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611270447.6A CN106487374B (en) | 2016-12-31 | 2016-12-31 | High-speed analog voltage signal buffer, chip and communication terminal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611270447.6A CN106487374B (en) | 2016-12-31 | 2016-12-31 | High-speed analog voltage signal buffer, chip and communication terminal |
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| Publication Number | Publication Date |
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| CN106487374A true CN106487374A (en) | 2017-03-08 |
| CN106487374B CN106487374B (en) | 2022-09-20 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110224678A (en) * | 2019-06-28 | 2019-09-10 | 深圳市锐能微科技有限公司 | Analogue buffer, tension measuring circuit and electric energy computation chip |
| CN112468101A (en) * | 2021-01-28 | 2021-03-09 | 上海灵动微电子股份有限公司 | Buffer with ultra-low static power consumption |
| WO2021102793A1 (en) * | 2019-11-28 | 2021-06-03 | 华为技术有限公司 | Operational amplifier, chip and electronic device |
| CN117453605A (en) * | 2023-12-26 | 2024-01-26 | 深圳市芯波微电子有限公司 | Signal output buffer, signal chip and printed circuit board |
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| CN103575964A (en) * | 2012-07-19 | 2014-02-12 | 快捷半导体(苏州)有限公司 | Over-current detection circuit and method for power switch tube |
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| US20080018401A1 (en) * | 2006-07-10 | 2008-01-24 | Samsung Electro-Mechanics Co., Ltd. | Variable gain amplifier with wide gain variation and wide bandwidth |
| CN101714868A (en) * | 2008-09-30 | 2010-05-26 | 奇景光电股份有限公司 | Output buffer and source driver using the same |
| CN102412824A (en) * | 2011-12-02 | 2012-04-11 | 上海贝岭股份有限公司 | Differential reference voltage buffer |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110224678A (en) * | 2019-06-28 | 2019-09-10 | 深圳市锐能微科技有限公司 | Analogue buffer, tension measuring circuit and electric energy computation chip |
| WO2021102793A1 (en) * | 2019-11-28 | 2021-06-03 | 华为技术有限公司 | Operational amplifier, chip and electronic device |
| CN112468101A (en) * | 2021-01-28 | 2021-03-09 | 上海灵动微电子股份有限公司 | Buffer with ultra-low static power consumption |
| CN112468101B (en) * | 2021-01-28 | 2021-04-30 | 上海灵动微电子股份有限公司 | Buffer with ultra-low static power consumption |
| CN117453605A (en) * | 2023-12-26 | 2024-01-26 | 深圳市芯波微电子有限公司 | Signal output buffer, signal chip and printed circuit board |
| CN117453605B (en) * | 2023-12-26 | 2024-04-12 | 深圳市芯波微电子有限公司 | Signal output buffer, signal chip and printed circuit board |
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| CN106487374B (en) | 2022-09-20 |
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