CN112468101B - Buffer with ultra-low static power consumption - Google Patents
Buffer with ultra-low static power consumption Download PDFInfo
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- CN112468101B CN112468101B CN202110114776.6A CN202110114776A CN112468101B CN 112468101 B CN112468101 B CN 112468101B CN 202110114776 A CN202110114776 A CN 202110114776A CN 112468101 B CN112468101 B CN 112468101B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
- H03F3/16—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only with field-effect devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
Abstract
The application provides a buffer with ultra-low static power consumption. In the buffer, the grids of the first NMOS, the seventh NMOS and the eighth NMOS are connected with a signal input end; the source electrodes of the first and second NMOS are connected with the drain electrode of the fourth NMOS, the drain electrode of the first NMOS is connected with the drain electrode of the first PMOS and the grid electrodes of the first to fourth PMOS, the drain electrode of the second NMOS is connected with the drain electrode of the second PMOS, and the grid electrode of the second NMOS is connected with the drain electrode of the ninth PMOS and the source electrode of the tenth PMOS; the source electrode of the seventh NMOS and the drain electrode of the tenth NMOS are connected with the drain electrode of the fifth NMOS, and the drain electrode of the seventh NMOS is connected with the drain electrode of the third PMOS and the gate electrode of the ninth PMOS; the source electrode of the eighth NMOS and the drain electrode of the twelfth PMOS are connected with the drain electrode of the sixth NMOS, the drain electrode of the eighth NMOS is connected with the drain electrode of the fourth PMOS and the grid electrode of the eleventh PMOS, and the drain electrode of the eleventh PMOS and the source electrode of the twelfth PMOS are connected with the signal output end. The buffer can drive a large load, and has high transient response and high power supply rejection ratio.
Description
Technical Field
The present application relates to the field of integrated circuits, and more particularly to a buffer with ultra-low static power consumption.
Background
The buffer is used for improving the driving capability of circuit signals, can isolate input signals and output signals, reduces the interference of the output signals to the input signals, has high transient response, and achieves the optimum in power consumption delay product when the circuit obtains the required driving capability. The design difficulty of the current buffer is that large power consumption and chip area are consumed to drive a large capacitive load and a small resistive load, and therefore, a buffer design capable of reducing the power consumption and the chip area is required to be provided.
Disclosure of Invention
The application aims to provide a buffer with ultralow static power consumption, which can drive a large load and has high transient response and high power supply rejection ratio.
The application discloses buffer of ultralow static power consumption includes: first to eighth NMOS transistors and first to twelfth PMOS transistors, wherein:
the gates of the first NMOS transistor, the seventh NMOS transistor and the eighth NMOS transistor are all connected with a signal input end;
the source electrodes of the first NMOS transistor and the second NMOS transistor are connected with the drain electrode of the fourth NMOS transistor, the drain electrode of the first NMOS transistor is connected with the drain electrode of the first PMOS transistor and the grid electrodes of the first PMOS transistor, the drain electrode of the second NMOS transistor is connected with the drain electrode of the second PMOS transistor, and the grid electrode of the second NMOS transistor is connected with the drain electrode of the ninth PMOS transistor and the source electrode of the tenth PMOS transistor;
a source electrode of the seventh NMOS transistor and a drain electrode of the tenth NMOS transistor are connected with a drain electrode of the fifth NMOS transistor, and a drain electrode of the seventh NMOS transistor is connected with a drain electrode of the third PMOS transistor and a grid electrode of the ninth PMOS transistor;
the source electrode of the eighth NMOS transistor and the drain electrode of the twelfth PMOS transistor are connected with the drain electrode of the sixth NMOS transistor, the drain electrode of the eighth NMOS transistor is connected with the drain electrode of the fourth PMOS transistor and the grid electrode of the eleventh PMOS transistor, and the drain electrode of the eleventh PMOS transistor and the source electrode of the twelfth PMOS transistor are connected with a signal output end;
the drain electrode of the third NMOS transistor is connected with the grid electrodes of the third to sixth NMOS transistors, and the source electrodes of the third to sixth NMOS transistors are all connected with a ground end;
the sources of the first to fourth PMOS transistors and the source of the eleventh PMOS transistor are connected with a power supply end.
In a preferred example, the third PMOS transistor and the fourth PMOS transistor, the tenth PMOS transistor and the twelfth PMOS transistor, the seventh NMOS transistor and the eighth NMOS transistor, and the fifth NMOS transistor and the sixth NMOS transistor are all identical.
In a preferred embodiment, a width-to-length ratio of the eleventh PMOS transistor is larger than a width-to-length ratio of the ninth PMOS transistor.
In a preferred embodiment, the method further comprises the following steps: the resistor and the capacitor are respectively connected between the signal output end and the ground end.
In a preferred embodiment, the method further comprises the following steps: the current source, a thirteenth PMOS transistor and a ninth NMOS transistor, wherein the thirteenth PMOS transistor and the ninth NMOS transistor are connected in parallel between the current source and the gate of the third NMOS transistor, the gate of the thirteenth PMOS transistor and the gate of the ninth NMOS transistor are respectively connected with a pair of inverted control signals, and the current source is connected between the power supply end and the ninth NMOS transistor.
In a preferred embodiment, the method further comprises the following steps: the first compensation capacitor is connected between the drain electrode of the second NMOS transistor and the ground end; the first compensation capacitance is adjusted larger when a phase margin of the buffer circuit is below a first predetermined threshold.
In a preferred embodiment, the method further comprises the following steps: a second compensation capacitor connected between the power supply terminal and the gate of the ninth PMOS transistor; and when the phase margin of the buffer circuit is lower than a second preset threshold value, the second compensation capacitor is increased.
In a preferred embodiment, the method further comprises the following steps: a third compensation capacitor and a compensation resistor, which are connected in series between the power supply terminal and the gate of the eleventh PMOS transistor; and when the phase margin of the buffer circuit is lower than a third preset threshold value, the third compensation capacitor is increased.
Compared with the prior art, the buffer with ultralow static power consumption has the following beneficial effects:
the buffer circuit can drive large capacitive load and small resistive load, has high transient response and high power supply rejection ratio, independently separates driving output level and reference level in the buffer circuit design, has strong anti-interference capability, and the reference level circuit only needs nanoampere level current to maintain work, provides stable output static working point, so the whole circuit can accomplish extremely low power consumption.
A large number of technical features are described in the specification, and are distributed in various technical solutions, so that the specification is too long if all possible combinations of the technical features (namely, the technical solutions) in the application are listed. In order to avoid this problem, the respective technical features disclosed in the above summary of the invention of the present specification, the respective technical features disclosed in the following embodiments and examples, and the respective technical features disclosed in the drawings may be freely combined with each other to constitute various new technical solutions (which should be regarded as having been described in the present specification) unless such a combination of the technical features is technically impossible. For example, in one example, the feature a + B + C is disclosed, in another example, the feature a + B + D + E is disclosed, and the features C and D are equivalent technical means for the same purpose, and technically only one feature is used, but not simultaneously employed, and the feature E can be technically combined with the feature C, then the solution of a + B + C + D should not be considered as being described because the technology is not feasible, and the solution of a + B + C + E should be considered as being described.
Drawings
FIG. 1 is a diagram illustrating an exemplary buffer with ultra-low static power consumption;
FIG. 2 is a diagram illustrating a mirror structure of an ultra-low quiescent power buffer according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a feedback loop of an ultra-low static power buffer according to an embodiment of the present application;
fig. 4 is a schematic diagram of a compensation circuit of a buffer with ultra-low static power consumption according to an embodiment of the present application.
Detailed Description
In the following description, numerous technical details are set forth in order to provide a better understanding of the present application. However, it will be understood by those skilled in the art that the technical solutions claimed in the present application may be implemented without these technical details and with various changes and modifications based on the following embodiments.
To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
The application discloses a buffer with ultra-low static power consumption, fig. 1 shows a schematic diagram of a buffer 100 with ultra-low static power consumption, the buffer 100 includes: first to eighth NMOS transistors and first to twelfth PMOS transistors.
Gates of the first, seventh, and eighth NMOS transistors NM1, NM7, and NM8 are connected to the signal input terminal VIN.
Sources of the first and second NMOS transistors NM1 and NM2 are both connected to a drain of the fourth NMOS transistor NM4, a drain of the first NMOS transistor NM1 is connected to a drain of the first PMOS transistor PM1 and gates of the first to fourth PMOS transistors PM1, PM2, PM3, PM4, a drain of the second NMOS transistor NM2 is connected to a drain of the second PMOS transistor PM2, and a gate of the second NMOS transistor NM2 is connected to a drain of the ninth PMOS transistor PM9 and a source of the tenth PMOS transistor PM 10.
A source of the seventh NMOS transistor NM7 and a drain of the tenth NMOS transistor NM10 are connected to a drain of the fifth NMOS transistor NM5, and a drain of the seventh NMOS transistor NM7 is connected to a drain of the third PMOS transistor PM3 and a gate of the ninth PMOS transistor PM 10.
The source of the eighth NMOS transistor NM8 and the drain of the twelfth PMOS transistor PM12 are connected to the drain of the sixth NMOS transistor NM6, the drain of the eighth NMOS transistor NM8 is connected to the drain of the fourth PMOS transistor PM4 and the gate of the eleventh PMOS transistor PM11, and the drain of the eleventh PMOS transistor PM11 and the source of the twelfth PMOS transistor PM12 are connected to the signal output terminal VOUT.
The drain of the third NMOS transistor NM3 is connected to the gates of the third to sixth NMOS transistors NM3, NM4, NM5, NM6, and the sources of the third to sixth NMOS transistors NM3, NM4, NM5, NM6 are all connected to ground.
The sources of the first to fourth PMOS transistors PM1, PM2, PM3, PM4 and the eleventh PMOS transistor PM11 are all connected to a power supply terminal.
In one embodiment, the buffer 100 further comprises: the resistor R1 and the capacitor C1, the resistor R1 and the capacitor C1 are respectively connected between the signal output terminal VOUT and the ground terminal.
In one embodiment, the buffer 100 further comprises: current source I0A thirteenth PMOS transistor PM13 and a ninth NMOS transistor NM9, the thirteenth PMOS transistor PM13 and the ninth NMOS transistor NM9 are connected in parallel to the current source I0And a gate (or drain) of the third NMOS transistor NM3, a gate of the ninth NMOS transistor PM9 is connected to the control signal EN, and a gate of the thirteenth PMOS transistor PM13 is connected to the control signal ENB, the control signals EN and ENB being a pair of inverted signals, and the current source I0Is connected between a power supply terminal and the ninth NMOS transistor NM9 (or the third PMOS transistor PM 13).
Referring to fig. 2, in the buffer, the partial circuit of the dashed box 202 is a mirror image of the partial circuit of the dashed box 201, and the partial circuit of the dashed box 201 and the partial circuit of the dashed box 202 in the circuit must be exactly the same, that is: the third and fourth PMOS transistors PM3, PM4, the tenth and twelfth PMOS transistors PM10, PM12, the seventh and eighth NMOS transistors PM7, PM8, and the fifth and sixth NMOS transistors PM5, PM6 are all identical. Further, the width-to-length ratio of the eleventh PMOS transistor PM11 is larger than the width-to-length ratio of the ninth PMOS transistor PM 9.
Referring to fig. 3, in the buffer circuit, a part of the circuit of the dashed line box 301 is used to provide a reference voltage, a part of the dashed line box 302 is used as a mirror driving output stage, the first NMOS transistor, the second NMOS transistor NM2, the first PMOS transistor PM1, the second PMOS transistor PM2, and the fourth NMOS transistor NM4 in the dashed line box 301 constitute a single-stage amplifier (or referred to as a reference stage circuit), the first NMOS transistor NM1 and the second NMOS transistor NM2 are mirror structures, a gate voltage of the first NMOS transistor NM1 is exactly equal to a gate voltage of the second NMOS transistor NM2, and a gate of the second NMOS transistor NM2 to a source of the tenth PMOS transistor PM10 are feedback loops. The partial circuit of the dashed line box 301 provides 4 sets of reference voltages to the output stage of the dashed line box 302, the gate voltages of the fourth PMOS transistor PM4 and the sixth NMOS transistor NM6 generate the reference current, the gate voltage of the eighth NMOS transistor NM8 provides the dc bias voltage, and the buffer voltage VOUT of the output stage is mainly determined by the gate voltage of the twelfth PMOS transistor PM 12.
When the output terminal VOUT is pulled down instantaneously, VGS of the twelfth PMOS transistor PM12 decreases, the fine adjustment current flowing through the eleventh PMOS transistor PM11 and the twelfth PMOS transistor PM12 decreases, the total current flowing through the sixth NMOS transistor NM6 does not change, so that the current flowing through the eighth NMOS transistor NM8 increases, the gate voltage of the eleventh PMOS transistor PM11 decreases, the signal fed back by the eleventh PMOS transistor PM11 increases the current, and the output terminal VOUT recovers to a stable output voltage. Similarly, when the output terminal VOUT is pulled high momentarily, VGS of the twelfth PMOS transistor PM12 increases, the fine tuning current flowing through the eleventh PMOS transistor PM11 and the twelfth PMOS transistor PM12 increases, the total current flowing through the sixth NMOS transistor NM6 does not change, so that the current flowing through the eighth NMOS transistor NM8 decreases, the gate voltage of the eleventh PMOS transistor PM11 increases, the signal fed back by the eleventh PMOS transistor PM11 decreases, and the output terminal VOUT recovers to a stable output voltage.
The buffer in this embodiment has three feedback loops, such as feedback loops 401, 402, 403 in fig. 3, where transistors PM3, PM9, PM10, NM7, NM5 constitute feedback loop 402, transistors PM1, PM2, NM1, NM2, NM4 and nested feedback loop 402 constitute feedback loop 401, and transistors PM4, PM11, PM12, NM6, NM8 constitute feedback loop 403. Part of the circuits of the feedback loop 401 are used as reference levels, part of the circuits of the feedback loop 403 are used as circuit driving output levels, and the feedback loop 402 and the feedback loop 403 which are nested in the feedback loop 401 are completely consistent in circuit and form mirror image output. When the voltage of the output terminal VOUT changes, it can be seen from the above that the voltage change of the single-stage amplifier is not affected. In the embodiment, the driving output stage and the reference stage are independently separated, the anti-interference capability is strong, the reference stage circuit only needs nanoampere current to maintain work, and a stable output static working point is provided, so that the whole circuit can achieve extremely low power consumption.
Referring to fig. 4, the buffer 100 further includes: a first compensation capacitor CC1, a first compensation capacitor CC1 is connected between the drain of the second NMOS transistor NM2 and ground. The buffer 100 further includes: a second compensation capacitor CC2, a second compensation capacitor CC2 is connected between the power source terminal and the gate of the ninth PMOS transistor PM 9. In one embodiment, the buffer 100 further comprises: a third compensation capacitor CC3 and a compensation resistor R2, and the third compensation capacitor CC3 and the compensation resistor R2 are connected in series between the power supply terminal and the gate of the eleventh PMOS transistor PM 11.
In the buffer circuit, the compensation capacitor CC1 determines the position of the dominant pole, which is usually caused by a larger capacitance inside the operational amplifier, and the calculation formula ω = gm/C of the pole indicates that gm is the first-stage transconductance and C is the total capacitance of the high-resistance node, when the compensation capacitor CC1 is increased, the dominant pole ω is decreased, and under the condition that the secondary point is not changed, the two poles are separated, and the phase margin is improved. The larger the capacitance is, the larger the phase margin is, the higher the stability is, the zero adjusting resistor R2 is connected with the compensating capacitor CC3 in series, when the CC3 is increased, the main pole omega of the driving stage is reduced, the two poles are separated, the phase margin is increased, a zero point is introduced, when R2>1/gm (PM12), the gain reduction is slowed down, the larger phase shift is generated, and the stability of a loop is increased.
As shown in conjunction with fig. 3 and 4, when the feedback loop 401 has insufficient phase margin, the compensation capacitor CC1 is increased until the phase margin is met to be greater than or equal to a first predetermined threshold, e.g., 60 degrees. When the feedback loop 402 has insufficient phase margin, the compensation capacitor CC2 is adjusted up until the phase margin is met to be greater than or equal to a second predetermined threshold, e.g., 60 degrees. When the feedback loop 403 has insufficient phase margin, the compensation capacitor CC3 is increased until the phase margin is met to be greater than or equal to a third predetermined threshold, e.g., 60 degrees. It should be noted that if the phase margins of the 3 feedback loops themselves meet the threshold condition of the respective phase margin, e.g. more than 60 degrees, the respective capacitances may not be adjusted.
It is noted that, in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the use of the verb "comprise a" to define an element does not exclude the presence of another, same element in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that a certain action is executed according to a certain element, it means that the action is executed according to at least the element, and two cases are included: performing the action based only on the element, and performing the action based on the element and other elements. The expression of a plurality of, a plurality of and the like includes 2, 2 and more than 2, more than 2 and more than 2.
All documents mentioned in this specification are to be considered as being incorporated in their entirety into the disclosure of this specification so as to be subject to modification as necessary. It should be understood that the above description is only a preferred embodiment of the present disclosure, and is not intended to limit the scope of the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of one or more embodiments of the present disclosure should be included in the scope of protection of one or more embodiments of the present disclosure.
Claims (7)
1. A buffer with ultra-low static power consumption, comprising: first to eighth NMOS transistors and first to twelfth PMOS transistors, wherein:
the gates of the first NMOS transistor, the seventh NMOS transistor and the eighth NMOS transistor are all connected with a signal input end;
the source electrodes of the first NMOS transistor and the second NMOS transistor are connected with the drain electrode of the fourth NMOS transistor, the drain electrode of the first NMOS transistor is connected with the drain electrode of the first PMOS transistor and the grid electrodes of the first PMOS transistor, the drain electrode of the second NMOS transistor is connected with the drain electrode of the second PMOS transistor, and the grid electrode of the second NMOS transistor is connected with the drain electrode of the ninth PMOS transistor and the source electrode of the tenth PMOS transistor;
a source electrode of the seventh NMOS transistor and a drain electrode of the tenth NMOS transistor are connected with a drain electrode of the fifth NMOS transistor, and a drain electrode of the seventh NMOS transistor is connected with a drain electrode of the third PMOS transistor and a grid electrode of the ninth PMOS transistor;
the source electrode of the eighth NMOS transistor and the drain electrode of the twelfth PMOS transistor are connected with the drain electrode of the sixth NMOS transistor, the drain electrode of the eighth NMOS transistor is connected with the drain electrode of the fourth PMOS transistor and the grid electrode of the eleventh PMOS transistor, and the drain electrode of the eleventh PMOS transistor and the source electrode of the twelfth PMOS transistor are connected with a signal output end;
the drain electrode of the third NMOS transistor is connected with the grid electrodes of the third to sixth NMOS transistors, and the source electrodes of the third to sixth NMOS transistors are all connected with a ground end;
the sources of the first to fourth PMOS transistors and the source of the eleventh PMOS transistor are connected with a power supply end;
further comprising: the current source, a thirteenth PMOS transistor and a ninth NMOS transistor, wherein the thirteenth PMOS transistor and the ninth NMOS transistor are connected in parallel between the current source and the gate of the third NMOS transistor, the gate of the thirteenth PMOS transistor and the gate of the ninth NMOS transistor are respectively connected with a pair of inverted control signals, and the current source is connected between the power supply end and the ninth NMOS transistor.
2. The ultra-low static power consumption buffer of claim 1, wherein the third and fourth PMOS transistors, the tenth and twelfth PMOS transistors, the seventh and eighth NMOS transistors, and the fifth and sixth NMOS transistors are all identical.
3. The buffer of claim 2, wherein the eleventh PMOS transistor has a larger width-to-length ratio than the ninth PMOS transistor.
4. The ultra-low static power consumption buffer of claim 1, further comprising: the resistor and the capacitor are respectively connected between the signal output end and the ground end.
5. The ultra-low static power consumption buffer of claim 1, further comprising: the first compensation capacitor is connected between the drain electrode of the second NMOS transistor and the ground end; the first compensation capacitance is adjusted larger when a phase margin of the buffer circuit is below a first predetermined threshold.
6. The ultra-low static power consumption buffer of claim 1, further comprising: a second compensation capacitor connected between the power supply terminal and the gate of the ninth PMOS transistor; and when the phase margin of the buffer circuit is lower than a second preset threshold value, the second compensation capacitor is increased.
7. The ultra-low static power consumption buffer of claim 1, further comprising: a third compensation capacitor and a compensation resistor, which are connected in series between the power supply terminal and the gate of the eleventh PMOS transistor; and when the phase margin of the buffer circuit is lower than a third preset threshold value, the third compensation capacitor is increased.
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| CN202110114776.6A CN112468101B (en) | 2021-01-28 | 2021-01-28 | Buffer with ultra-low static power consumption |
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| CN202110114776.6A CN112468101B (en) | 2021-01-28 | 2021-01-28 | Buffer with ultra-low static power consumption |
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| CN112468101B true CN112468101B (en) | 2021-04-30 |
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| CN102385408A (en) * | 2011-09-21 | 2012-03-21 | 电子科技大学 | Low dropout linear voltage regulator |
| CN102739175A (en) * | 2011-04-01 | 2012-10-17 | Nxp股份有限公司 | Source or emitter follower buffer circuit and method |
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2021
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| CN101204008A (en) * | 2005-06-10 | 2008-06-18 | 统宝香港控股有限公司 | Buffer circuit |
| US20070164974A1 (en) * | 2006-01-13 | 2007-07-19 | Dong-Ryul Chang | Output buffer with improved output deviation and source driver for flat panel display having the output buffer |
| CN102739175A (en) * | 2011-04-01 | 2012-10-17 | Nxp股份有限公司 | Source or emitter follower buffer circuit and method |
| CN102385408A (en) * | 2011-09-21 | 2012-03-21 | 电子科技大学 | Low dropout linear voltage regulator |
| CN106487374A (en) * | 2016-12-31 | 2017-03-08 | 唯捷创芯(天津)电子技术股份有限公司 | A kind of High Speed Analog voltage signal buffer, chip and communication terminal |
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Address after: Room 301, building 10, 399 Keyuan Road, Zhangjiang Town, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai, 201203 Applicant after: SHANGHAI MINDMOTION MICROELECTRONICS Co.,Ltd. Address before: 2-1, 2 / F, building 10, 399 Keyuan Road, Zhangjiang Town, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai, 201203 Applicant before: SHANGHAI MINDMOTION MICROELECTRONICS Co.,Ltd. |
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