CN204517765U - The rail-to-rail operational amplifier of the wide amplitude of oscillation - Google Patents

Abstract

The utility model discloses the rail-to-rail operational amplifier of a kind of wide amplitude of oscillation, comprise: voltage input module, its input is connected with source voltage signal, and converts voltage signal to current signal; First order output module, its input is connected with the output of voltage input module; Voltage reduction module, it is connected with the output of voltage input module and the input of first order output module respectively; Class-AB control module, it is connected with first order output module, controls the output of first order output module, realizes rail-to-rail output; Second level output module, it is connected with first order output module, and first order output module exports for second level output module provides bias voltage to realize push-pull type.The utility model efficiently solves the problem of rail-to-rail amplifier gain decline in case of high pressures and DC maladjustment increase, and does not increase complexity and the power consumption of circuit.

Description

The rail-to-rail operational amplifier of the wide amplitude of oscillation

Technical field

The utility model relates to a kind of operational amplifier, particularly the rail-to-rail operational amplifier of the wide amplitude of oscillation of one.

Background technology

The rail-to-rail operational amplifier of the wide amplitude of oscillation (Rail-to-Rail Operational Amplifier) is extensive use, has the circuit unit of superelevation multiplication factor, is widely used in each electronic product.Due to the change of technique and temperature, some indexs that amplifier itself has, as the indexs such as input offset voltage can change, and amplifier is generally applied in closed loop, therefore high-gain amplifier to minimizing imbalance and error all most important.But when inputting the amplitude of oscillation and being larger, we find that gain can along with the increase of input voltage, the variation tendency diminished again of changing from small to big, and gain minimizing produces a lot of adverse influence to the practical application of amplifier.

As shown in Figure 1, in order to can normally work, its supply voltage must meet the following conditions traditional rail-to-rail amplifier amplifier:

$V_{\mathrm{DD}}\≥\max \{V_{\mathrm{GS}21}+V_{\mathrm{GS}22}+V_{I_{0^{\text{'}}}}{V}_{\mathrm{GS}19}+V_{\mathrm{GS}20}+V_{1_1}\}---\left(1\right)$ Wherein, V _gs21represent the gate source voltage of metal-oxide-semiconductor M21; V _irepresent the voltage at current source two ends; V _dDrepresent supply voltage.

Therefore when this structure can not be applied to low supply voltage.Usually for the technique of tsmc025um, the regular threshold voltage of metal-oxide-semiconductor is approximately 1V, and the pressure reduction at current source two ends is 0.2V, and namely in order to enable circuit normally work, supply voltage is generally greater than 2V.Therefore this structure is for requiring that supply voltage is at 1.6V, even still can normally work when 1.4V, is unacceptable.

In order to make circuit still can normally work in respect of low supply voltages, Fig. 2 gives one more rational structure.By analysis chart 2, we can draw, the change in voltage trend of A, B 2 is identical, shows the effect of Class AB.Then Mn ₉the voltage difference at source and drain two ends is:

V _ds，n9＝V _DD-V _GS·p15-V _DS·n11(2)

Wherein, V _{ds, n9}represent M _n9source-drain voltage; V _{gS, p15}represent M _p15gate source voltage; VDD represents supply voltage; V _{dS, n11}represent M _n11source-drain voltage.

As can be seen from formula (2), along with the rising of supply voltage, Mn ₉the voltage at source and drain two ends also raises.MOS transistor device Mn ₉drain terminal and substrate between direction bias voltage also can along with increase, when this voltage difference reach certain value obtain time, drain terminal and the charge carrier between sinking to the bottom in drain depletion region because collision produces electron-hole pair, wherein partial holes flows to substrate and forms substrate current, and this impact can with a controlled current source I from drain terminal to substrate terminal _dBcarry out equivalence, as shown in Figure 3.Show according to correlative study experience, electric current I _dBcan be expressed as:

$I_{\mathrm{DB}}=K_1(V_{\mathrm{DS}}-V_{\mathrm{DS}\left(\mathrm{act}\right)})I_D\exp (-\frac{K_2}{V_{\mathrm{DS}}-V_{\mathrm{DS}\left(\mathrm{act}\right)}})---\left(3\right)$

Wherein, K ₁and K ₂procedure parameter, relevant with the type of technique and metal-oxide-semiconductor.V _{ds (act)}the minimum V of transistor required for amplification region _dsvalue.

This impact is much smaller for PMOS device, because the ability that the hole in raceway groove produces hole-electron right wants the ability of the electronics of specific energy abundance much lower.The impact of above-mentioned phenomenon on circuit performance is mainly reflected in Lou breaks and there is a dead resistance between substrate.Formula (3) is differentiated, can obtain leakage-substrate between small-signal conductance be:

$g_{\mathrm{db}}=\frac{\∂I_{\mathrm{DB}}}{\∂{\mathrm{VI}}_D}=\frac{I_{\mathrm{DB}}}{V_{\mathrm{DS}}-V_{\mathrm{DS}\left(\mathrm{act}\right)}}(\frac{K_2}{V_{\mathrm{DS}}-V_{\mathrm{DS}\left(\mathrm{act}\right)}}+1)\≈\frac{K_2{I}_{\mathrm{DB}}}{{(V_{\mathrm{DS}}-V_{\mathrm{DS}\left(\mathrm{act}\right)})}^2}---\left(4\right)$

Wherein, g _dbfor the mutual conductance of drain terminal and substrate terminal.

As can be seen from formula (3), (4), the dead resistance between leakage-substrate presents the impact of index, therefore along with V _dSbetween the increase of voltage, the impact of this resistance can not be ignored, and Fig. 4 gives tsmc025um, under ttcorner process condition, impedance and V between typical N metal-oxide-semiconductor leakage-substrate _dSbetween relation.Look down from the A point Fig. 2, its equiva lent impedance is designated as r ₀₁, be approximately by calculating:

$r_{01}\≈\frac{g_{m,\mathrm{mn}9}}{g_{\mathrm{ds},\mathrm{mn}9}{g}_{\mathrm{ds},\mathrm{mn}11}}\≈400\mathrm{M\Ω}---\left(5\right)$

As can be seen from Fig. 4 we, the spurious impedance of leakage-substrate is along with the change of temperature and source and drain terminal voltage difference, and the temperature that four curves are corresponding is from top to bottom 120 DEG C, 80 DEG C, 25 DEG C ,-45 DEG C respectively, from Fig. 4, get V respectively _dSfor the r in 0.2V, 1V, 2V, 3V, 4V five kinds of situations _dbcomposition table-1, as can be seen from table-1, works as V _dSvalue when being less than 3V, r _dball be greater than r ₀₁, this hourglass breaks-and the impact of substrate parasitics resistance can ignore.

Table-1 temperature and source and drain terminal voltage difference are on the impact of leakage-substrate parasitics resistance

Note: the unit of resistance is M Ω

Can also be found by emulation, when source and drain terminal voltage difference is more than more than 3.5V time, between leakage-substrate, spurious impedance also can have a huge impact DC maladjustment, as shown in Figure 5.Therefrom can find out, work as Mn ₉the DC maladjustment that source and drain terminal voltage surpasses 3.5V is about Mn ₉5 times time source and drain terminal voltage difference is 1V.Due to Mn ₉upper source and drain terminal voltage difference is excessive, causes detrimental effects, and reduces the performance of whole rail-to-rail amplifier.

Utility model content

The purpose of this utility model is to provide the rail-to-rail operational amplifier of a kind of wide amplitude of oscillation, efficiently solves the problem of rail-to-rail amplifier gain decline in case of high pressures and DC maladjustment increase, and does not increase complexity and the power consumption of circuit.

In order to realize above object, the utility model is achieved through the following technical solutions:

The rail-to-rail operational amplifier of a kind of wide amplitude of oscillation, comprises:

Voltage input module, the input of described voltage input module is connected with source voltage signal, and converts voltage signal to current signal;

First order output module, the input of described first order output module is connected with the output of voltage input module;

Voltage reduction module, described voltage reduction module is connected with the output of voltage input module and the input of first order output module respectively;

Class-AB control module, described Class-AB control module is connected with first order output module, controls the output of first order output module, realizes rail-to-rail output;

Second level output module, described second level output module is connected with first order output module, and described first order output module provides bias voltage for second level output module, realizes push-pull type and exports.

Described voltage input module comprises input first branch road and input second branch road of circuit connection, described first order output module comprises one-level first branch road and one-level second branch road of circuit connection, described input first branch road is connected with one-level first branch road, and described input second branch road is connected with one-level second branch road.

Described input first branch road and one-level first branch road comprise the PMOS that several circuit are connected respectively; Described input second branch road and one-level second branch road comprise the NMOS tube that several circuit are connected.

Described input first branch road comprises circuit connection: first, second, third, fourth, the 5th and the 6th PMOS;

The grid of described first PMOS connects anode input signal;

The grid of described second PMOS connects negative terminal input signal;

Described first, second and the source electrode and the 3rd of the 6th PMOS, the drain electrode of the 4th PMOS are connected;

The source electrode of described 3rd, the 4th and the 5th PMOS connects supply voltage;

The grid of described 3rd, the 6th PMOS connects the first bias voltage respectively;

The grid of described 4th, the 5th PMOS and the drain electrode of the 5th PMOS are connected.

Described input second branch road comprises circuit connection: first, second, third, fourth, the 5th and the 6th NMOS tube;

The grid of described first NMOS tube connects anode input signal;

The grid of described second NMOS tube connects negative terminal input signal;

Be connected with the drain electrode of the 3rd NMOS tube after the source electrode of described first NMOS tube is connected with the source electrode of the second NMOS tube;

Be connected with the source electrode of the first NMOS tube after the source electrode of the drain electrode of described 3rd NMOS tube, the drain electrode of the 5th NMOS tube and the 6th NMOS tube connects;

The source electrode of the source electrode of described 3rd NMOS tube, the source electrode of the 4th NMOS tube and the 5th NMOS tube connects ground voltage respectively;

The grid of described 3rd NMOS tube and the grid of the 6th NMOS tube connect the second bias voltage respectively;

Be connected with the drain electrode of the 6th PMOS after the drain electrode connection of the grid of described 4th NMOS tube, the grid of the 5th NMOS tube and the 4th NMOS tube;

The drain electrode of described 6th NMOS tube is connected with the drain electrode of the 5th PMOS.

Described one-level first branch road comprises the 8th, the 9th, the tenth, the 11 and the 12 PMOS; The 7th outside PMOS provides bias voltage for one-level first branch road;

The source electrode of described 7th PMOS, the source electrode of the 9th PMOS and the source electrode of the 12 PMOS connect supply voltage respectively;

The grid of described 7th PMOS, the drain electrode of the 7th PMOS, the 8th, the tenth and the 11 the grid of PMOS be connected with ground voltage respectively;

Be connected with the drain electrode of the second NMOS tube after the source electrode of described 8th PMOS and the drain electrode of the 9th PMOS connect;

The grid of described 9th PMOS is connected with the grid of the 12 PMOS;

Be connected with the drain electrode of the first NMOS tube after the drain electrode connection of the described source electrode of the tenth PMOS, the source electrode of the 11 PMOS and the 12 PMOS.

Described one-level second branch road comprises the 8th, the 9th, the tenth, the 11 and the 12 NMOS tube; The 8th outside NMOS tube provides bias voltage for one-level second branch road;

The source electrode of described 7th NMOS tube, the source electrode of the 9th PMOS and the source electrode of the 12 PMOS connect ground voltage respectively;

The grid of the grid of described 7th NMOS tube, the drain electrode of the 7th NMOS tube, the 8th NMOS tube, the grid of the tenth NMOS tube and the grid of the 11 NMOS tube are connected with supply voltage respectively;

Be connected with the drain electrode of the second PMOS after the source electrode of described 8th NMOS tube and the drain electrode of the 9th NMOS tube connect;

Be connected with the drain electrode of the 8th PMOS after the grid of the drain electrode of described 8th NMOS tube, the grid of the 9th NMOS tube and the 12 NMOS tube connects;

Be connected with the drain electrode of the first PMOS after the drain electrode connection of the described source electrode of the tenth NMOS tube, the source electrode of the 11 NMOS tube and the 12 NMOS tube;

The drain electrode of described 11 NMOS tube is connected with the drain electrode of the 11 PMOS.

Described voltage reduction module comprises the 17 NMOS tube, and the source electrode of described 17 NMOS tube is connected with the drain electrode of the tenth NMOS tube, and the drain electrode of described 17 NMOS tube is connected with the drain electrode of the tenth PMOS, and the grid of described 17 NMOS tube is connected with supply voltage.

Described Class-AB control module comprises the 13, the 14 and the 15 PMOS, the 13, the 14 and the 15 NMOS tube;

The source electrode of described 13 PMOS and the source electrode of the 15 PMOS connect supply voltage;

The drain electrode of described 13 PMOS is connected with the source electrode of the 14 PMOS;

The described grid of the 13 PMOS is connected with draining with the grid of the 15 PMOS;

The drain electrode of described 14 PMOS is connected with the drain electrode of the 15 NMOS tube, the grid of the 15 NMOS tube and the grid of the 11 NMOS tube;

The described source electrode of the 13 NMOS tube is connected with ground voltage with the source electrode of the 15 NMOS tube;

The drain electrode of described 13 NMOS tube is connected with the source electrode of the 14 NMOS tube;

The drain electrode of described 14 NMOS tube is connected with the drain electrode of the 15 PMOS;

The grid of described 14 NMOS tube is connected with the drain electrode of the 7th NMOS tube.

Described second level output module comprises the 16 PMOS, the 16 NMOS tube, the first electric capacity and the second electric capacity;

The source electrode of described 16 PMOS connects supply voltage;

The source electrode of described 16 NMOS tube connects ground voltage;

The drain electrode of described 16 PMOS is connected with the drain electrode of the 16 NMOS tube;

The drain electrode of the grid of described 16 PMOS and the grid of the 14 PMOS, the drain electrode of the 17 NMOS tube and the tenth PMOS is connected;

The grid of described 16 NMOS tube is connected with the drain electrode of the 11 PMOS, the drain electrode of the 11 NMOS tube and the grid of the 13 NMOS tube;

The two ends of described first electric capacity are connected with draining with the grid of the 16 PMOS respectively;

The two ends of described second electric capacity are connected with draining with the grid of the 16 NMOS tube respectively.

The utility model compared with prior art, has the following advantages:

1, the problem of rail-to-rail amplifier gain decline in case of high pressures and DC maladjustment increase is efficiently solved;

2, complexity and the power consumption of circuit is not increased.

Accompanying drawing explanation

The rail-to-rail operational amplifier configuration figure that Fig. 1 is traditional;

The rail-to-rail operational amplifier configuration figure that can normally work under the follow-on low voltage situations of Fig. 2;

Fig. 3 MOSFET affects by ionization, leakage-substrate equivalence controlled current flow;

The spurious impedance of Fig. 4 leakage-substrate is along with the change of temperature and source and drain terminal voltage difference;

Fig. 5 source and drain terminal voltage difference is on the impact of amplifier DC maladjustment;

Fig. 6 is the theory diagram of the rail-to-rail operational amplifier of the wide amplitude of oscillation of the utility model;

Fig. 7 is the circuit theory diagrams of the rail-to-rail operational amplifier of the wide amplitude of oscillation of the utility model;

Fig. 8 in circuit theory diagrams shown in Fig. 7 with or without M _n16the comparison of amplifier gain.

Embodiment

Below in conjunction with accompanying drawing, by describing a preferably specific embodiment in detail, the utility model is further elaborated.

As shown in Figure 6, the rail-to-rail operational amplifier of a kind of wide amplitude of oscillation, comprises: voltage input module, first order output module, voltage reduction module, Class-AB control module, second level output module.Wherein, the input of voltage input module is connected with source voltage signal, and converts voltage signal to current signal; The input of first order output module is connected with the output of voltage input module; Voltage reduction module is connected with the output of voltage input module and the input of first order output module respectively; Class-AB control module is connected with first order output module, controls the output of first order output module, realizes rail-to-rail output; Second level output module is connected with first order output module, first order output module provides bias voltage for second level output module, namely described first order output module converts the current signal that voltage input module produces to voltage signal, for controlling the output voltage of second level output module, realizing push-pull type and exporting.

Voltage input module comprises input first branch road and input second branch road of circuit connection, first order output module comprises one-level first branch road and one-level second branch road of circuit connection, wherein, input the first branch road to be connected with one-level first branch road, input the first branch road and one-level first branch road and comprise the PMOS that several circuit are connected respectively; Input the second branch road to be then connected with one-level second branch road, input the second branch road and one-level second branch road and comprise the NMOS tube that several circuit are connected.

In the present invention, provide a kind of preferred circuit structure, as shown in Figure 7, specific as follows:

Input the first branch road comprise circuit connect: first, second, third, fourth, the 5th and the 6th PMOS; First PMOS M _p0grid connect anode input signal V _ip; Second PMOS M _p1grid connect negative terminal input signal V _in; First PMOS M _p0, the second PMOS M _p1and the 6th PMOS M _p5source electrode and the 3rd PMOS M _p2, the 4th PMOS M _p3drain electrode be connected; 3rd PMOS M _p2, the 4th PMOS M _p3and the 5th PMOS M _p4source electrode connect supply voltage; 3rd PMOS M _p2, the 6th PMOS M _p5grid connect the first bias voltage V respectively _p1; 4th PMOS M _p3, the 5th PMOS M _p4grid and the 5th PMOS M _p4drain electrode be connected.

Input the second branch road comprise circuit connect: first, second, third, fourth, the 5th and the 6th NMOS tube; First NMOS tube M _n0grid connect anode input signal; Second NMOS tube M _n1grid connect negative terminal input signal; First NMOS tube M _n0source electrode and the second NMOS tube M _n1source electrode connect after with the 3rd NMOS tube M _n2drain electrode be connected; 3rd NMOS tube M _n2drain electrode, the 5th NMOS tube M _n4drain electrode and the 6th NMOS tube M _n5source electrode connect after with the first NMOS tube M _n0source electrode connect; 3rd NMOS tube M _n2source electrode, the 4th NMOS tube M _n3source electrode and the 5th NMOS tube M _n4source electrode connect ground voltage respectively; 3rd NMOS tube M _n2grid and the 6th NMOS tube M _n5grid connect the second bias voltage V respectively _n1; 4th NMOS tube M _n3grid, the 5th NMOS tube M _n4grid and the 4th NMOS tube M _n3drain electrode connect after with the 6th PMOS M _p5drain electrode connect; 6th NMOS tube M _n5drain electrode and the 5th PMOS M _p4drain electrode connect.

One-level first branch road comprises the 8th, the 9th, the tenth, the 11 and the 12 PMOS, the 7th outside PMOS provides bias voltage for one-level first branch road; 7th PMOS M _p6source electrode, the 9th PMOS M _p8source electrode and the 12 PMOS M _p11source electrode connect supply voltage respectively; 7th PMOS M _p6grid, the 7th PMOS M _p6drain electrode, the 8th PMOS M _p7, the tenth PMOS M _p9and the 11 PMOS M _p10grid be connected with ground voltage respectively; 8th PMOS M _p7source electrode and the 9th PMOS M _p8drain electrode connect after with the second NMOS tube M _n1drain electrode connect; 9th PMOS M _p8grid and the 12 PMOS M _p1grid connect; Tenth PMOS M _p9source electrode, the 11 PMOS M _p10source electrode and the 12 PMOS M _p11drain electrode connect after with the first NMOS tube M _n0drain electrode connect.

One-level second branch road comprises the 8th, the 9th, the tenth, the 11 and the 12 NMOS tube, the 7th outside NMOS tube provides bias voltage for one-level second branch road; 7th NMOS tube M _n6source electrode, the 9th PMOS M _p8source electrode and the 12 PMOS M _p11source electrode connect ground voltage respectively; 7th NMOS tube M _n6grid, the 7th NMOS tube M _n6drain electrode, the 8th NMOS tube M _n7grid, the tenth NMOS tube M _n9grid and the 11 NMOS M _n10the grid of pipe is connected with supply voltage respectively; 8th NMOS tube M _n7source electrode and the 9th NMOS tube M _n8drain electrode connect after with the second PMOS M _p1drain electrode connect; 8th NMOS tube M _n7drain electrode, the 9th NMOS tube M _n8grid and the 12 NMOS tube M _n11grid connect after with the 8th PMOS M _p7drain electrode connect; Tenth NMOS tube M _n9source electrode, the 11 NMOS tube M _n10source electrode and the 12 NMOS tube M _n11drain electrode connect after with the first PMOS M _p0drain electrode connect; 11 NMOS tube M _n10drain electrode and the 11 PMOS M _p10drain electrode connect.

Voltage reduction module comprises the 17 NMOS tube M _n16, the 17 NMOS tube M _n16source electrode and the tenth NMOS tube M _n9drain electrode be connected, the 17 NMOS tube M _n16drain electrode and the tenth PMOS M _p9drain electrode be connected, the 17 NMOS tube M _n16grid be connected with supply voltage.Known by emulating, as shown in Figure 5, when source and drain power-off pressure reduction is more than more than 3.5V time, between leakage-substrate, spurious impedance can have a huge impact DC maladjustment, the tenth NMOS tube M _n9source and drain terminal voltage be about the tenth NMOS tube M more than the DC maladjustment of 3.5V _n95 times time source and drain terminal voltage difference is 1V, so, when high pressure, due to the tenth NMOS tube M _n9source and drain terminal voltage difference is comparatively large, can cause the hydraulic performance decline of operational amplifier.Therefore, due to the 17 NMOS tube M _n16existence, make the tenth NMOS tube M _n9source and drain terminal voltage difference is:

V _ds，n9＝V _DD-V _GS·n16-V _DS·n11(6)

Wherein, V _{ds, n9}represent M _n9source-drain voltage; V _{gS, n16}represent M _n16gate source voltage; V _dDrepresent supply voltage; V _{dS, n11}represent M _n11source-drain voltage.

By rationally arranging V _gS.n16value, we can obtain in the gamut of full swing, V _{ds, n9}≤ 3.5V.Fig. 8 gives in ttcorner situation, whether adds Mn ₁₆time impact on gain: Mn16 exists, the gain of amplifier is 104.2dB; M _n16time non-existent, the gain of amplifier is 95.15dB.Therefore, effectively can be addressed this problem by its step-down, can ensure in the scope of full swing, the tenth NMOS tube M _n9source and drain terminal voltage difference is not more than 3.5V all the time, ensure that the gain of operational amplifier, and does not increase complexity and the power consumption of circuit.

Class-AB control module comprises the 13, the 14 and the 15 PMOS, the 13, the 14 and the 15 NMOS tube; 13 PMOS M _p12source electrode and the 15 PMOS M _p14source electrode connect supply voltage; 13 PMOS M _p12drain electrode and the 14 PMOS M _p13source electrode connect; 13 PMOS M _p12grid and the 15 PMOS M _p14grid with drain electrode be connected; 14 PMOS M _p13drain electrode and the 15 NMOS tube M _n14drain electrode, the 15 NMOS tube M _n14grid and the 11 NMOS tube M _n10grid be connected; 13 NMOS tube M _n12source electrode and the 15 NMOS tube M _n14source electrode be connected with ground voltage; 13 NMOS tube M _n12drain electrode and the 14 NMOS tube M _n13source electrode be connected; 14 NMOS tube M _n13drain electrode and the 15 PMOS M _p14drain electrode be connected; 14 NMOS tube M _n13grid and the 7th NMOS tube M _n6drain electrode be connected.

Second level output module comprises the 16 PMOS M _p15, the 16 NMOS tube M _n15, the first electric capacity C ₁and the second electric capacity C ₂; 16 PMOS M _p15source electrode connect supply voltage; 16 NMOS tube M _n15source electrode connect ground voltage; 16 PMOS M _p15drain electrode and the 16 NMOS tube M _n15drain electrode be connected; 16 PMOS M _p15grid and the 14 PMOS M _p13grid, the 17 NMOS tube M _n16drain electrode and the tenth PMOS M _p9drain electrode be connected; 16 NMOS tube M _n15grid and the 11 PMOS M _p10drain electrode, the 11 NMOS tube M _n10drain electrode and the 13 NMOS tube M _n12grid be connected; First electric capacity C ₁two ends respectively with the 16 PMOS M _p15grid with drain electrode be connected; Second electric capacity C ₂two ends respectively with the 16 NMOS tube M _n15grid with drain electrode be connected.

In sum, the rail-to-rail operational amplifier of the wide amplitude of oscillation of the utility model, efficiently solves the problem of rail-to-rail amplifier gain decline in case of high pressures and DC maladjustment increase, and does not increase complexity and the power consumption of circuit.

Although content of the present utility model has done detailed introduction by above preferred embodiment, will be appreciated that above-mentioned description should not be considered to restriction of the present utility model.After those skilled in the art have read foregoing, for multiple amendment of the present utility model and substitute will be all apparent.Therefore, protection range of the present utility model should be limited to the appended claims.

Claims (10)

1. the rail-to-rail operational amplifier of the wide amplitude of oscillation, is characterized in that, comprise:

Voltage input module, the input of described voltage input module is connected with source voltage signal, and converts voltage signal to current signal;

First order output module, the input of described first order output module is connected with the output of voltage input module;

Voltage reduction module, described voltage reduction module is connected with the output of voltage input module and the input of first order output module respectively;

Class-AB control module, described Class-AB control module is connected with first order output module, controls the output of first order output module, realizes rail-to-rail output;

Second level output module, described second level output module is connected with first order output module, and described first order output module provides bias voltage for second level output module, realizes push-pull type and exports.

2. the rail-to-rail operational amplifier of the wide amplitude of oscillation as claimed in claim 1, it is characterized in that, described voltage input module comprises input first branch road and input second branch road of circuit connection, described first order output module comprises one-level first branch road and one-level second branch road of circuit connection, described input first branch road is connected with one-level first branch road, and described input second branch road is connected with one-level second branch road.

3. the rail-to-rail operational amplifier of the wide amplitude of oscillation as claimed in claim 2, it is characterized in that, described input first branch road and one-level first branch road comprise the PMOS that several circuit are connected respectively; Described input second branch road and one-level second branch road comprise the NMOS tube that several circuit are connected.

4. the rail-to-rail operational amplifier of the wide amplitude of oscillation as claimed in claim 3, is characterized in that, described input first branch road comprises that circuit connects: first, second, third, fourth, the 5th and the 6th PMOS;

The grid of described first PMOS connects anode input signal;

The grid of described second PMOS connects negative terminal input signal;

Described first, second and the source electrode and the 3rd of the 6th PMOS, the drain electrode of the 4th PMOS are connected;

The source electrode of described 3rd, the 4th and the 5th PMOS connects supply voltage;

The grid of described 3rd, the 6th PMOS connects the first bias voltage respectively;

The grid of described 4th, the 5th PMOS and the drain electrode of the 5th PMOS are connected.

5. the rail-to-rail operational amplifier of the wide amplitude of oscillation as claimed in claim 4, is characterized in that, described input second branch road comprises that circuit connects: first, second, third, fourth, the 5th and the 6th NMOS tube;

The grid of described first NMOS tube connects anode input signal;

The grid of described second NMOS tube connects negative terminal input signal;

Be connected with the drain electrode of the 3rd NMOS tube after the source electrode of described first NMOS tube is connected with the source electrode of the second NMOS tube;

Be connected with the source electrode of the first NMOS tube after the source electrode of the drain electrode of described 3rd NMOS tube, the drain electrode of the 5th NMOS tube and the 6th NMOS tube connects;

The source electrode of the source electrode of described 3rd NMOS tube, the source electrode of the 4th NMOS tube and the 5th NMOS tube connects ground voltage respectively;

The grid of described 3rd NMOS tube and the grid of the 6th NMOS tube connect the second bias voltage respectively;

Be connected with the drain electrode of the 6th PMOS after the drain electrode connection of the grid of described 4th NMOS tube, the grid of the 5th NMOS tube and the 4th NMOS tube;

The drain electrode of described 6th NMOS tube is connected with the drain electrode of the 5th PMOS.

6. the rail-to-rail operational amplifier of the wide amplitude of oscillation as claimed in claim 5, is characterized in that, described one-level first branch road comprises the 8th, the 9th, the tenth, the 11 and the 12 PMOS; The 7th outside PMOS provides bias voltage for one-level first branch road;

The source electrode of described 7th PMOS, the source electrode of the 9th PMOS and the source electrode of the 12 PMOS connect supply voltage respectively;

The grid of described 7th PMOS, the drain electrode of the 7th PMOS, the 8th, the tenth and the 11 the grid of PMOS be connected with ground voltage respectively;

Be connected with the drain electrode of the second NMOS tube after the source electrode of described 8th PMOS and the drain electrode of the 9th PMOS connect;

The grid of described 9th PMOS is connected with the grid of the 12 PMOS;

Be connected with the drain electrode of the first NMOS tube after the drain electrode connection of the described source electrode of the tenth PMOS, the source electrode of the 11 PMOS and the 12 PMOS.

7. the rail-to-rail operational amplifier of the wide amplitude of oscillation as claimed in claim 6, is characterized in that, described one-level second branch road comprises the 8th, the 9th, the tenth, the 11 and the 12 NMOS tube; The 8th outside NMOS tube provides bias voltage for one-level second branch road;

The source electrode of described 7th NMOS tube, the source electrode of the 9th PMOS and the source electrode of the 12 PMOS connect ground voltage respectively;

The grid of the grid of described 7th NMOS tube, the drain electrode of the 7th NMOS tube, the 8th NMOS tube, the grid of the tenth NMOS tube and the grid of the 11 NMOS tube are connected with supply voltage respectively;

Be connected with the drain electrode of the second PMOS after the source electrode of described 8th NMOS tube and the drain electrode of the 9th NMOS tube connect;

Be connected with the drain electrode of the 8th PMOS after the grid of the drain electrode of described 8th NMOS tube, the grid of the 9th NMOS tube and the 12 NMOS tube connects;

Be connected with the drain electrode of the first PMOS after the drain electrode connection of the described source electrode of the tenth NMOS tube, the source electrode of the 11 NMOS tube and the 12 NMOS tube;

The drain electrode of described 11 NMOS tube is connected with the drain electrode of the 11 PMOS.

8. the rail-to-rail operational amplifier of the wide amplitude of oscillation as claimed in claim 7, it is characterized in that, described voltage reduction module comprises the 17 NMOS tube, the source electrode of described 17 NMOS tube is connected with the drain electrode of the tenth NMOS tube, the drain electrode of described 17 NMOS tube is connected with the drain electrode of the tenth PMOS, and the grid of described 17 NMOS tube is connected with supply voltage.

9. the rail-to-rail operational amplifier of the wide amplitude of oscillation as claimed in claim 8, is characterized in that, described Class-AB control module comprises the 13, the 14 and the 15 PMOS, the 13, the 14 and the 15 NMOS tube;

The source electrode of described 13 PMOS and the source electrode of the 15 PMOS connect supply voltage;

The drain electrode of described 13 PMOS is connected with the source electrode of the 14 PMOS;

The described grid of the 13 PMOS is connected with draining with the grid of the 15 PMOS;

The drain electrode of described 14 PMOS is connected with the drain electrode of the 15 NMOS tube, the grid of the 15 NMOS tube and the grid of the 11 NMOS tube;

The described source electrode of the 13 NMOS tube is connected with ground voltage with the source electrode of the 15 NMOS tube;

The drain electrode of described 13 NMOS tube is connected with the source electrode of the 14 NMOS tube;

The drain electrode of described 14 NMOS tube is connected with the drain electrode of the 15 PMOS;

The grid of described 14 NMOS tube is connected with the drain electrode of the 7th NMOS tube.

10. the rail-to-rail operational amplifier of the wide amplitude of oscillation as claimed in claim 9, it is characterized in that, described second level output module comprises the 16 PMOS, the 16 NMOS tube, the first electric capacity and the second electric capacity;

The source electrode of described 16 PMOS connects supply voltage;

The source electrode of described 16 NMOS tube connects ground voltage;

The drain electrode of described 16 PMOS is connected with the drain electrode of the 16 NMOS tube;

The drain electrode of the grid of described 16 PMOS and the grid of the 14 PMOS, the drain electrode of the 17 NMOS tube and the tenth PMOS is connected;

The grid of described 16 NMOS tube is connected with the drain electrode of the 11 PMOS, the drain electrode of the 11 NMOS tube and the grid of the 13 NMOS tube;

The two ends of described first electric capacity are connected with draining with the grid of the 16 PMOS respectively;

The two ends of described second electric capacity are connected with draining with the grid of the 16 NMOS tube respectively.