CN106469677B - 具有双晶界的互连结构及其形成方法 - Google Patents
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- CN106469677B CN106469677B CN201610674152.9A CN201610674152A CN106469677B CN 106469677 B CN106469677 B CN 106469677B CN 201610674152 A CN201610674152 A CN 201610674152A CN 106469677 B CN106469677 B CN 106469677B
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- conductive material
- twin boundary
- diffusion barrier
- barrier layer
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- 238000000034 method Methods 0.000 title claims abstract description 64
- 239000004065 semiconductor Substances 0.000 claims abstract description 75
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 239000004020 conductor Substances 0.000 claims description 105
- 230000004888 barrier function Effects 0.000 claims description 61
- 238000009792 diffusion process Methods 0.000 claims description 61
- 239000000463 material Substances 0.000 claims description 31
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 18
- 239000010941 cobalt Substances 0.000 claims description 16
- 229910017052 cobalt Inorganic materials 0.000 claims description 16
- 238000005516 engineering process Methods 0.000 claims description 11
- -1 cobalt nitride Chemical class 0.000 claims description 9
- 238000004070 electrodeposition Methods 0.000 claims description 7
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 229910052707 ruthenium Inorganic materials 0.000 claims description 6
- 239000002305 electric material Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 115
- 239000010949 copper Substances 0.000 description 18
- 230000005012 migration Effects 0.000 description 18
- 238000013508 migration Methods 0.000 description 18
- 230000015572 biosynthetic process Effects 0.000 description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 15
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 11
- 230000008569 process Effects 0.000 description 11
- 239000011248 coating agent Substances 0.000 description 9
- 238000000576 coating method Methods 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 9
- 238000005530 etching Methods 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 239000003989 dielectric material Substances 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 7
- 230000008859 change Effects 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 239000013078 crystal Substances 0.000 description 5
- 230000009977 dual effect Effects 0.000 description 5
- 230000005611 electricity Effects 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 230000007547 defect Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 229910003978 SiClx Inorganic materials 0.000 description 3
- 229910020776 SixNy Inorganic materials 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 239000003792 electrolyte Substances 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000007517 polishing process Methods 0.000 description 3
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 3
- 239000004810 polytetrafluoroethylene Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000003321 amplification Effects 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000033001 locomotion Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229920000090 poly(aryl ether) Polymers 0.000 description 2
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 2
- 238000011112 process operation Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910001316 Ag alloy Inorganic materials 0.000 description 1
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910000906 Bronze Inorganic materials 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910000807 Ga alloy Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910001362 Ta alloys Inorganic materials 0.000 description 1
- 239000004809 Teflon Substances 0.000 description 1
- 229920006362 Teflon® Polymers 0.000 description 1
- 229910001069 Ti alloy Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910001080 W alloy Inorganic materials 0.000 description 1
- CPJYFACXEHYLFS-UHFFFAOYSA-N [B].[W].[Co] Chemical compound [B].[W].[Co] CPJYFACXEHYLFS-UHFFFAOYSA-N 0.000 description 1
- FEBFYWHXKVOHDI-UHFFFAOYSA-N [Co].[P][W] Chemical compound [Co].[P][W] FEBFYWHXKVOHDI-UHFFFAOYSA-N 0.000 description 1
- DUFGEJIQSSMEIU-UHFFFAOYSA-N [N].[Si]=O Chemical compound [N].[Si]=O DUFGEJIQSSMEIU-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 210000001367 artery Anatomy 0.000 description 1
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- QDWJUBJKEHXSMT-UHFFFAOYSA-N boranylidynenickel Chemical compound [Ni]#B QDWJUBJKEHXSMT-UHFFFAOYSA-N 0.000 description 1
- IGLTYURFTAWDMX-UHFFFAOYSA-N boranylidynetungsten nickel Chemical compound [Ni].B#[W] IGLTYURFTAWDMX-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000011010 flushing procedure Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000002706 hydrostatic effect Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- CSJDCSCTVDEHRN-UHFFFAOYSA-N methane;molecular oxygen Chemical compound C.O=O CSJDCSCTVDEHRN-UHFFFAOYSA-N 0.000 description 1
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 230000001617 migratory effect Effects 0.000 description 1
- DOTMOQHOJINYBL-UHFFFAOYSA-N molecular nitrogen;molecular oxygen Chemical compound N#N.O=O DOTMOQHOJINYBL-UHFFFAOYSA-N 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 229920000052 poly(p-xylylene) Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 210000003462 vein Anatomy 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
- H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Abstract
本发明提供了一种具有双晶界的半导体器件结构及其形成方法。半导体器件结构包括衬底和在衬底上方形成的导电结构。导电结构包括双晶界,并且双晶界的密度在约25μm‑1至约250μm‑1的范围中。
Description
技术领域
本发明总体涉及半导体领域,更具体地,涉及互连结构及其形成方法。
背景技术
半导体器件被用于诸如个人电脑、手机、数码相机和其他电子设备的多种电子应用中。半导体器件通常通过以下步骤来制造:在半导体衬底上方依次沉积绝缘或介电层、导电层和半导体材料层;使用光刻来图案化多个材料层,以在其上形成电路部件和元件。许多集成电路通常制造在单个半导体晶圆上,并且通过沿着划线在集成电路之间锯切来分割晶圆上的单独的管芯。通常,单独的管芯以例如多管芯模块或以其他封装类型来被分别封装。
为了增大器件密度,在制造工艺中不断减小半导体器件的尺寸。相应地,提供了多层互连结构。互连结构可以包括一个或多个导线和通孔层。
虽然现有的互连结构和制造互连结构的方法对于它们的预期目的通常已经足够,但是它们不是在所有方面都已完全令人满意。
发明内容
根据本发明的一个方面,提供了一种半导体器件结构,包括:衬底;以及导电结构,形成在所述衬底上方,其中,所述导电结构包括双晶界,以及所述双晶界的密度在约25μm-1至约250μm-1的范围中。
优选地,所述双晶界的平均双层片宽度在约4nm至约40nm的范围中。
优选地,所述导电结构包括:扩散阻挡层;以及导电材料,形成在所述扩散阻挡层上方。
优选地,所述扩散阻挡层的晶格常数与所述导电材料的晶格常数之间的晶格失配率在约0.1%到约6%的范围中。
优选地,该半导体器件结构还包括:胶层,在所述扩散阻挡层和所述导电材料之间形成,其中,所述胶层的晶格常数与所述导电材料的晶格常数之间的晶格失配率在约0.1%至约6%的范围中。
优选地,所述扩散阻挡层是由钌(Ru)、镍(Ni)、α-钴(Co)、β-钴(CO)、氮化钴(Co4N)或它们的组合制成的。
优选地,该半导体器件结构还包括:沟槽-通孔结构,形成在所述导电材料上方,其中,所述沟槽-通孔结构包括双晶界,并且所述双晶界的密度在约25μm-1至约250μm-1的范围中。
优选地,该半导体器件结构还包括:器件元件,形成在所述衬底中;以及介电层,形成在所述器件元件上方,其中,所述导电结构电连接至所述器件元件。
根据本发明的另一方面,提供了一种半导体器件结构,包括:第一介电层,形成在衬底上方;扩散阻挡层,形成在所述第一介电层中;以及导电材料,形成在所述扩散阻挡层上方,其中,所述扩散阻挡层的晶格常数与所述导电材料的晶格常数之间的晶格失配率在约0.1%到约6%的范围中。
优选地,所述导电结构包括双晶界,以及所述双晶界的密度在约25μm-1至约250μm-1的范围中。
优选地,所述双晶界的平均双层片宽度在约4nm至约40nm的范围中。
优选地,所述扩散阻挡层是由钌(Ru)、镍(Ni)、α-钴(Co)、β-钴(CO)、氮化钴(Co4N)或它们的组合制成的。
优选地,该半导体器件结构还包括:胶层,形成在所述扩散阻挡层和所述导电材料之间,其中,所述胶层的晶格常数与所述导电材料的晶格常数之间的晶格失配率在约0.1%至约6%的范围中。
优选地,该半导体器件结构还包括:沟槽-通孔结构,形成在所述导电材料上方,其中,所述沟槽-通孔结构包括双晶界,以及所述双晶界的密度在约25μm-1至约250μm-1的范围中。
根据本发明的又一方面,提供了一种形成半导体器件结构的方法,包括:提供衬底;以及在所述衬底上方形成导电结构,其中,所述导电结构包括双晶界,以及所述双晶界的密度在约25μm-1至约250μm-1的范围中。
优选地,在所述衬底上方形成所述半导体器件结构包括:通过脉冲电流的方法来执行电沉积工艺。
优选地,所述电沉积工艺操作在约-5度至约5度范围的温度下执行。
优选地,在所述衬底上方形成所述导电结构包括:形成扩散阻挡层;以及
在所述扩散阻挡层上方形成导电材料,其中,所述扩散阻挡层的晶格常数与所述导电材料的晶格常数之间的晶格失配率在约0.1%至约6%的范围中。
优选地,该方法还包括:在所述扩散阻挡层和所述导电材料之间形成胶层,其中,所述胶层的晶格常数与所述导电材料的晶格常数之间的晶格失配率在约0.1%至约6%的范围中。
优选地,该方法还包括:在所述导电结构上方形成沟槽-通孔结构,其中,所述沟槽-通孔结构包括双晶界,以及所述双晶界的密度在约25μm-1至约250μm-1的范围中。
附图说明
当结合附图进行阅读时,根据下面详细的描述可以最佳地理解本发明的各个方面。应该注意,根据工业中的标准实践,各种部件没有被按比例绘制。实际上,为了清楚的讨论,各种部件的尺寸可以被任意地增加或减少。
图1A至图1D示出了根据本发明的一些实施例的形成半导体器件结构的各个阶段的截面示图。
图2示出了根据本发明的一些实施例的图1C的区域A的放大的示图。
图3A至图3B示出了根据本发明的一些实施例的半导体器件结构的截面示图。
图4A至图4C示出了根据本发明的一些实施例的形成半导体器件结构的各个阶段的截面示图。
图5A至图5B示出了根据本发明的一些实施例的形成半导体器件结构的各个阶段的截面示图。
图6示出了根据本发明的一些实施例的导电材料的双晶界的密度和原子迁移率(VTM/V0)的关系。
图7示出了根据本发明的一些实施例的导电材料的双晶界的双层片宽度和故障电流密度的关系。
图8A至图8B示出了具有双晶界(如实施例4标记)和没有双晶界(如实施例5标记)的导电材料电压和电流的关系
具体实施方式
以下公开内容提供了多种不同实施例或实例,用于实现所提供主题的不同特征。以下将描述组件和布置的具体实例以简化本发明。当然,这些仅是实例并且不意欲限制本发明。例如,在以下描述中,在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例,也可以包括形成在第一部件和第二部件之间的附加部件使得第一部件和第二部件不直接接触的实施例。而且,本发明在各个实例中可以重复参考数字和/或字母。这种重复仅是为了简明和清楚,其自身并不表示所论述的各个实施例和/或配置之间的关系。
描述了实施例的一些变化。在各个视图和说明性实施例中,类似的参考标号用于标示类似的元件。应该理解,可以在方法之前、期间和之后提供附加的操作,并且对于方法的其他实施例,可以代替或消除描述的一些操作。
提供了半导体器件结构和用于形成半导体器件结构的方法的实施例。图1A至图1D示出了根据本发明的一些实施例的形成半导体器件结构100a的各个阶段的截面示图。
参考图1A,提供了衬底102。衬底102可以由硅或其他半导体材料制成。可选地或额外地,衬底102可以包括诸如锗的其他元素半导体材料。在一些实施例中,衬底102是由诸如碳化硅、砷化镓、砷化铟或磷化铟的化合物半导体制成。在一些实施例中,衬底102是由诸如硅锗、碳化硅锗、磷砷化镓或磷铟化镓的合金半导体制成的。在一些实施例中,衬底102包括外延层。例如,该衬底102具有覆盖块状半导体的外延层。
半导体器件结构100a包括在衬底102上方的第一介电层110。在一些实施例中,第一介电层110是层间电介(ILD)层。第一介电层110由氧化硅(SiOx)、氮化硅(SixNy)或氮氧化硅(SiON)制成。
器件元件104形成在第一介电层110中。器件元件104包括晶体管(例如,金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极结型晶体管(BJT)、高压晶体管、高频晶体管、P-沟道和/或n-沟道场效应晶体管(PFET/NFET)等)、二极管和/或其他适用的元件。执行各种工艺(诸如,沉积、蚀刻、注入、光刻、退火和/或其他适用的工艺)以形成器件元件104。在一些实施例中,在前段制程(FEOL)工艺中,在衬底102中形成器件元件104。
衬底102可以包括诸如p-型阱或n-型阱的各个掺杂区域。掺杂区域可以掺杂有p-型掺杂剂(诸如硼或BF2)和/或n-型掺杂剂(诸如磷(P)或砷(As))。掺杂区域可以以p-阱结构、n-阱结构或双-阱结构直接在衬底102上形成。
衬底102还可以进一步包括诸如浅沟槽隔离(STI)部件或局部硅氧化(LOCOS)部件的隔离部件(未示出)。隔离部件可以限定和隔离各个器件元件。
在第一介电层110上方形成第二介电层120。在一些实施例中,第二介电层120是金属间介电(IMD)层。第二介电层120可以是单层或多层。第二介电层120由氧化硅(SiOx)、氮化硅(SixNy)、氮氧化硅(SiON)、具有低介电常数(低-k)的介电材料或它们的组合制成。
在一些实施例中,第二介电层120由具有小于约2.5的介电常数(k)的极低k(ELK)介电材料制成。由于随着技术节点发展至30nm及以下,几何尺寸缩小,ELK介电材料用于最小化器件RC(时间常数,R:电阻,C:电容)延迟。在一些实施例中,ELK介电材料包括掺杂碳的氧化硅、非晶氟化碳、聚对二甲苯、双苯并环丁烯(BCB)、聚四氟乙烯(PTFE)(特氟龙)或碳氧化硅聚合物(SiOC)。在一些实施例中,ELK介电材料包括多孔形式的现有的介电材料,诸如氢倍半硅氧烷(HSQ)、多孔甲基倍半硅氧烷(MSQ)、多孔聚芳醚(PAE)、多孔SiLK或多孔氧化硅(SiO2)。在一些实施例中,第二介电层120通过化学汽相沉积工艺(诸如等离子体增强化学汽相沉积,PECVD)或旋涂工艺沉积。
根据本发明的一些实施例,如图1B所示,在第二介电层120形成之后,沟槽122形成在第二介电层120中。沟槽122通过图案化工艺形成。图案化工艺包括光刻工艺和蚀刻工艺。光刻工艺包括软烘、掩模对准、曝光、曝光后烘焙、使光刻胶显影、冲洗和干燥(如,硬烘)。蚀刻工艺包括干蚀刻工艺或湿蚀刻工艺。
根据本发明的一些实施例,如图1C所示,在沟槽122形成之后,导电结构130形成在沟槽122中和第二介电层120的上方。导电结构130是互连结构的一部分。互连结构用于将器件元件104的信号电连接至外部器件(未显示)。导电结构130电连接至器件元件104。
示出的导电结构130仅仅是为了说明的目的。导电结构130可包括其他配置并可包括一个或多个导线和通孔层。
导电结构130包括扩散阻挡层132和导电材料134。扩散阻挡层132用于防止导电材料134扩散至相邻区域。第二介电层120、扩散阻挡层132和导电材料134在后段制程(BEOL)工艺中形成。
在一些实施例中,导电材料134由金属(诸如,铜(Cu)、铜合金、铝(Al)、铝合金、钨(W)、钨合金、钛(Ti)、钛合金、钽(Ta)或钽合金、银(Ag)或银合金,金(Au)或金合金)制成。在一些实施例中,当导电材料134是由铜(Cu)或铜基合金制成时,导电材料134具有改进的电阻值,从而使信号高速传播通过铜(Cu)互连件。
应该注意,导电结构130的迁移可以分为由直流引起的“电迁移(EM)”和由剩余应力引起的“应力迁移(SM)”,这些应力在形成多层布线时就已产生。“电迁移(EM)”和“应力迁移(SM)”是评估导电结构130的可靠性的两个因素。
术语“电迁移(EM)”可以指代基于在互连结构(如导电材料130)中的金属原子和在互连结构中的运动的电子之间的相互作用的扩散现象。具体地,电迁移(EM)是金属原子的迁移方向与电子的运动方向相同的现象。当发生EM时,金属原子的迁移会引起原子缺位或空洞或者引起小丘(hillock)。当形成这样的空洞时,导电材料的截面面积会减小,因此导电材料的电流密度会增大。电迁移(EM)会增大器件的电阻率,并且降低器件的性能。
当具有不同热膨胀系数的各种材料形成在互连结构中时,由于在不同的材料之间产生应力而出现“应力迁移”。形成空洞是受静水应力梯度驱动的空位迁移的结果。结果,一些小的空洞形成在互连结构中(诸如导电结构130)。这些小空洞可以共同形成一个大的空洞。大的空洞减少或消除各金属层之间的电接触。在另一个实例中,应力迁移(SM)由热循环和工艺变化(诸如退火不当、化学机械抛光(“CMP”)工艺、填充导电材料)引起。因此,应力迁移会引起各导电材料之间的电接触减少,这会引起电阻率增大以及导致器件故障。
随着半导体器件的几何尺寸继续缩小,电迁移(EM)和应力迁移(SM)的可靠性问题变得严重。为了提高电迁移(EM)可靠性和应力迁移(SM)可靠性,导电结构130包括高密度双边界,以抑制电迁移(EM)和应力迁移(SM)。
图2示出了根据本发明的一些实施例的图1C中的区域A的放大示图。导电结构130具有包括晶界210(实线显示)和双晶界220(虚线显示)的一些缺陷。双晶界220用于当电压被施加到导电结构130上时,延迟导电结构130的导电材料的原子的迁移。一旦导电材料的原子的迁移率被双晶界限制,电迁移(EM)就减小了,应力迁移(SM)也减小了。在一些实施例中,双晶界220的密度在约25μm-1至约250μm-1范围中。如果双晶界220的密度小于25μm-1,导电材料130的电迁移不可以减小。如果双晶界220的密度大于250μm-1,缺陷可能会过大,从而扩散阻挡层132和导电材料134之间的粘合会降低。双晶界220的密度由每单位长度双晶界220的数量来限定。在一些实施例中,双晶界220的密度由透射电子显微镜(TEM)来测量。
在一些实施例中,双晶界220具有在约4纳米至约40纳米的范围中的平均双层片宽度。如果双层片宽度小于4纳米,缺陷可能过大,从而扩散阻挡层132和导电材料134之间的粘合会劣化。如果双层片宽度大于40纳米,导电结构130的电迁移(EM)不能被有效地减小。
此外,当双晶界220的密度在上述的范围内时,导电材料134的电阻率可以保持。与没有双晶界的导电材料134相比,即便是导电材料134的缺陷增加,电阻率也不会改变。
双晶界220可以由两种工艺形成。第一工艺是接通时间(on-time)工艺,第二工艺是停止时间(off-time)工艺。接通时间工艺意味着双晶界220在形成导电材料134的期间建立,停止时间工艺意思是双晶界220在形成导电材料134之后建立。
在一些实施例中,导电材料134的双晶界220通过接通时间工艺形成。接通时间工艺包括通过脉冲电流方法执行电沉积工艺。衬底102和电极被设置在电解质中,并且电沉积工艺在受控的温度下进行。衬底102和电极分别用作阴极和阳极。然后,对衬底102施加脉冲电流,并且导电材料134沉积在扩散阻挡层132上。
在一些实施例中,电解质是一种硫酸铜溶液。在一些实施例中,电沉积工艺在约-5度至约5度的温度范围中操作。如果温度低于-5度,电解质会冻住。如果温度高于5度,可以形成多晶结构而不是双晶界220。在一些实施例中,脉冲电流具有在约0.4A/cm2至约1.8A/cm2范围中的电流密度。如果脉冲电流小于0.4A/cm2,双晶界220的密度可能会过小。如果脉冲电流大于1.8A/cm2,会形成多晶结构而不是双晶界220。在一些实施例中,脉冲电流操作的时间段在约0.02秒至约0.2秒范围内。如果时间段小于0.02秒,双晶界220可能不会形成。如果时间段大于0.2秒,双晶界220的密度可能会过小。
脉冲电流提高了在形成导电材料134期间堆垛层错的可能性。温度控制在上述的范围中以利于形成双晶界220的成核位置。
在其他一些实施例中,当导电材料134通过接通时间工艺形成的时候,扩散阻挡层132是由钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)、氮化钨(WN)以及它们的组合形成。
在其他一些实施例中,导电材料134的双晶界220通过停止时间工艺形成,扩散阻挡层132的材料用来引起双晶界220的形成。扩散阻挡层132和导电材料134由不同的材料形成,并且因此具有不同的晶格常数。在对导电结构130执行热退火工艺之后,扩散阻挡层132和导电材料134之间的晶格常数的不同会在导电材料134中引起缺一些陷。
如上所述,扩散阻挡层132和导电材料134之间的晶格常数的不同用来诱导在导电材料134中形成双晶界(或双结构)。在一些实施例中,扩散阻挡层132的晶格常数和导电材料134的晶格常数之间的晶格失配率的范围在约0.1%到约6%之间。如果晶格失配率小于0.1%,双晶界220的密度可能会过低。如果晶格失配率大于6%,扩散阻挡层132和导电材料134之间的粘合会降低。因此,可能会出现脱层问题。
在一些实施例中,当导电材料134是由具有面心立方(fcc)晶体结构的铜(Cu)组成时,扩散阻挡层132是由钌(Ru)、镍(Ni)、α-钴(Co)、β-钴(CO)、氮化钴(Co4N)或它们的组合形成的。在一些实施例中,扩散阻挡层132是双层结构,钽(Ta)和钌(Ru)依次形成于沟槽122中。
表1示出了不同材料的扩散阻挡层132的晶体结构和晶格常数。如表1所示,计算了铜(Cu)和各种材料的晶格常数之间的百分比差异。
表1
在一些实施例中,扩散阻挡层132通过物理汽相沉积(PVD)、化学汽相沉积(CVD)、原子层沉积(ALD)或其他合适的工艺制成。
在沉积扩散阻挡层132之后,导电材料134形成在扩散阻挡层132上方。之后,对导电结构130执行热退火工艺。在一些实施例中,热退火工艺操作的温度范围是在约150至约400度之间。如果温度低于150度,不能形成双晶界。如果温度高于400度,会劣化扩散阻挡层的质量。在一些实施例中,热退火工艺操作的时间段在约1分钟至约1小时的范围内。如果时间段小于1分钟,不能形成双晶界。如果时间段大于1小时,会劣化扩散阻挡层的质量。
根据本发明的一些实施例,如图1D所示,在形成导电材料134之后,对导电材料134执行抛光工艺。去除沟槽122外多余的材料。结果,导电材料134的顶面与第二介电层120的顶面齐平。在一些实施例中,抛光工艺是化学抛光工艺(CMP)。
然后,重复图1B至1D的工艺步骤,以制造多层双镶嵌金属互连结构(未显示)。当多层导电材料都有高的双晶界密度的时候,半导体器件结构的可靠性会进一步提高。
图3A到3B示出了根据本发明的一些实施例半导体器件结构100b的截面图。半导体器件结构100b与图1D所示的半导体器件结构100a类似或相同,除了胶层133形成在扩散阻挡层132上方。用于形成半导体结构100b的工艺和材料可以与用于形成半导体结构100a的工艺和材料类似或相同,因此在此处未重复。
如图3A所示,胶层133形成在扩散阻挡层132和导电材料134之间。胶层133用来提高扩散阻挡层132和导电材料134之间的粘合。
在一些实施例中,胶层133的晶格常数和导电材料134的晶格常数之间的晶格失配率在约0.1%至约6%的范围。当晶格失配率在上述的范围内,导电材料134的双晶界220会容易地形成。
然后,根据本发明的一些实施例,如图3B所示,去除导电材料134、胶层133和扩散阻挡层132的一部分。
图4A至图4C示出了根据本发明的一些实施例的形成半导体器件结构100c的各个阶段的截面示图。用于形成半导体结构100c的工艺和材料可以与用于形成半导体结构100a的工艺和材料类似或相同,因此在此处未重复。
如图4A所示,覆盖层410形成在导电材料134的上方。覆盖层410是介电覆盖层或金属覆盖层。在一些实施例中,介电覆盖层由氮化硅(如,SiN)、氮氧化硅(如,SiON)、碳化硅(例如,SiC)、碳氧化硅(如SiOC或SiCO)、碳氮化硅(如SiCN)、另一种适用的材料或它们的组合制成。在一些实施例中,金属介电层是由镍(Ni)、镍硼(NiB)、镍钨硼(NiWB)、钴(Co)、钴钨硼(CoWB)、钴钨磷(CoWP)、NiReP、其他适用的材料或其组合制成。
可以理解的是,各个介电覆盖层或金属覆盖层的化学计量根据化学汽相沉积(CVD)工艺的变化而变化的,包括反应物相对配比的改变以获得希望的薄膜压缩应力。
根据本发明的一些实施例,如图4B所示,在形成覆盖层410之后,蚀刻停止层420形成在覆盖层410和第二介电层120上方。
蚀刻停止层420可以是单层或多层。蚀刻停止层420由碳化硅(SiC)、氮化硅(SixNy)、碳氮化硅(SiCN)、碳氧化硅(SiOC)、氮碳氧化硅(SiOCN)、或其他适用的材料制成。在一些实施例中,蚀刻停止层420具有形成在碳化硅(SiC)层上的氧化硅(SiOx)层的双层结构。氧化硅(SiOx)层比碳化硅(SiC)层具有更好的防湿性。此外,SiC层用来提高下面的层和SiOx层的粘合。
在蚀刻停止层420形成之后,第三介电层430形成在蚀刻停止层420上方。在一些实施例中,第三介电层430与第二介电层120相同。在一些实施例中,第三介电层430由具有小于约2.5的介电常数(k)的极低-k(ELK)介电材料制成。随着由于技术节点发展至30nm及以下而导致的几何尺寸缩小,ELK介电材料用于最小化器件RC(时间常数,R:电阻,C:电容)延迟。
然后,用作双镶嵌腔的沟槽-通孔结构435形成在第三介电层430中。沟槽-通孔结构435包括通孔部分435a和第一沟槽孔435b。在一些实施例中,沟槽-通孔结构435由两次图案化-两次蚀刻(2P2E)工艺制成。
根据本发明的一些实施例,如图4C所示,在沟槽-通孔结构435形成之后,扩散阻挡层232和导电材料234顺序形成在沟槽-通孔结构435中。然后,对扩散阻挡层232和导电材料234执行抛光工艺以去除多余材料。扩散阻挡层232和导电材料234共同构成双镶嵌结构。
导电材料234包括双晶界以在不引起高电阻率的情况下提高电迁移(EM)的可靠性和应力迁移(SM)的可靠性。在一些实施例中,双晶界的双密度在约25μm-1至约250μm-1的范围中。在一些实施例中,双晶界的双层片宽度在约4nm至约40nm的范围中。
应该注意,导电材料234电连接至导电材料134,两者都具有高的双密度以减小电迁移(EM)和应力迁移(SM)。
图5A至图5B示出了根据本发明的一些实施例的形成半导体器件结构100d的各个阶段的截面示图。用于形成半导体结构100d的工艺和材料可以与用于形成半导体结构100a的工艺和材料类似或相同,因此在此处未重复。
如图5A所示,在导电部件134上方形成覆盖层410。在一些实施例中,覆盖层410是由金属或合金制成,并且它是由电镀工艺形成的。
然后,在覆盖层410上方形成蚀刻停止层420、第三介电层430。沟槽-通孔结构穿过第三介电层430、蚀刻停止层420和覆盖层430形成。然后,根据本发明的一些实施例,如图5B所示,扩散阻挡层232、胶层233和导电材料234形成在沟槽-通孔结构中。因此,得到了双镶嵌导电结构230。
图6示出了根据本发明的一些实施例的导电材料134的双晶界的密度与原子迁移率(VTM/V0)的关系。
图6所示的数据是通过原位透射电镜获得的。导电材料134是由铜(Cu)制成的。X轴示出了导电材料(例如导电材料134和234)的双晶界的密度。Y轴示出了具有双晶界的导电材料的迁移率(用VTM表示)与没有双晶界的材料的迁移率(用Vo表示)的比率。铜原子的迁移率被导电材料的每个双晶界延迟了两秒(标记为实施例1)、三秒(标记为实施例2)、五秒(标记为实施例3)。实施例1、2和3的导电材料是由铜(Cu)制成的。
如图6所示,随着由铜(Cu)制成的导电材料的双晶界的密度增加,导电材料的迁移率逐渐减小。当导电材料的双晶界密度是常数时,导电材料的迁移率随着迁移铜原子的延迟时间的增加而下降。换句话说,导电材料134的迁移率被双晶界减少。所以,当导电材料134的双晶界的密度范围在约25μm-1至约250μm-1的时候,电子迁移率(EM)有效地抑制了。所以,当导电材料由高密度双晶界形成的时候,互连结构的可靠性提高了。
图7示出了根据本发明的一些实施例的导电材料的双晶界的双层片宽度与故障电流密度的关系。
图7所示的数据是由TEM获得的双层片宽度(双晶界的间隔)。X轴示出了由铜(Cu)制成的导电材料的双层片宽度(诸如导电材料134和234)。X轴中的“no”表示导电材料没有双晶界。Y轴示出了故障电流密度,单位是108A/cm2。
如图7所示,随着导电材料的双晶界的双层片宽度减小,故障电流密度增加。换句话说,具有小双层片宽度的导电材料的双晶界具有更高的耐受电流。
图8A和图8B示出了具有双晶界(标记为实施例4)和没有双晶界(标记为实施例5)的导电材料的电压和电流的关系。
当电压施加到导电材料(诸如导电材料134和234),测量导电材料的电流。如图8A所示,实施例4具有比实施例5更高的耐受电流。
图8B中所示的两条线表示导电材料的电阻率。实施例4的斜率类似于实施例5的斜率。因此,实施例4的电阻率接近实施例5的电阻率,导电材料的原始性能的电阻率没有被双晶界改变。导电材料的双晶界提高了电迁移率(EM)的可靠性和应力迁移率(SM)的可靠性而没有引起高电阻率。
本发明提供了形成半导体器件结构和形成半导体器件结构的方法的实施例。半导体器件结构包括形成在衬底上方的互连结构。互连结构包括具有双晶界的导电材料。在一些实施例中,双晶界的双密度在从约25μm-1至约250μm-1的范围中。当电压施加到导电材料上的时,双晶界用来延迟导电结构的原子迁移率。所以,减小了电迁移(EM)和应力迁移(SM),并且提高了半导体器件结构的可靠性。
在一些实施例中,提供了半导体器件结构。半导体器件结构包括衬底和形成在衬底上方的导电结构。导电结构包括双晶界,并且双晶界的密度在从约25μm-1至约250μm-1的范围中。
在一些实施例中,提供了半导体器件结构。半导体器件结构包括形成在衬底上方的第一介电层和形成在第一介电层中的扩散阻挡层。半导体器件结构也包括形成在扩散阻挡层上方的导电材料。扩散阻挡层的晶格常数和导电材料的晶格常数之间的晶格失配率在约0.1%至约6%的范围中。
在一些实施例中,提供了形成一种半导体器件结构的方法。这种方法包括提供衬底并且在衬底上方形成导电结构。导电结构包括双晶界,双晶界的密度范围在约25μm-1至约250μm-1。
以上论述了若干实施例的部件,使得本领域的技术人员可以更好地理解本发明的各个方面。本领域技术人员应该理解,他们可以很容易地使用本发明作为基础来设计或更改其他用于达到与本文所介绍实施例相同的目的和/或实现相同优点的工艺和结构。本领域技术人员也应该意识到,这些等效结构并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,可以进行多种变化、替换以及改变。
Claims (19)
1.一种半导体器件结构,包括:
衬底;以及
导电结构,形成在所述衬底上方,其中,所述导电结构包括双晶界,以及所述双晶界的密度在25μm-1至250μm-1的范围中。
2.根据权利要求1所述的半导体器件结构,其中,所述双晶界的平均双层片宽度在4nm至40nm的范围中。
3.根据权利要求1所述的半导体器件结构,其中,所述导电结构包括:
扩散阻挡层;以及
导电材料,形成在所述扩散阻挡层上方。
4.根据权利要求3所述的半导体器件结构,其中,所述扩散阻挡层的晶格常数与所述导电材料的晶格常数之间的晶格失配率在0.1%到6%的范围中。
5.根据权利要求3所述的半导体器件结构,还包括:
胶层,在所述扩散阻挡层和所述导电材料之间形成,其中,所述胶层的晶格常数与所述导电材料的晶格常数之间的晶格失配率在0.1%至6%的范围中。
6.根据权利要求4所述的半导体器件结构,其中,所述扩散阻挡层是由钌(Ru)、镍(Ni)、α-钴(Co)、β-钴(CO)、氮化钴(Co4N)或它们的组合制成的。
7.根据权利要求1所述的半导体器件结构,还包括:
沟槽-通孔结构,形成在所述导电材料上方,其中,所述沟槽-通孔结构包括双晶界,并且所述双晶界的密度在25μm-1至250μm-1的范围中。
8.根据权利要求1所述的半导体器件结构,还包括:
器件元件,形成在所述衬底中;以及
介电层,形成在所述器件元件上方,其中,所述导电结构电连接至所述器件元件。
9.一种半导体器件结构,包括:
第一介电层,形成在衬底上方;
扩散阻挡层,形成在所述第一介电层中;以及
导电材料,形成在所述扩散阻挡层上方,其中,所述扩散阻挡层的晶格常数与所述导电材料的晶格常数之间的晶格失配率在0.1%到6%的范围中,所述扩散阻挡层和所述导电材料组成导电结构,所述导电结构包括双晶界,以及所述双晶界的密度在25μm-1至250μm-1的范围中。
10.根据权利要求9所述的半导体器件结构,其中,所述双晶界的平均双层片宽度在4nm至40nm的范围中。
11.根据权利要求9所述的半导体器件结构,其中,所述扩散阻挡层是由钌(Ru)、镍(Ni)、α-钴(Co)、β-钴(CO)、氮化钴(Co4N)或它们的组合制成的。
12.根据权利要求9所述的半导体器件结构,还包括:
胶层,形成在所述扩散阻挡层和所述导电材料之间,其中,所述胶层的晶格常数与所述导电材料的晶格常数之间的晶格失配率在0.1%至6%的范围中。
13.根据权利要求9所述的半导体器件结构,还包括:
沟槽-通孔结构,形成在所述导电材料上方,其中,所述沟槽-通孔结构包括双晶界,以及所述双晶界的密度在25μm-1至250μm-1的范围中。
14.一种形成半导体器件结构的方法,包括:
提供衬底;以及
在所述衬底上方形成导电结构,其中,所述导电结构包括双晶界,以及所述双晶界的密度在25μm-1至250μm-1的范围中。
15.根据权利要求14所述的形成半导体器件结构的方法,其中,在所述衬底上方形成所述半导体器件结构包括:
通过脉冲电流的方法来执行电沉积工艺。
16.根据权利要求15所述的形成半导体器件结构的方法,其中,所述电沉积工艺操作在-5度至5度范围的温度下执行。
17.根据权利要求14所述的形成半导体器件结构的方法,其中,在所述衬底上方形成所述导电结构包括:
形成扩散阻挡层;以及
在所述扩散阻挡层上方形成导电材料,其中,所述扩散阻挡层的晶格常数与所述导电材料的晶格常数之间的晶格失配率在0.1%至6%的范围中。
18.根据权利要求17所述的形成半导体器件结构的方法,还包括:
在所述扩散阻挡层和所述导电材料之间形成胶层,其中,所述胶层的晶格常数与所述导电材料的晶格常数之间的晶格失配率在0.1%至6%的范围中。
19.根据权利要求14所述的形成半导体器件结构的方法,还包括:
在所述导电结构上方形成沟槽-通孔结构,其中,所述沟槽-通孔结构包括双晶界,以及所述双晶界的密度在25μm-1至250μm-1的范围中。
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