CN106443220B - A kind of method and apparatus measuring measured device noise coefficient - Google Patents
A kind of method and apparatus measuring measured device noise coefficient Download PDFInfo
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- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/26—Measuring noise figure; Measuring signal-to-noise ratio
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Abstract
The embodiment of the invention discloses a kind of methods for measuring measured device noise coefficient, comprising: obtains the noise coefficient of measured device expanded circuit；The measured device expanded circuit includes measured device and measured device access, and the measured device access includes the first impedance matching network that any one input port of the measured device or any one output port is arranged in；Obtain the insertion loss of the measured device access；The insertion loss of noise coefficient and the measured device access based on the measured device expanded circuit, obtains the noise coefficient of the measured device.The embodiment of the invention also discloses a kind of devices for measuring measured device noise coefficient.
Description
Technical Field
The present invention relates to Noise Figure measurement technologies, and in particular, to a method and an apparatus for measuring Noise Figure (NF) of a Device Under Test (DUT).
Background
With the rapid development of mobile communication technology, the requirement for the measurement accuracy of the noise figure of the device under test is higher and higher. For some devices under test, such as radio frequency transceivers (RF transceivers), when measuring the noise figure of the device under test, it is usually necessary to provide an impedance matching network at each output port of the device under test, provide a test socket at the output end of the impedance matching network, and connect a noise figure measuring instrument with the test socket to complete the measurement of the noise figure of the device under test. However, in the above-mentioned technical solution for measuring the noise figure of the device under test, the impedance matching network may introduce insertion loss, so that the measured noise figure is not the noise figure of the device under test itself, and the accuracy of the noise figure measurement result is reduced.
Taking the device under test as an rf transceiver for example, fig. 1 is a schematic diagram of a circuit structure for measuring the noise figure of an rf transceiver in the prior art, as shown in fig. 1, the circuit for measuring the noise figure of an rf transceiver is located on a chip test board 100, and the circuit includes: the test system comprises a power supply module 101, a clock module 102, a state control module 103, an analog test socket 104, a radio frequency test socket 105, a test motherboard interface 106, a test point 107, a radio frequency transceiver 108 and an impedance matching network 109; wherein, the output port of the radio frequency transceiver 108 is connected with the radio frequency test seat 105 through the corresponding impedance matching network 109, and the butt joint with the noise coefficient measuring instrument can be realized on the radio frequency test seat; the radio frequency transceiver 108 has a plurality of output ports, which are illustrated as one output port in fig. 1. Specifically, the clock module 102 is used for providing an operating clock for the radio frequency transceiver; the state control module 103 is used for controlling the working state of the radio frequency transceiver; the power supply module 101 is used for respectively providing a working power supply for the radio frequency transceiver, the clock module and the state control module; the analog test socket 104 is used for providing an analog IQ signal to the rf transceiver or receiving an analog IQ signal from the rf transceiver; the radio frequency test socket 105 is used for providing radio frequency signals to the radio frequency transceiver or receiving radio frequency signals from the radio frequency transceiver, and the radio frequency test socket can be used for a noise coefficient measuring instrument; the test point 107 is connected to a pin of the rf transceiver for monitoring an operating status of the rf transceiver. The test motherboard interface 106 is used for completing the butt joint of the chip test board 100 and an FPGA motherboard, and the FPGA motherboard is used for providing an SPI signal and a baseband data processing function and ensuring that each device on the chip test board can work normally. In fig. 1, the circuit between the rf transceiver and the noise figure measuring apparatus affects the measurement result of the noise figure of the rf transceiver. Specifically, after the input/output port of the rf transceiver 108 is connected to the impedance matching network 109, the input/output port needs to be connected to the rf test socket 105 through a wire, and the impedance matching network causes insertion loss, thereby affecting the measurement result of the noise figure of the rf transceiver; in addition, when the number of input/output ports of the rf transceiver is large, based on the layout consideration of the circuit design, the routing between the impedance matching network and the rf test socket may be relatively long, which may cause a relatively large insertion loss, which may further affect the measurement result of the noise factor of the rf transceiver.
Disclosure of Invention
In order to solve the above technical problems, embodiments of the present invention desirably provide a method and an apparatus for measuring a noise coefficient of a device under test, which can improve accuracy of measuring the noise coefficient of the device under test.
The technical scheme of the invention is realized as follows:
the embodiment of the invention provides a method for measuring the noise coefficient of a tested device, which comprises the following steps:
acquiring a noise coefficient of a tested device expansion circuit; the device under test expansion circuit comprises a device under test and a device under test path, wherein the device under test path comprises a first impedance matching network arranged at any input port or any output port of the device under test;
obtaining the insertion loss of the device under test path;
and deriving the noise coefficient of the device under test based on the noise coefficient of the device under test expansion circuit and the insertion loss of the device under test path.
In the above solution, the first impedance matching network has a device under test port for connecting the device under test;
the obtaining insertion loss of the device under test path comprises: replicating the device under test path; setting an impedance matching network which forms conjugate matching or mirror symmetry with the first impedance matching network at the tested device port of the impedance matching network of the copied tested device path; obtaining an insertion loss of a cascade path, wherein the cascade path comprises a copied device under test path and an impedance matching network connected with the copied device under test path; deriving an insertion loss of the device under test path based on the insertion loss of the cascode path.
In the above scheme, the insertion loss of the device under test via is half of the insertion loss of the cascade via.
In the foregoing solution, when a device under test port of an impedance matching network of a duplicated device under test path is provided with an impedance matching network forming mirror symmetry with a first impedance matching network, the obtaining of the insertion loss of the cascade path includes:
measuring the insertion loss of a cascade path to obtain an initial value of the insertion loss of the cascade path; and obtaining the reflection loss of the cascade path, and subtracting the reflection loss of the cascade path from the initial value of the insertion loss of the cascade path to obtain the insertion loss of the cascade path.
In the above solution, the obtaining a noise figure of the dut expansion circuit includes: and deriving a gain and a noise power spectral density of the device under test extension circuit through measurement, and deriving a noise coefficient of the device under test extension circuit based on the measured gain and noise power spectral density of the device under test extension circuit.
In the above solution, the deriving the noise figure of the device under test based on the noise figure of the device under test expander circuit and the insertion loss of the device under test path includes: and subtracting the insertion loss of the tested device passage from the noise coefficient of the tested device expansion circuit to obtain the noise coefficient of the tested device.
The embodiment of the invention also provides a device for measuring the noise coefficient of the tested device, which comprises: the device comprises a first acquisition module, a second acquisition module and a calculation module; wherein,
the first acquisition module is used for acquiring the noise coefficient of the expansion circuit of the device under test; the device under test expansion circuit comprises a device under test and a device under test path, wherein the device under test path comprises a first impedance matching network arranged at any input port or any output port of the device under test;
a second obtaining module, configured to obtain an insertion loss of the device under test path;
a calculation module for deriving the noise figure of the device under test based on the noise figure of the device under test expander circuit and the insertion loss of the device under test path.
In the above solution, the first impedance matching network has a device under test port for connecting the device under test;
the second obtaining module is specifically configured to copy the device under test path; setting an impedance matching network which forms conjugate matching or mirror symmetry with the first impedance matching network at the tested device port of the impedance matching network of the copied tested device path; obtaining the insertion loss of a cascade path, wherein the cascade path comprises a copied tested device path and an impedance matching network connected with the copied tested device path; deriving an insertion loss of the device under test path based on the insertion loss of the cascode path.
In the above scheme, the second obtaining module is configured to measure the insertion loss of the cascade path when the copied impedance matching network of the device-under-test path is provided with an impedance matching network that forms mirror symmetry with the first impedance matching network, so as to obtain an initial value of the insertion loss of the cascade path; and obtaining the reflection loss of the cascade path, and subtracting the reflection loss of the cascade path from the initial value of the insertion loss of the cascade path to obtain the insertion loss of the cascade path.
In the above scheme, the calculating module is specifically configured to subtract the insertion loss of the device under test path from the noise coefficient of the device under test spreading circuit to obtain the noise coefficient of the device under test.
The embodiment of the invention provides a method and a device for measuring the noise coefficient of a tested device, which are used for obtaining the noise coefficient of an extended circuit of the tested device; obtaining the insertion loss of the device under test path; and deriving the noise coefficient of the device under test based on the noise coefficient of the device under test expansion circuit and the insertion loss of the device under test path. Therefore, the insertion loss of the channel of the device to be tested can be obtained, and the accuracy of measuring the noise coefficient of the device to be tested is further improved.
Drawings
FIG. 1 is a schematic diagram of a prior art circuit for measuring noise figure of a radio frequency transceiver;
FIG. 2 is a flow chart of a first embodiment of a method of measuring a noise figure of a device under test according to the present invention;
FIG. 3 is a schematic diagram illustrating the structure of an expander circuit of a device under test according to a first embodiment of the method for measuring the noise figure of the device under test of the present invention;
FIG. 4 is a flow chart of a first method for obtaining insertion loss of a path of a device under test according to a first embodiment of the method for measuring a noise figure of the device under test of the present invention;
FIG. 5 is a schematic diagram illustrating the structure of a first combinational path in the method for measuring the noise figure of a device under test according to the present invention;
FIG. 6 is a flow chart of a second method for obtaining insertion loss of a path of a device under test according to a first embodiment of the method for measuring a noise figure of the device under test of the present invention;
FIG. 7 is a schematic diagram illustrating the structure of a second combined path according to the first embodiment of the method for measuring the noise figure of a device under test;
FIG. 8 is a flowchart of a second embodiment of the method of measuring a noise figure of a device under test according to the present invention;
FIG. 9 is a schematic diagram of the structure of an apparatus for measuring the noise figure of a device under test according to an embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
First embodiment
FIG. 2 is a flow chart of a first embodiment of the method for measuring the noise figure of a device under test according to the present invention, as shown in FIG. 2, the method comprises:
step 200: the noise figure of the tested device expansion circuit is obtained.
Fig. 3 is a schematic diagram illustrating a structure of a device under test expansion circuit in a first embodiment of the method for measuring a noise figure of a device under test according to the present invention, and as shown in fig. 3, the device under test expansion circuit 300 includes a device under test 301 and a device under test path 302, and the device under test path 302 includes a first impedance matching network 303 disposed at any input port or any output port of the device under test 301.
Here, the device under test 301 may be a device such as a radio frequency transceiver, a radio frequency receiver, etc.; the device under test 301 has at least one output port and at least one input port; the device under test path 302 may also include a first test socket 304 connected to the first impedance matching network 301, and a trace between the first impedance matching network 303 and the first test socket 304, the first test socket 304 may be used to access a noise figure measurement instrument.
Here, the device under test expansion Circuit 300 may be located on a first Printed Circuit Board (PCB).
In this step, there are many existing implementations for obtaining the noise coefficient of the dut expansion circuit, for example, the noise coefficient of the dut expansion circuit can be measured by using a gain method and a Y-factor method.
The following illustrates the process of obtaining the noise figure of the device under test expander circuit.
The method for acquiring the noise coefficient of the device under test expansion circuit comprises the following steps: gain of the device under test expansion circuit and noise power spectral density P of the device under test expansion circuit are obtained through measurementNOUTThe noise factor NF of the rf transceiver extension circuit is obtained by the following formula:
NF＝PNOUT-(-174dBm/Hz+Gain)。
there are several existing implementations of measuring gain and noise power spectral density of the device under test expander circuit, and are not described in detail here.
In this step, the first impedance matching network may be a circuit in the form of a pure resistor, or may be a circuit including a reactance part; the first impedance matching network arranged at the input port of the device to be tested has the function of ensuring that a signal can be input into the device to be tested with the minimum loss, and the first impedance matching network arranged at the output port of the device to be tested has the function of ensuring that an output signal of the device to be tested can be sent out with the minimum loss; in order to make the first impedance matching network function correspondingly, before this step, a corresponding impedance matching network is set up at each input/output port of the device under test by debugging, and the setting of the first impedance matching network has a variety of existing implementations, which are not described in detail herein.
Here, the first impedance matching network 303 has two ports, one of which is a device under test port for connecting the device under test 301; the other port of the first impedance matching network 303 is a noise coefficient test port and is used for accessing a noise coefficient measuring instrument; further, the noise figure test port of the first impedance matching network 303 may access a noise figure measurement instrument through the first test socket 304.
Step 201: and acquiring the insertion loss of the channel of the device under test.
The obtaining insertion loss of the device under test path comprises: replicating the device under test path; setting an impedance matching network which forms conjugate matching or mirror symmetry with the first impedance matching network at the tested device port of the impedance matching network of the copied tested device path; obtaining the insertion loss of a cascade path, wherein the cascade path comprises a copied tested device path and an impedance matching network connected with the copied tested device path; deriving an insertion loss of the device under test path based on the insertion loss of the cascode path. Here, the insertion loss of the device-under-test path is half of the insertion loss of the cascade path.
Specifically, in this step, the insertion loss of the device under test via can be obtained by the following two methods.
The first method comprises the following steps:
fig. 4 is a flowchart of a first method for obtaining the insertion loss of the device under test path according to the first embodiment of the method for measuring the noise figure of the device under test of the present invention, as shown in fig. 4, the flowchart includes:
step 201A: and copying the channel of the device to be tested to obtain a first copied channel of the device to be tested. That is, the replicated device under test via is the first replicated device under test via.
Here, the device under test vias may be replicated on a second PCB, which has the same laminate structure as the first PCB.
In this step, only the device under test path is duplicated, and the device under test is not duplicated.
Step 201B: and arranging a second impedance matching network at the tested device port of the impedance matching network of the first copied tested device path, so that the impedance matching network in the copied tested device and the second impedance matching network form conjugate matching.
Specifically, the second impedance matching network and the impedance matching network in the first duplicated tested device path have a symmetrical circuit structure form on the second PCB, and the trace in the second impedance matching network and the trace of the impedance matching network in the first duplicated tested device path are symmetrical to each other. Here, the impedance matching network in the duplicated device under test and the second impedance matching network can realize impedance matching by adjusting parameters of the device of the second impedance matching network, and the process of adjusting the parameters of the device of the second impedance matching network has a variety of existing implementation manners, which is not described in detail here.
In this step, the impedance matching network and the second impedance matching network in the first replica tested device path satisfy the condition of conjugate matching; that is, for the impedance matching network in the second impedance matching network and the first replica device-under-test path, the real parts of the impedances of the two are equal, and the imaginary parts are opposite numbers.
In practical application, the second impedance matching network has two ports, one of the two ports is used for connecting the device under test port of the first duplicate device under test access, and the other port of the second impedance matching network is an insertion loss test port for accessing an insertion loss measuring instrument; the first copied device-under-test path is provided with two ports, wherein one port is a tested device port of the impedance matching network of the first copied device-under-test path and is used for connecting the second impedance matching network, and the other port of the first copied device-under-test path is an insertion loss test port and is used for accessing an insertion loss measuring instrument. Here, the insertion loss measuring instrument may be implemented using a vector network analyzer.
Step 201C: the insertion loss of the first combined path is obtained.
Fig. 5 is a schematic diagram illustrating a structure of a first combined path in a first embodiment of the method for measuring a noise figure of a device under test according to the present invention, as shown in fig. 5, the first combined path 500 includes a second impedance matching network 501 and a first duplicated device under test path 502, the first combined path 500 has two ports, one of the two ports is an insertion loss test port of the second impedance matching network 501 for accessing an insertion loss measurement instrument; the other port of the first combined path 500 is an insertion loss test port of the first duplicate device-under-test path 502 for accessing an insertion loss measurement instrument. Here, the cascade path is the first combined path 500.
In practical application, the insertion loss of the first combined path may be measured by an insertion loss measuring instrument such as a vector network analyzer, so as to obtain the insertion loss of the first combined path.
In addition, when the insertion loss of the first combined path is measured, the insertion loss of the first combined path can be obtained by measuring the S21 parameter of the first combined path.
Further, the first combined path 500 further includes a second test socket 503 connected to the insertion loss test port of the second impedance matching network 501, and a trace between the second impedance matching network 501 and the second test socket 503, where the second test socket 503 is used to access an insertion loss measurement instrument.
Here, the trace between the impedance matching network in the first duplicated device under test via 502 and the insertion loss test port of the first duplicated device under test via 502 is denoted as a first trace structure, the trace between the second impedance matching network 501 and the second test socket 503 is denoted as a second trace structure, and the first trace structure and the second trace structure are symmetrical to each other on the second PCB.
Step 201D: deriving an insertion loss of the device under test path based on the insertion loss of the first combined path, the insertion loss of the device under test path A1 being: a1 is S21/2, and S21 represents the insertion loss of the first combined path obtained in step 201C.
The second method comprises the following steps:
fig. 6 is a flowchart of a method for measuring a noise figure of a device under test according to a first embodiment of the present invention, which uses a second method to obtain an insertion loss of a path of the device under test, as shown in fig. 6, the flowchart includes:
step 201 a: and copying the channel of the device to be tested to obtain a second copied channel of the device to be tested. That is, the replicated device under test via is the second replicated device under test via.
Here, the device under test vias may be replicated on a third PCB, which has the same laminate structure as the first PCB.
In this step, only the device under test path is duplicated, and the device under test is not duplicated.
Step 201 b: and arranging a third impedance matching network at the tested device port of the impedance matching network of the second copied tested device channel, wherein the circuit structure of the third impedance matching network is in mirror symmetry with the circuit structure of the impedance matching network of the second copied tested device channel.
Here, each device of the third impedance matching network employs the same device as its own symmetric device.
In practical application, the third impedance matching network has two ports, one of the two ports is used for connecting the device under test port of the second duplicate device under test access, and the other port of the third impedance matching network is an insertion loss test port for accessing an insertion loss measuring instrument; the second copied device-under-test path has two ports, wherein one port is a device-under-test port of the impedance matching network of the second copied device-under-test path and is used for connecting a third impedance matching network, and the other port of the second copied device-under-test path is an insertion loss test port and is used for accessing an insertion loss measuring instrument. Here, the insertion loss measuring instrument may be implemented using a vector network analyzer.
Step 201 c: obtaining the insertion loss of the second combined path;
fig. 7 is a schematic diagram illustrating a structure of a second combined path in the first embodiment of the method for measuring a noise figure of a device under test of the present invention, as shown in fig. 7, the second combined path 700 includes a third impedance matching network 701 and a second duplicate device under test path 702, the second combined path 700 has two ports, one of the two ports is an insertion loss test port of the third impedance matching network 701 for accessing an insertion loss measurement instrument; the other port of the second combined path 700 is an insertion loss test port of a second duplicate device-under-test path 702 for accessing an insertion loss measurement instrument. Here, the cascade path is a second combined path 700.
In practical application, the insertion loss of the second combined path may be measured by an insertion loss measuring instrument such as a vector network analyzer, so as to obtain an initial value of the insertion loss of the second combined path.
In addition, when the insertion loss of the second combined path is measured, an initial value of the insertion loss of the second combined path can be obtained by measuring the S21 parameter of the second combined path.
Further, the second combined path 700 further includes a third test socket 703 connected to the insertion loss test port of the third impedance matching network 701, and a trace between the third impedance matching network 701 and the third test socket 703, where the third test socket 703 is used to access the insertion loss measurement instrument.
Here, a trace between the impedance matching network in the second duplicated device under test path 702 and the insertion loss test port of the second duplicated device under test path 702 is denoted as a third trace structure, a trace between the third impedance matching network 701 and the third test socket 703 is denoted as a fourth trace structure, and the third trace structure and the fourth trace structure are symmetrical to each other on the third PCB.
In this step, after obtaining the initial value of the insertion loss of the second combined path, or before obtaining the initial value of the insertion loss of the second combined path, the reflection loss of the second combined path is obtained. Here, the reflection loss of the second combined path may be obtained through simulation, and for example, the reflection loss of the second combined path may be obtained through simulation by simulation software such as ads (advanced Design system).
After obtaining the reflection loss of the second combined path, subtracting the reflection loss of the second combined path from the initial value of the insertion loss of the second combined path to obtain the insertion loss of the second combined path.
Step 201 d: and deriving an insertion loss of the device under test path based on the insertion loss of the second combined path, wherein the insertion loss of the device under test path is half of the insertion loss of the second combined path.
That is, the insertion loss of the device under test path can be calculated by the following equation:
A1＝(S21’-LR)/2
wherein S21' represents an initial value of insertion loss of the second combined path, LRRepresenting the reflection loss of the second combined path.
It should be noted that, in the first embodiment of the present invention, the insertion loss of the device under test via may be obtained after obtaining the noise figure of the device under test extension circuit; the insertion loss of the device under test path may also be obtained before the noise figure of the device under test spreading circuit is obtained.
Step 202: and deriving the noise coefficient of the device under test based on the noise coefficient of the device under test expansion circuit and the insertion loss of the device under test path.
The method specifically comprises the following steps: and subtracting the insertion loss of the tested device passage from the noise coefficient of the tested device expansion circuit to obtain the noise coefficient of the tested device. That is, the noise figure NF of the device under testportComprises the following steps: NFport＝NF-A1。
In the first embodiment of the present invention, if the insertion loss of the path of the device under test is obtained by the first method, since the impedance matching network in the path of the first replica device under test and the second impedance matching network satisfy the condition of conjugate matching, the loss of signal transmission in the first combined path can be reduced to the minimum. In addition, the second PCB has the same laminated structure with the first PCB, so the insertion loss caused by the laminated structure of the second PCB and the first PCB is kept consistent, and thus, the insertion loss of the device under test via on the first PCB can be calculated by using the insertion loss of the first combined via on the second PCB.
Here, when the insertion loss of the device under test via is obtained by the first method, the first impedance matching network is suitable for a case where the first impedance matching network is a pure resistor since the reflection loss is not considered.
In the first embodiment of the present invention, if the insertion loss of the device under test path is obtained by the second method, since the impedance matching network in the second duplicated device under test path is mirror-symmetric to the third impedance matching network, the initial value of the insertion loss of the second combined path not only includes the insertion loss caused by the device loss of the second combined path and the insertion loss caused by the trace loss, but also includes the insertion loss caused by the reflection loss of the second combined path; when there is no reflection loss in the path of the device under test or the corresponding reflection loss is very low, it is necessary to eliminate the insertion loss caused by the reflection loss of the second combined path when calculating the insertion loss of the second combined path. In addition, the third PCB and the first PCB have the same laminated structure, so the insertion loss caused by the laminated structure of the third PCB and the first PCB is consistent, and thus, the insertion loss of the device under test via on the first PCB can be calculated by using the insertion loss of the second combined via on the third PCB.
Here, when the insertion loss of the device under test path is obtained by the second method, the insertion loss caused by the reflection loss is considered, and therefore, the method is suitable for the case where the first impedance matching network is a pure resistor or the case where the first impedance matching network includes a reactance section.
Second embodiment
To further illustrate the object of the present invention, the first embodiment of the present invention is further illustrated.
In the second embodiment of the invention, the device to be tested is a radio frequency transceiver, and the receiving and transmitting performance tests of the radio frequency transceiver can be completed on the first PCB; among them, the noise figure in the receiving performance of the rf transceiver is a very critical rf index. In order to obtain the noise coefficient in the receiving performance of the radio frequency transceiver, a first impedance matching network is debugged at one input port of the radio frequency transceiver, the first impedance matching network is used for ensuring that radio frequency signals can be transmitted to the radio frequency transceiver with minimum loss, and the impedance of the input port of the first radio frequency transceiver is usually matched to be close to 50 ohms, so that the reflection loss caused by the first impedance matching network can be reduced as much as possible; after the first impedance matching network is tuned out, the noise figure in the receiving performance of the rf transceiver can be measured, which will be described in detail below.
FIG. 8 is a flowchart of a second embodiment of the method for measuring the noise figure of a device under test according to the present invention, as shown in FIG. 8, the flowchart includes:
step 800: and acquiring the noise coefficient of the radio frequency transceiver extension circuit.
Here, the radio frequency transceiver extension circuit is located on the first PCB, the radio frequency transceiver extension circuit including a radio frequency pad and a radio frequency path including a first impedance matching network disposed at any one of the input ports of the radio frequency transceiver. The radio frequency path further comprises a first test seat connected with the first impedance matching network and a wire between the first impedance matching network and the first test seat, and the first test seat can be used for being connected with a noise coefficient measuring instrument.
The obtaining the noise coefficient of the radio frequency transceiver extension circuit comprises the following steps: gain of the RF transceiver extension circuit and noise power spectral density P of the RF transceiver extension circuit are measuredNOUTThe noise factor NF of the rf transceiver extension circuit is obtained by the following formula:
NF＝PNOUT-(-174dBm/Hz+Gain)。
it should be noted that, because the radio frequency path may bring about insertion loss, the noise coefficient obtained in this step is not the noise coefficient of the radio frequency transceiver itself, and the noise coefficient of the radio frequency transceiver itself may be obtained only after the insertion loss brought about by the radio frequency path is obtained through measurement.
Step 801: and acquiring the insertion loss of the radio frequency path.
In this step, since the rf path has no approximate reflection loss in actual operation, when the insertion loss of the rf path is obtained by the second method, the insertion loss caused by the reflection loss of the second combined path needs to be eliminated.
Step 801 is the same as the implementation of step 201 and will not be described in detail here.
Step 802: and obtaining the noise coefficient of the radio frequency transceiver based on the noise coefficient of the radio frequency transceiver extension circuit and the insertion loss of the radio frequency path.
Step 802 is the same as the implementation of step 202 and will not be described in detail here.
Third embodiment
The embodiment of the present invention further provides a device for measuring a noise coefficient of a device under test, fig. 9 is a schematic diagram of a structure of the device for measuring a noise coefficient of a device under test according to the embodiment of the present invention, and as shown in fig. 9, the device includes: a first obtaining module 900, a second obtaining module 901 and a calculating module 902; wherein,
a first obtaining module 900, configured to obtain a noise figure of the device under test expansion circuit; the device under test expansion circuit comprises a device under test and a device under test path, wherein the device under test path comprises a first impedance matching network arranged at any input port or any output port of the device under test;
a second obtaining module 901, configured to obtain an insertion loss of the device under test path;
a calculating module 902, configured to derive a noise figure of the device under test based on the noise figure of the device under test spreading circuit and the insertion loss of the device under test path.
Here, the first impedance matching network has a device under test port for connecting the device under test;
the second obtaining module 901 is specifically configured to copy the device under test path; setting an impedance matching network which forms conjugate matching or mirror symmetry with the first impedance matching network at the tested device port of the impedance matching network of the copied tested device path; obtaining the insertion loss of a cascade path, wherein the cascade path comprises a copied tested device path and an impedance matching network connected with the copied tested device path; deriving an insertion loss of the device under test path based on the insertion loss of the cascode path.
Further, the second obtaining module 901 is configured to, when a device under test port of the impedance matching network of the copied device under test access is provided with an impedance matching network forming mirror symmetry with the first impedance matching network, obtain an initial value of an insertion loss of the cascade access and a reflection loss of the cascade access, and subtract the reflection loss of the cascade access from the initial value of the insertion loss of the cascade access to obtain the insertion loss of the cascade access.
The calculating module 902 is specifically configured to subtract the insertion loss of the device under test path from the noise figure of the device under test spreading circuit to obtain the noise figure of the device under test.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.
Claims (8)
1. A method of measuring a noise figure of a device under test, the method comprising:
acquiring a noise coefficient of a tested device expansion circuit; the device under test expansion circuit comprises a device under test and a device under test path, wherein the device under test path comprises a first impedance matching network arranged at any input port or any output port of the device under test; wherein the first impedance matching network has a device under test port for connecting the device under test;
obtaining the insertion loss of the device under test path; wherein the obtaining the insertion loss of the device under test via comprises: replicating the device under test path; setting an impedance matching network which forms conjugate matching or mirror symmetry with the first impedance matching network at the tested device port of the impedance matching network of the copied tested device path; obtaining an insertion loss of a cascade path, wherein the cascade path comprises a copied device under test path and an impedance matching network connected with the copied device under test path; deriving an insertion loss of the device under test path based on the insertion loss of the cascode path;
and deriving the noise coefficient of the device under test based on the noise coefficient of the device under test expansion circuit and the insertion loss of the device under test path.
2. The method of claim 1, wherein the device under test via has an insertion loss that is half of an insertion loss of the cascode via.
3. The method of claim 1, wherein obtaining the insertion loss of the cascaded path when the device under test port of the impedance matching network of the replicated device under test path is provided with an impedance matching network forming a mirror symmetry with the first impedance matching network comprises:
measuring the insertion loss of a cascade path to obtain an initial value of the insertion loss of the cascade path; and obtaining the reflection loss of the cascade path, and subtracting the reflection loss of the cascade path from the initial value of the insertion loss of the cascade path to obtain the insertion loss of the cascade path.
4. The method of any of claims 1 to 3, wherein said obtaining a noise figure of the device under test expander circuit comprises: and deriving a gain and a noise power spectral density of the device under test extension circuit through measurement, and deriving a noise coefficient of the device under test extension circuit based on the measured gain and noise power spectral density of the device under test extension circuit.
5. The method of any of claims 1 to 3, wherein deriving the noise figure of the device under test based on the noise figure of the device under test spreading circuit and the insertion loss of the device under test path comprises: and subtracting the insertion loss of the tested device passage from the noise coefficient of the tested device expansion circuit to obtain the noise coefficient of the tested device.
6. An apparatus for measuring a noise figure of a device under test, the apparatus comprising: the device comprises a first acquisition module, a second acquisition module and a calculation module; wherein,
the first acquisition module is used for acquiring the noise coefficient of the expansion circuit of the device under test; the device under test expansion circuit comprises a device under test and a device under test path, wherein the device under test path comprises a first impedance matching network arranged at any input port or any output port of the device under test; wherein the first impedance matching network has a device under test port for connecting the device under test;
a second obtaining module, configured to obtain an insertion loss of the device under test path; wherein the obtaining the insertion loss of the device under test via comprises: replicating the device under test path; setting an impedance matching network which forms conjugate matching or mirror symmetry with the first impedance matching network at the tested device port of the impedance matching network of the copied tested device path; obtaining an insertion loss of a cascade path, wherein the cascade path comprises a copied device under test path and an impedance matching network connected with the copied device under test path; deriving an insertion loss of the device under test path based on the insertion loss of the cascode path;
a calculation module for deriving the noise figure of the device under test based on the noise figure of the device under test expander circuit and the insertion loss of the device under test path.
7. The apparatus according to claim 6, wherein the second obtaining module is configured to measure the insertion loss of the cascade path when the device under test port of the impedance matching network of the copied device under test path is provided with an impedance matching network forming mirror symmetry with the first impedance matching network, so as to obtain an initial value of the insertion loss of the cascade path; and obtaining the reflection loss of the cascade path, and subtracting the reflection loss of the cascade path from the initial value of the insertion loss of the cascade path to obtain the insertion loss of the cascade path.
8. The apparatus according to any of the claims 6 to 7, wherein the calculation module is specifically configured to subtract the insertion loss of the device under test path from the noise figure of the device under test extension circuit to obtain the noise figure of the device under test.
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| CN201510474016.0A CN106443220B (en) | 2015-08-05 | 2015-08-05 | A kind of method and apparatus measuring measured device noise coefficient |
| PCT/CN2016/089490 WO2017020683A1 (en) | 2015-08-05 | 2016-07-08 | Method and device for measuring noise figure of device under test |
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| CN107247696B (en) * | 2017-06-07 | 2020-09-18 | 中国电子科技集团公司第四十一研究所 | Method for calling S2P file to acquire loss compensation data in noise coefficient analyzer |
| CN108982983A (en) * | 2018-08-27 | 2018-12-11 | 湖南红太阳新能源科技有限公司 | A kind of Resistance Thermal Noise test method and test macro |
| TWI712810B (en) * | 2019-09-11 | 2020-12-11 | 英業達股份有限公司 | Method for detecting a pair of differential signals |
| CN112067914A (en) * | 2020-08-04 | 2020-12-11 | 中电科仪器仪表有限公司 | Method for correcting error introduced by extra network in noise coefficient measurement |
| CN115144805A (en) * | 2022-09-01 | 2022-10-04 | 北京唯捷创芯精测科技有限责任公司 | On-line quick calibration method for radio frequency switch chip test |
| CN116539931B (en) * | 2023-06-16 | 2023-10-20 | 荣耀终端有限公司 | Radio frequency device test connection device and test system |
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