CN115987284A - DRFM module-based rapid phase correction method for signal simulator - Google Patents

Abstract

The invention discloses a rapid phase correction method of a signal simulator based on a DRFM module. The signal simulator has two working modes: a normal operating mode and a phase correction operating mode; in a phase correction working mode, the FPGA chip of the DRFM module generates an intermediate-frequency pulse signal, the intermediate-frequency pulse signal is output to the power division module through the DA chip of the DRFM module, the power division module inputs the intermediate-frequency pulse signal into the switch module through the intermediate-frequency closed-loop correction circuit and inputs the intermediate-frequency pulse signal into the AD chip of the DRFM module through the switch module, and the computer control module performs phase analysis on the intermediate-frequency pulse signal generated by the FPGA chip and the intermediate-frequency pulse signal acquired by the FPGA chip through the AD chip and is used for phase correction of the signal simulator. The invention has the characteristics of simple and quick phase correction process, no need of manual intervention and the like.

Description

DRFM module-based rapid phase correction method for signal simulator

Technical Field

The invention belongs to the technical field of signal simulators, and particularly relates to a rapid phase correction method of a signal simulator based on a DRFM module.

Background

With the rapid development of electronic technology, in radio frequency simulation systems, semi-physical simulation systems and electronic warfare equipment, the DRFM (digital radio frequency memory) technology has become a mainstream signal processing and signal generating technology, and a signal simulator taking a DRFM module as a core can directly digitize radio frequency signals and then process and store the radio frequency signals, so as to realize the simulation of signals such as target echo signals, interference signals and radiation signals.

The DRFM module generally includes an AD chip, a DA chip, an FPGA chip, and a memory, and because the working clocks of the AD chip and the DA chip are different from the working clock of the FPGA chip, and the data transmission delay between the AD chip and the FPGA chip, and between the DA chip and the FPGA chip is jittered, the transfer function phase of the DRFM module itself changes randomly (after power up, power is not interrupted, and the transfer function phase does not change). For some simulation systems or equipment, a plurality of signal simulators based on the DRFM module are needed, a certain phase relation is needed among a plurality of simulator channels, and the phase of the DRFM module needs to be corrected after power failure and power supply.

The currently adopted phase correction mode is to use an instrument (such as a vector network analyzer) or a special device for correction, manual intervention is needed, the correction process is complex and time-consuming, and an operator is required to be familiar with the operation and use of the instrument device. Furthermore, some equipment cannot tolerate lengthy calibration procedures, resulting in improper use of the device.

Disclosure of Invention

In order to overcome the defects in the prior art, the invention provides a rapid phase correction method of a signal simulator based on a DRFM module, which has the characteristics of simple and rapid phase correction process, no need of manual intervention and the like.

In order to achieve the purpose, the technical scheme adopted by the invention is as follows:

in a first aspect, a signal simulator is provided, comprising: the system comprises a down-conversion module, a DRFM module, an up-conversion module, a frequency synthesis module, a computer control module and an intermediate frequency closed loop correction circuit; the frequency synthesizer module provides clock signals for the down-conversion module, the DRFM module and the up-conversion module; the computer control module is electrically connected with the FPGA chip of the DRFM module; the signal simulator has two working modes: a normal operating mode and a phase correction operating mode; in a normal working mode, a down-conversion module receives a radio frequency input signal and converts the radio frequency input signal into an intermediate frequency input signal, and the intermediate frequency input signal is input into an AD chip of the DRFM module through a switch module; the DRFM module modulates the intermediate-frequency input signal and converts the modulated intermediate-frequency input signal into an intermediate-frequency output signal, the intermediate-frequency output signal is output to a power division module through a DA chip of the DRFM module and then input into the up-conversion module through the power division module, and the up-conversion module converts the intermediate-frequency output signal into a radio-frequency output signal; under the phase correction working mode, the FPGA chip of the DRFM module generates an intermediate frequency pulse signal, the intermediate frequency pulse signal is output to the power division module through the DA chip of the DRFM module, the power division module inputs the intermediate frequency pulse signal to the switch module through the intermediate frequency closed loop correction circuit, the intermediate frequency pulse signal is input to the AD chip of the DRFM module through the switch module, and the computer control module performs phase analysis on the intermediate frequency pulse signal generated by the FPGA chip and the intermediate frequency pulse signal acquired by the FPGA chip through the AD chip and is used for phase correction of the signal simulator.

Further, the intermediate frequency closed loop correction circuit includes a low pass filter, an input end of the low pass filter is electrically connected to one of the output ends of the power dividing module, and an output end of the low pass filter is electrically connected to one of the input ends of the switching module.

Further, the DRFM module also comprises a storage chip, and the storage chip is electrically connected with the FPGA chip of the DRFM module.

In a second aspect, there is provided a phase correction method for a signal simulator, where the signal simulator is the signal simulator in the first aspect, the method includes: the signal simulator keeps a power-on state, generates an intermediate frequency pulse signal in an FPGA chip of the DRFM module, outputs the intermediate frequency pulse signal through a DA chip, and acquires the intermediate frequency pulse signal by an AD chip after passing through an intermediate frequency closed loop correction circuit and sends the intermediate frequency pulse signal to the FPGA chip; the FPGA chip receives the AD chipThe intermediate frequency output signal collected by the chip and the intermediate frequency pulse signal generated by the FPGA chip are sent to a computer control module; calculating the phase difference between the intermediate frequency output signal collected by the AD chip and the intermediate frequency pulse signal generated by the FPGA chip in the computer control module by using a least square method, and recording the phase difference as phi _DA +Φ _AD ） _Recording (ii) a After the signal simulator is powered off, the power is applied again, and the steps are repeated to obtain the phi after the power is applied _AD +Φ _DA A value, recorded as (Φ) _DA +Φ _AD ） _{This time} (ii) a Inputting radio frequency input signal to the signal simulator, and performing phase modulation in the DRFM module with a modulation value of (phi) _DA +Φ _AD ） _{This time} -（Φ _DA +Φ _AD ） _Recording And finishing the phase correction of the signal simulator.

Further, before the FPGA chip of the DRFM module generates the intermediate frequency pulse signal, a vector network analyzer is adopted to measure the phase difference between the radio frequency output signal and the radio frequency input signal of the signal simulator, and the phase difference is recorded as phi _OUT -Φ _IN And the modulation value used for verifying the phase correction is verified according to the following conditions: equation Φ _OUT -Φ _IN =（Φ _DA +Φ _AD ） _{This time} -（Φ _DA +Φ _AD ） _Recording This is true.

Further, when the phases of the plurality of signal simulators need to be corrected to be consistent, the phase of each signal simulator is corrected, and then the phases of the rest of the signal simulators are adjusted by taking one of the signal simulators as a reference.

Compared with the prior art, the invention has the following beneficial effects:

(1) The invention receives a radio frequency input signal through a down-conversion module, converts the radio frequency input signal into an intermediate frequency input signal, and inputs the intermediate frequency input signal into an AD chip of a DRFM module through a switch module; the DRFM module converts an intermediate-frequency input signal into an intermediate-frequency output signal, then the intermediate-frequency output signal is output to the power division module through the DA chip, the power division module inputs one path of intermediate-frequency output signal into the switch module through the intermediate-frequency closed-loop correction circuit and inputs the intermediate-frequency output signal and an AD chip of the DRFM module through the switch module, and the FPGA chip of the DRFM module inputs the intermediate-frequency output signal acquired by the AD chip and a transmitting signal of the intermediate-frequency output signal into the computer control module for phase analysis for phase correction of the signal simulator, so that the method has the characteristics of simple and rapid phase correction process, no need of manual intervention and the like;

(2) The invention realizes the rapid, automatic, high-precision and digital correction method of the phase of the signal simulator based on the DRFM technology, does not need instruments, does not need manual intervention in the correction process, automatically corrects after equipment is powered on, has high correction speed, high precision and strong adaptability, and can meet the phase consistency correction requirement of a plurality of signal simulator channels based on the DRFM module.

Drawings

FIG. 1 is a schematic diagram of a signal simulator based on a DRFM module;

fig. 2 is a schematic diagram of a principle of phase correction of a signal simulator based on a DRFM module according to an embodiment of the present invention (in which, the frequency synthesizer module is not shown).

Detailed Description

The invention is further described below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.

The first embodiment is as follows:

as shown in fig. 1, the DRFM module-based signal simulator generally includes a down-conversion module, a DRFM module, an up-conversion module, a frequency synthesis module, and a computer control module, wherein the DRFM module includes an AD chip, a DA chip, an FPGA chip, and a memory chip.

As shown in fig. 2, the present embodiment provides a signal simulator based on a DRFM module, which includes: the device comprises a down-conversion module, a DRFM module, an up-conversion module, a frequency synthesis module, a computer control module and an intermediate frequency closed loop correction circuit.

The frequency synthesis module provides clock signals for the down-conversion module, the DRFM module and the up-conversion module.

And the computer control module is electrically connected with the FPGA chip of the DRFM module. The signal simulator has two modes of operation: a normal operating mode and a phase correction operating mode.

In a normal working mode, the down-conversion module receives a radio frequency input signal and converts the radio frequency input signal into an intermediate frequency input signal, and the intermediate frequency input signal is input into an AD chip of the DRFM module through the switch module; the DRFM module modulates the intermediate-frequency input signal and converts the modulated intermediate-frequency input signal into an intermediate-frequency output signal, the intermediate-frequency output signal is output to the power division module through a DA chip of the DRFM module, and then the intermediate-frequency output signal is input into the up-conversion module through the power division module, and the up-conversion module converts the intermediate-frequency output signal into a radio-frequency output signal.

Under the phase correction working mode, an FPGA chip of the DRFM module generates an intermediate frequency pulse signal, the intermediate frequency pulse signal is output to the power division module through a DA chip of the DRFM module, the power division module inputs the intermediate frequency pulse signal into the switch module through the intermediate frequency closed loop correction circuit and inputs the intermediate frequency pulse signal into an AD chip of the DRFM module through the switch module, and the computer control module performs phase analysis on the intermediate frequency pulse signal generated by the FPGA chip and the intermediate frequency pulse signal acquired by the FPGA chip through the AD chip and is used for phase correction of the signal simulator.

The intermediate frequency closed loop correction circuit comprises a low-pass filter, wherein the input end of the low-pass filter is electrically connected with one of the output ends of the power dividing module, and the output end of the low-pass filter is electrically connected with one of the input ends of the switch module.

The DRFM module also comprises a storage chip which is electrically connected with the FPGA chip of the DRFM module.

The principle of phase correction is as follows.

The signal simulator is powered on and kept in a power-on state, and the phase difference between the AD chip and the FGPA chip caused by clock and transmission delay jitter factors is phi _AD The phase difference between the DA chip and the FGPA chip is phi _DA For determining the value, the initial phase of the RF input signal input by the signal simulator is phi _IN The phase difference caused by the other parts except the AD chip and the DA chip in the signal simulator is phi _Δ The phase phi of the RF output signal _OUT Comprises the following steps:

Φ _OUT =Φ _IN +Φ _AD +Φ _DA +Φ _Δ

wherein phi _AD And phi _DA After each power-on, a determined value is obtained, and the phase position is randomly changed between each power-on, namely the phase position needing to be corrected. Phi _Δ Is a fixed value and is related to the total electrical length of other devices in the circuit except the AD chip and the DA chip. The above equation can be converted into the following equation, i.e. the phase difference between the rf output signal and the rf input signal (phase difference caused by the electrical length of the signal simulator) is composed of three parts: phi _AD 、Φ _DA And phi _Δ ：

Φ _OUT -Φ _IN =Φ _AD +Φ _DA +Φ _Δ

The phase difference caused by the electrical length of the signal simulator can be measured by the vector network analyzer, and only phi needs to be measured _AD +Φ _DA To obtain phi _AD +Φ _DA Value sum phi _OUT -Φ _IN The corresponding relationship of (1).

Φ _AD +Φ _DA The measurement method of the value is as follows.

The method comprises the steps that a dot frequency pulse (intermediate frequency pulse signal) is generated in an FPGA chip of a DRFM module and is played through a DA chip, the output intermediate frequency pulse signal enters a low-pass filter in an intermediate frequency closed loop correction circuit after passing through a power divider of a power dividing module and then enters an AD chip after being switched through a switch in a switch module, the AD chip collects the intermediate frequency pulse signal and then sends the collected intermediate frequency pulse signal and a signal (a digital baseband, namely a transmitting signal of an intermediate frequency output signal) which generates output by the AD chip to the FPGA chip, the FPGA chip transmits the collected intermediate frequency pulse signal and the signal (the digital baseband, namely the transmitting signal of the intermediate frequency output signal) to a computer control module, and phase analysis is carried out on the two signals in the computer control module.

The generated dot frequency pulse has a phase phi ₁ The phase of the signal is phi after being output by the DA chip ₁ +Φ _DA After correcting the intermediate frequency closed loop branch, the signal phase is phi ₁ +Φ _DA +Φ _{Branch stand} （Φ _{Branch stand} The phase influence value of the intermediate frequency closed loop branch circuit, including the influence of a cable, a power divider, a switch and a low-pass filter, is a fixed value), is acquired by an AD chip and then is sent to an FPGA chip, and the signal phase is phi ₁ +Φ _DA +Φ _{Branch stand} +Φ _AD The pulse generatedImpulse signal phase phi ₁ In contrast, increase phi _DA +Φ _{Branch stand} +Φ _AD Wherein phi _{Branch stand} Is a fixed value. Sending the collected signal and the transmitted signal (digital baseband) to the computer control module, and obtaining phi in the computer control module by least square method _DA +Φ _{Branch stand} +Φ _AD Value, fixed value phi _{Branch stand} The same for each power-up, the variable phi for each power-up _DA +Φ _AD No effect and negligible.

Measuring phi by vector network analyzer _OUT -Φ _IN Value, phi, can be measured by internally generating a signal for intermediate frequency closed loop _AD +Φ _DA Value, record this time phi _DA +Φ _AD And phi _OUT -Φ _IN The value is obtained.

Powering up again after power failure, adopting once internal intermediate frequency self-closed loop again, and measuring phi after the power up _AD +Φ _DA Value according to the measured phi _AD +Φ _DA Value and recorded phi _DA +Φ _AD The difference value of the values is used for carrying out phase compensation on the signals received by the simulator in the FPGA, and the compensation quantity is (phi) _DA +Φ _AD ） _{This time} -（Φ _DA +Φ _AD ） _Recording Phi, i.e. to ensure that the phase difference between the simulator output signal and the input signal is recorded _OUT -Φ _IN The value is obtained.

Measured phi due to correction at intermediate frequency _DA +Φ _AD The method is independent of the frequency of the input signal, and does not need to traverse the frequency when phase correction is carried out, so that the correction time can be greatly shortened, and only a vector network analyzer is needed to measure phi _OUT -Φ _IN And the frequency traversal is performed, and the work is only needed to be done once without being done every time of correction.

The DRFM module-based signal simulator can carry out rapid, automatic and high-precision digital correction on the phase, instruments are not needed, manual intervention is not needed in the correction process, the device is automatically corrected after being powered on, the correction speed is high, the precision is high, the adaptability is strong, and the requirements of phase consistency correction of a plurality of DRFM module-based signal simulator channels can be met.

The second embodiment:

based on the signal simulator based on the DRFM module in the first embodiment, this embodiment provides a phase correction method for a signal simulator, where the signal simulator is the signal simulator in the first embodiment, and the method includes:

1. after the signal simulator is electrified, the phase difference between the output signal and the input signal of the signal simulator is measured by adopting a vector network analyzer and recorded as phi _OUT -Φ _IN ；

2. The signal simulator keeps a power-on state, generates an intermediate frequency pulse signal in an FPGA chip of the DRFM module, outputs the intermediate frequency pulse signal through a DA chip, and acquires the intermediate frequency pulse signal by an AD chip after passing through an intermediate frequency closed loop correction circuit and sends the intermediate frequency pulse signal to the FPGA chip;

3. the FPGA chip sends the received intermediate-frequency output signal acquired by the AD chip and the intermediate-frequency pulse signal generated by the FPGA chip to the computer control module;

4. calculating the phase difference between the intermediate frequency output signal collected by the AD chip and the intermediate frequency pulse signal generated by the FPGA chip in the computer control module by using a least square method, and recording the phase difference as phi _DA +Φ _AD ） _Recording ；

5. Powering up the signal simulator again after the power failure, and repeating the steps 2 to 4 to obtain the phi after the power up _AD +Φ _DA A value, recorded as (Φ) _DA +Φ _AD ） _{This time} ；

6. Inputting radio frequency input signal to the signal simulator, and performing phase modulation in the DRFM module with a modulation value of (phi) _DA +Φ _AD ） _{This time} -（Φ _DA +Φ _AD ） _Recording Completing the phase correction of the signal simulator; the phase difference between the radio frequency output signal and the radio frequency input signal of the signal simulator measured in the step 1 can be used for verifying a modulation value of phase correction, and the verification passing condition is as follows: equation Φ _OUT -Φ _IN =（Φ _DA +Φ _AD ） _{This time} -（Φ _DA +Φ _AD ） _Recording If true;

7. when a plurality of signal simulators based on the DRFM module are required to have consistent phase difference of each signal simulator channel, 1 to 6 steps of work can be respectively carried out on each signal simulator channel, and the phase difference between the output signal and the input signal of each signal simulator channel is fixed after the work is finished. Furthermore, one of the channels is used as a reference, and fixed phase differences among the channels are compensated, so that the aim of consistent phase differences of the channels of the plurality of signal simulators can be fulfilled.

The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, it is possible to make various improvements and modifications without departing from the technical principle of the present invention, and those improvements and modifications should be considered as the protection scope of the present invention.

Claims (6)

1. A signal simulator, comprising: the system comprises a down-conversion module, a DRFM module, an up-conversion module, a frequency synthesis module, a computer control module and an intermediate frequency closed loop correction circuit;

the frequency synthesizer module provides clock signals for the down-conversion module, the DRFM module and the up-conversion module; the computer control module is electrically connected with the FPGA chip of the DRFM module;

the signal simulator has two working modes: a normal operating mode and a phase correction operating mode;

in a normal working mode, a down-conversion module receives a radio frequency input signal and converts the radio frequency input signal into an intermediate frequency input signal, and the intermediate frequency input signal is input into an AD chip of the DRFM module through a switch module; the DRFM module modulates the intermediate-frequency input signal and converts the modulated intermediate-frequency input signal into an intermediate-frequency output signal, the intermediate-frequency output signal is output to a power division module through a DA chip of the DRFM module and then input into the up-conversion module through the power division module, and the up-conversion module converts the intermediate-frequency output signal into a radio-frequency output signal;

in a phase correction working mode, the FPGA chip of the DRFM module generates an intermediate-frequency pulse signal, the intermediate-frequency pulse signal is output to the power division module through the DA chip of the DRFM module, the power division module inputs the intermediate-frequency pulse signal into the switch module through the intermediate-frequency closed-loop correction circuit and inputs the intermediate-frequency pulse signal into the AD chip of the DRFM module through the switch module, and the computer control module performs phase analysis on the intermediate-frequency pulse signal generated by the FPGA chip and the intermediate-frequency pulse signal acquired by the FPGA chip through the AD chip and is used for phase correction of the signal simulator.

2. The signal simulator of claim 1, wherein the intermediate frequency closed loop correction circuit comprises a low pass filter, an input of the low pass filter is electrically connected to one of the output terminals of the power dividing module, and an output of the low pass filter is electrically connected to one of the input terminals of the switching module.

3. The signal simulator of claim 1, wherein the DRFM module further comprises a memory chip electrically connected to the FPGA chip of the DRFM module.

4. A method for correcting phase of a signal simulator, wherein the signal simulator is the signal simulator according to any one of claims 1 to 3, and the method comprises:

the signal simulator keeps a power-on state, generates an intermediate frequency pulse signal in an FPGA chip of the DRFM module, outputs the intermediate frequency pulse signal through a DA chip, and acquires the intermediate frequency pulse signal by an AD chip after passing through an intermediate frequency closed loop correction circuit and sends the intermediate frequency pulse signal to the FPGA chip;

the FPGA chip sends the received intermediate-frequency output signal acquired by the AD chip and the intermediate-frequency pulse signal generated by the FPGA chip to the computer control module;

calculating the phase difference between the intermediate frequency output signal collected by the AD chip and the intermediate frequency pulse signal generated by the FPGA chip in the computer control module by using a least square method, and recording the phase difference as phi _DA +Φ _AD ） _Recording ；

After the signal simulator is powered off, the power is applied again, and the steps are repeated to obtain the phi after the power is applied _AD +Φ _DA A value, recorded as (Φ) _DA +Φ _AD ） _{This time} ；

Inputting radio frequency input signal to the signal simulator, and performing phase modulation in the DRFM module with a modulation value of (phi) _DA +Φ _AD ） _{This time} -（Φ _DA +Φ _AD ） _Recording And finishing the phase correction of the signal simulator.

5. The method of claim 4, wherein before the FPGA chip of the DRFM module generates the intermediate frequency pulse signal, the phase difference between the RF output signal and the RF input signal of the signal simulator is measured by a vector network analyzer and recorded as Φ _OUT -Φ _IN And the modulation value used for verifying the phase correction is verified according to the following conditions: equation Φ _OUT -Φ _IN =（Φ _DA +Φ _AD ） _{This time} -（Φ _DA +Φ _AD ） _Recording This is true.

6. The method according to claim 4, wherein when the phases of the plurality of signal simulators need to be corrected to be consistent, the phase of each signal simulator is corrected, and then the phases of the rest of the signal simulators are adjusted with one of the signal simulators as a reference.

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