CN210776661U - Automatic identifying and expanding device for JTAG link - Google Patents

Abstract

The utility model provides a JTAG link automatic identification and expansion device, including two at least PCBs, all be equipped with first JTAG connector, second JTAG connector, alternative chip and establish ties the JTAG sublink that forms by at least one JTAG device on every PCB. The utility model discloses a second JTAG connector on the first PCB in two adjacent PCBs and the disconnection and the connection of the first JTAG connector on the second PCB change the control signal input of alternative chip, and then the length of automatic adjustment JTAG link need not software control to can be according to the demand, the scope of pertinence selection test object provides more alternative for the user.

Description

Automatic identifying and expanding device for JTAG link

Technical Field

The utility model relates to a technical field that cascades of JTAG link between PCB boards specifically is a JTAG link automatic identification and extends device.

Background

JTAG (Joint Test Action Group) is an international standard Test protocol and is mainly used for testing the inside of a chip. At present, many complex devices support the JTAG protocol, such as DSP, FPGA, etc., and such devices supporting the JTAG protocol are generally called JTAG devices. The JTAG device can be conveniently downloaded and debugged through the JTAG connector.

When a circuit contains a plurality of JTAG devices, the space occupied by the circuit is greatly increased if one JTAG connector is arranged for each JTAG device. One solution is to connect multiple JTAG devices in a circuit in series to form a JTAG link (i.e., a mode of connecting TDI to TDO to TDI forms a non-closed JTAG link, where a JTAG device in the JTAG link that is not connected in series with TDO pins of other JTAG devices may be referred to as a first JTAG device of the JTAG link, and a JTAG device in the JTAG link that is not connected in series with TDI pins of other JTAG devices may be referred to as a last JTAG device of the JTAG link), so that downloading and debugging of each JTAG device can be completed through one JTAG connector, and connectivity between each JTAG device can also be tested through the JTAG link.

At present, a plurality of application occasions are derived according to the JTAG link in the industry, but the cascading and adjusting scheme of the JTAG link between the PCB boards needs to be controlled by software, the length of the JTAG link cannot be automatically identified and adjusted, only the fixed JTAG maximum link can be realized, and certain constraint is achieved. In addition, in the using process, the circuit is more prone to realize cascade connection from the whole to local stages, but the existing scheme cannot meet the requirement of local circuit debugging.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a JTAG link automatic identification and extend device, the device need not just can realize the cascade of JTAG link between the PCB board with the help of software, the length of automatic identification and adjustment JTAG link.

The technical scheme of the utility model is that:

a JTAG link automatic identification and expansion device comprises at least two PCBs, wherein each PCB is provided with a first JTAG connector, a second JTAG connector, an alternative chip and a JTAG sub-link formed by connecting at least one JTAG device in series;

when a second JTAG connector on a first PCB in two adjacent PCBs is disconnected with a first JTAG connector on a second PCB, a first signal transmission channel of the alternative chip is conducted, and a JTAG sub-link on the first PCB is disconnected with a JTAG sub-link on the second PCB;

when a second JTAG connector on a first PCB in two adjacent PCBs is connected with a first JTAG connector on a second PCB, a second signal transmission channel of the alternative chip is conducted, and a JTAG sub-link on the first PCB is connected with a JTAG sub-link on the second PCB.

The automatic identification and expansion device of the JTAG link is characterized in that a TDI pin of a first JTAG device of each JTAG sub-link on each PCB is connected with a TDI pin of a first JTAG connector, a TDO pin of a last JTAG device is respectively connected with a TDO pin of a second JTAG connector and a first input pin of an alternative chip, a second input pin of the alternative chip is connected with a TDI pin of the second JTAG connector, and an output pin of the alternative chip is connected with a TDO pin of the first JTAG connector;

the port input pin of the first JTAG connector is connected with GND, the port input pin of the second JTAG connector is connected with the control signal input pin of the alternative chip, and a node between the port input pin of the second JTAG connector and the control signal input pin of the alternative chip is connected with VCC through a pull-up resistor;

when a second JTAG connector on a first PCB in two adjacent PCBs is disconnected with a first JTAG connector on a second PCB, the control signal input of an alternative chip on the first PCB is at a high level, and a signal on a first input pin of the alternative chip reaches an output pin through a first signal transmission channel;

when a second JTAG connector on a first PCB in two adjacent PCBs is connected with a first JTAG connector on a second PCB, the control signal input of an alternative chip on the first PCB is low level, and a signal on a second input pin of the alternative chip reaches an output pin through a second signal transmission channel.

The JTAG link automatic identification and expansion device is an FPGA chip.

According to the above technical scheme, the utility model discloses a connection and the disconnection of JTAG connector between PCB board have realized the automatic length adjustment of JTAG link, need not software control to can be according to the demand, the scope of pertinence ground selection test object provides more alternative for the user.

Drawings

Fig. 1 is a schematic structural diagram of the present invention;

fig. 2 is a schematic view of the working principle of the present invention.

Detailed Description

The invention is further described with reference to the following figures and specific embodiments.

As shown in fig. 1 and fig. 2, an automatic JTAG link identification and expansion apparatus includes at least two PCBs 0, each PCB0 is provided with a first JTAG connector 1, a second JTAG connector 2, an alternative chip 3, and a JTAG sublink 4 formed by at least one JTAG device connected in series (the JTAG sublink mentioned here has the same definition as a well-known JTAG link, and different names are used for convenience of description, the same applies hereinafter).

The TDI pin of the first JTAG device of the JTAG sub-link 4 on each PCB0 is connected with the TDI pin of the first JTAG connector 1, the TDO pin of the last JTAG device of the JTAG sub-link 4 is respectively connected with the TDO pin of the second JTAG connector 2 and the first input pin IN1 of the alternative chip 3, the second input pin IN2 of the alternative chip 3 is connected with the TDI pin of the second JTAG connector 2, and the output pin OUT of the alternative chip 3 is connected with the TDO pin of the first JTAG connector 1.

The PINx pin (port input pin) of the first JTAG connector 1 is connected to GND, the PINx pin (port input pin) of the second JTAG connector 2 is connected to the control signal input pin S of the one-out-of-two chip 3, and a node between the PINx pin of the second JTAG connector 2 and the control signal input pin S of the one-out-of-two chip 3 is connected to VCC through a pull-up resistor 5.

When the second JTAG connector 2 on the first PCB0 of the two adjacent PCBs 0 is disconnected from the first JTAG connector 1 on the second PCB0 (at this time, the PINx pin of the second JTAG connector 2 on the first PCB0 is disconnected from the PINx pin of the first JTAG connector 1 on the second PCB 0), the control signal SEL input of the one-of-two chip 3 on the first PCB0 is at a high level, the first signal transmission channel of the one-of-two chip 3 is turned on, and the signal on the first input pin IN1 of the one-of-two chip 3 reaches the output pin OUT through the first signal transmission channel of the one-of-two chip 3.

When the second JTAG connector 2 on the first PCB0 of the two adjacent PCBs 0 is connected to the first JTAG connector 1 on the second PCB0 (at this time, the PINx pin of the second JTAG connector 2 on the first PCB0 is connected to the PINx pin of the first JTAG connector 1 on the second PCB 0), the control signal SEL input of the one-of-two chip 3 on the first PCB0 is at a low level, the second signal transmission path of the one-of-two chip 3 is turned on, and the signal on the second input pin IN2 of the one-of-two chip 3 reaches the output pin OUT through the second signal transmission path of the one-of-two chip 3.

In this embodiment, the JTAG device constituting the JTAG sub-link 4 is an FPGA chip.

The utility model discloses a theory of operation:

as shown in fig. 2, assuming that the number of PCBs 0 is 2, this is taken as an example for explanation:

when the second JTAG connector 2 on the first PCB0 is empty, the control signal SEL of the second chip 3 on the first PCB0 has a value VCC, and at this time, the first signal transmission path between the first input pin IN1 and the output pin OUT of the second chip 3 on the first PCB0 is turned on.

The JTAG path is: first JTAG connector 1 on first PCB0 → JTAG sublink 4 on first PCB0 → first JTAG connector 1 on first PCB0, i.e., only the intra-board JTAG link of first PCB0 can be implemented. In this JTAG path, the first JTAG connector 1 on the first PCB0 is used as a system debug interface connector.

When the second JTAG connector 2 on the first PCB0 is connected to the first JTAG connector 1 on the second PCB0 IN an inserted manner, the control signal SEL of the second chip 3 on the first PCB0 has a value of GND, and at this time, the second signal transmission path between the second input pin IN2 and the output pin OUT of the second chip 3 on the first PCB0 is turned on.

The JTAG path is: the first JTAG connector 1 on the first PCB0 → the JTAG sub-link 4 on the first PCB0 → the JTAG sub-link 4 on the second PCB0 → the first JTAG connector 1 on the first PCB0, that is, the JTAG link cascade between the two PCBs 0 is realized. In this JTAG path, the first JTAG connector 1 on the first PCB0 is used as a system debug interface connector.

To sum up, the utility model discloses can change control signal SEL's level through the plug of JTAG connector on the adjacent PCB according to the demand, and control signal SEL adjusts the connection figure of JTAG sublink through the signal transmission passageway of control alternative chip, and then realizes the automatic length adjustment of JTAG link.

The above-mentioned embodiments are only to describe the preferred embodiments of the present invention, but not to limit the scope of the present invention, and various modifications and improvements made by those skilled in the art without departing from the design spirit of the present invention should fall into the protection scope defined by the claims of the present invention.

Claims (3)

1. A JTAG link automatic identification and expansion device comprises at least two PCBs, and is characterized in that: each PCB is provided with a first JTAG connector, a second JTAG connector, an alternative chip and a JTAG sub-link formed by connecting at least one JTAG device in series;

when a second JTAG connector on a first PCB in two adjacent PCBs is disconnected with a first JTAG connector on a second PCB, a first signal transmission channel of the alternative chip is conducted, and a JTAG sub-link on the first PCB is disconnected with a JTAG sub-link on the second PCB;

when a second JTAG connector on a first PCB in two adjacent PCBs is connected with a first JTAG connector on a second PCB, a second signal transmission channel of the alternative chip is conducted, and a JTAG sub-link on the first PCB is connected with a JTAG sub-link on the second PCB.

2. The automatic JTAG link identification and expansion apparatus of claim 1, wherein: the first JTAG device TDI pin of each PCB is connected with the first JTAG connector TDI pin, the last JTAG device TDO pin is respectively connected with the second JTAG connector TDO pin and the first input pin of the alternative chip, the second input pin of the alternative chip is connected with the second JTAG connector TDI pin, and the output pin of the alternative chip is connected with the first JTAG connector TDO pin;

the port input pin of the first JTAG connector is connected with GND, the port input pin of the second JTAG connector is connected with the control signal input pin of the alternative chip, and a node between the port input pin of the second JTAG connector and the control signal input pin of the alternative chip is connected with VCC through a pull-up resistor;

when a second JTAG connector on a first PCB in two adjacent PCBs is disconnected with a first JTAG connector on a second PCB, the control signal input of an alternative chip on the first PCB is at a high level, and a signal on a first input pin of the alternative chip reaches an output pin through a first signal transmission channel;

when a second JTAG connector on a first PCB in two adjacent PCBs is connected with a first JTAG connector on a second PCB, the control signal input of an alternative chip on the first PCB is low level, and a signal on a second input pin of the alternative chip reaches an output pin through a second signal transmission channel.

3. The automatic JTAG link identification and expansion apparatus of claim 1, wherein: the JTAG device is an FPGA chip.

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