CN106409840A - Thin film transistor array substrate, manufacturing method thereof and display panel - Google Patents
Thin film transistor array substrate, manufacturing method thereof and display panel Download PDFInfo
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- CN106409840A CN106409840A CN201610916022.1A CN201610916022A CN106409840A CN 106409840 A CN106409840 A CN 106409840A CN 201610916022 A CN201610916022 A CN 201610916022A CN 106409840 A CN106409840 A CN 106409840A
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- amorphous silicon
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- 239000000758 substrate Substances 0.000 title claims abstract description 86
- 239000010409 thin film Substances 0.000 title claims abstract description 63
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 84
- 239000004065 semiconductor Substances 0.000 claims abstract description 39
- 238000000034 method Methods 0.000 claims description 20
- 239000012212 insulator Substances 0.000 claims description 17
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 8
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 abstract description 7
- 239000002041 carbon nanotube Substances 0.000 abstract description 5
- 229910021393 carbon nanotube Inorganic materials 0.000 abstract description 5
- 230000005611 electricity Effects 0.000 abstract description 3
- 239000013078 crystal Substances 0.000 description 6
- 239000010408 film Substances 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 239000004568 cement Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 2
- 229910010272 inorganic material Inorganic materials 0.000 description 2
- 239000011147 inorganic material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 229920000728 polyester Polymers 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013039 cover film Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052573 porcelain Inorganic materials 0.000 description 1
- 238000000197 pyrolysis Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000012780 transparent material Substances 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1229—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with different crystal properties within a device or between different devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1604—Amorphous materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides a thin film transistor array substrate, a manufacturing method thereof and a display panel. The thin film transistor array substrate comprises thin film transistors, wherein each thin film transistor is internally provided with an active layer composed of a carbon nanotube semiconductor layer and a non-doped amorphous silicon layer, and the non-doped amorphous silicon layer is arranged between the corresponding carbon nanotube semiconductor layer and a source as well as a drain. Therefore, when the thin film transistor is turned on, electricity is mainly conducted by means of the carbon nanotube semiconductor layer in the active layer, and the carbon nanotube semiconductor layer has high electron mobility and forms a high ON-state current; and when the thin film transistor is turned off, a leakage current is mainly released by means of the non-doped amorphous silicon layer in the active layer, and the leakage current is small, thus the thin film transistor has a high switching current ratio.
Description
Technical field
The present invention relates to display technology field, particularly to a kind of thin-film transistor array base-plate, its manufacture method and aobvious
Show panel.
Background technology
Rise with Global Information Community increased the demand to various display devices.Therefore, various planes are shown
The research and development of device has put into very big effort, such as liquid crystal display (LCD), plasma display panel (PDP), electroluminescent
Display (ELD) and vacuum fluorescent display (VFD).
Thin film transistor (TFT) (Thin Film Transistor, TFT) is the key electricity of one of modern microelectronic technology
Sub-component, has been widely used in the fields such as flat faced display at present.In actual applications, the requirement to thin film transistor (TFT)
It is desirable to obtain larger switching current ratio.The factor affecting above-mentioned switching current ratio in addition to the preparation technology of thin film transistor (TFT),
In active layer in thin film transistor (TFT), the carrier mobility of semi-conducting material is the most important impact of impact switching current ratio
One of factor.
In prior art, the material forming active layer in thin film transistor (TFT) is non-crystalline silicon or polysilicon.Using non-crystalline silicon as
The technology of preparing of the amorphous silicon film transistor of active layer is more ripe, but in amorphous silicon film transistor, due to active layer
In usually contain substantial amounts of dangling bonds so that the mobility of carrier is very low, thus leading to the response speed of thin film transistor (TFT) relatively
Slowly.Using polysilicon as the thin film transistor (TFT) of active layer with respect to the thin film transistor (TFT) using non-crystalline silicon as active layer, have relatively
High carrier mobility, but polycrystalline SiTFT low temperature preparation is relatively costly, and method is more complicated, and polysilicon membrane is brilliant
The off-state current of body pipe is larger.
Content of the invention
In consideration of it, being necessary to provide a kind of thin-film transistor array base-plate, its manufacture method and display floater, existing to solve
In some thin film transistor (TFT)s, or the mobility of carrier is relatively low in active layer, lead to the response speed of thin film transistor (TFT) slower,
Preparation cost is higher, and method is more complicated, the problems such as off-state current is larger.
In order to achieve the above object, the embodiment of the present invention provides a kind of thin-film transistor array base-plate, described film crystal
Pipe array base palte includes underlay substrate and the multiple thin film transistor (TFT)s being located on described underlay substrate, and described thin film transistor (TFT) includes
Grid on underlay substrate, gate insulator, source electrode, drain electrode and active layer, described source electrode and described drain electrode respectively with institute
State active layer contact, described active layer includes CNT semiconductor layer and undoped amorphous silicon layer, described undoped non-crystalline silicon
Layer is located between described CNT semiconductor layer and described source electrode and described drain electrode.
The present invention also provides a kind of display floater, and described display floater includes a thin-film transistor array base-plate, described thin
Film transistor array base palte includes underlay substrate and the multiple thin film transistor (TFT)s being located on described underlay substrate, described film crystal
Pipe includes grid on underlay substrate, gate insulator, source electrode, drain electrode and active layer, and described source electrode and described drain electrode divide
Do not contact with described active layer, described active layer includes CNT semiconductor layer and undoped amorphous silicon layer, described undoped
Amorphous silicon layer is located between described CNT semiconductor layer and described source electrode and described drain electrode.
The present invention also provides a kind of manufacture method of thin-film transistor array base-plate, and methods described includes：
One underlay substrate is provided；
Multiple thin film transistor (TFT)s are formed on described underlay substrate, described thin film transistor (TFT) includes grid and gate insulator
Layer, source electrode, drain electrode and active layer, described source electrode is contacted with described active layer respectively with described drain electrode, and described active layer includes carbon
Nano-tubes semiconductor layer and undoped amorphous silicon layer, described undoped amorphous silicon layer is located at described CNT semiconductor layer and institute
State between source electrode and described drain electrode.
Thin-film transistor array base-plate provided in an embodiment of the present invention, its manufacture method and display floater, in film crystal
The active layer being made up of CNT semiconductor layer and undoped amorphous silicon layer is set in pipe, and undoped amorphous silicon layer is set
It is placed between CNT semiconductor layer and source electrode and drain electrode.So, when thin film transistor (TFT) is opened, mainly pass through in active layer
CNT semiconductor layer conductive, CNT semiconductor layer has higher electron mobility, and forms larger ON state
Electric current, when thin film transistor (TFT) cuts out, leakage current is mainly discharged by the undoped amorphous silicon layer in active layer, has relatively
Little leakage current, so that thin film transistor (TFT) has higher switching current ratio.
Brief description
A kind of axonometric chart of display device that Fig. 1 provides for a preferred embodiment of the present invention；
Fig. 2 is the fragmentary cross-sectional view in Fig. 1 shown in II-II；
In the manufacturing process of the thin-film transistor array base-plate that Fig. 3 to Fig. 6 is provided by the present invention one better embodiment
Profile.
Specific embodiment
For making the technical problem to be solved in the present invention, technical scheme and advantage clearer, below in conjunction with accompanying drawing and tool
Body embodiment is described in detail.
As shown in figure 1, the axonometric chart of a kind of display device that Fig. 1 provides for a preferred embodiment of the present invention.Described display
Device 100 includes second substrate 20 that first substrate 10 is oppositely arranged with described first substrate 10 and is located at described first substrate
Liquid crystal layer 30 between 10 and described second substrate 20.Described display device 100 also includes a viewing area 101 and shows around described
Show the Zhou Bianqu 102 in area 101, described viewing area 101 is used for realizing the display function of described display device.
In present embodiment, described first substrate is thin-film transistor array base-plate, and described second substrate is colorized optical filtering
Plate base, but be not limited thereto, in other embodiments, described first substrate can also be colored filter substrate, institute
Stating second substrate can also be thin-film transistor array base-plate.Hereinafter, first substrate is all called for thin film transistor (TFT) array base
Plate.
Please refer to Fig. 2, Fig. 2 is the fragmentary cross-sectional view in Fig. 1 shown in II-II.Described thin film transistor (TFT) array base
Plate 10 includes multiple thin film transistor (TFT)s 11, underlay substrate 12, passivation layer 13 and pixel electrode 14.Multiple described thin film transistor (TFT)s 11
On described underlay substrate 12, described passivation layer 13 cover film transistor 11 and described underlay substrate 12, described pixel electricity
Pole 14 is arranged on described passivation layer 13 and is electrically connected with described thin film transistor (TFT) 11.
Described thin film transistor (TFT) 11 includes grid 111, gate insulator 112, source electrode 113, drain electrode 114 and active layer 115,
Described grid 111 is arranged on described underlay substrate 12, and described gate insulator 112 covers described grid 111 and described substrate
Substrate 12, described active layer 115 is located on described gate insulator 112 and is correspondingly arranged in the top of described grid 111, described
Source electrode 113 and described drain electrode 114 are located on described active layer 115 and are contacted with described active layer 115, described source electrode 113 and institute
State the opposite end that drain electrode 114 is respectively arranged at described active layer 115.
Described passivation layer 13 includes contact hole 131, described contact hole 131 be located at described drain electrode 114 above, and with described leakage
Pole 114 is correspondingly arranged, and described pixel electrode 14 passes through described contact hole 131 and described drain electrode 114 electric connection.Described thin film is brilliant
Body pipe array base palte 10 also includes the common electrode layer (not shown) with described pixel electrode 14 insulation set.
Described display device can be：Any tool such as LCD TV, liquid crystal display, DPF, mobile phone, panel computer
There are product or the part of display function, wherein, described display device also includes flexible PCB, printed circuit board (PCB) and backboard.
In present embodiment, described underlay substrate 12 can for printing opacity (as glass, quartz or the like) or light tight (such as
Chip, pottery or the like) rigid inorganic material, can also be organic for the pliability such as plastic cement, rubber, polyester or Merlon
Material.
In present embodiment, the material of described pixel electrode 14 is preferably electrically conducting transparent material, such as tin indium oxide, Indium sesquioxide.
Zinc or the like etc..
Described active layer 115 includes CNT semiconductor layer 1151 and undoped amorphous silicon layer 1152, described carbon nanometer
Pipe semiconductor layer 1151 is located between described undoped amorphous silicon layer 1152 and described gate insulator 112, and described undoped is non-
Crystal silicon layer 1152 is located between described CNT semiconductor layer 1151 and described source electrode 113 and described drain electrode 114.Described carbon is received
Projection on described underlay substrate 12 for the mitron semiconductor layer 1151 and described undoped amorphous silicon layer 1152 are in described substrate base
Projection on plate 12 overlaps.
Described source electrode 113 and described drain electrode 114 projections on described underlay substrate 12 are located at described undoped non-crystalline silicon
Layer 1152 in the projection on described underlay substrate, simultaneously as described CNT semiconductor layer 1151 is in described substrate base
Projection on described underlay substrate 12 overlaps with described undoped amorphous silicon layer 1152 for projection on plate 12, so described source electrode
113 and described drain electrode 114 projections on described underlay substrate 12 be similarly positioned in described CNT semiconductor layer 1151 in institute
State in the projection on underlay substrate 12.
Described active layer 115 also includes the first doped amorphous silicon layer 1153 and the second doped amorphous silicon layer 1154, and described
One doped amorphous silicon layer 1153 is located between described source electrode 113 and described undoped amorphous silicon layer 1152, and described second doping is non-
Crystal silicon layer 1154 is located between described drain electrode 114 and described undoped amorphous silicon layer 1152, described first doped amorphous silicon layer
1153 are located at the two ends of described undoped amorphous silicon layer 1152 respectively with described second doped amorphous silicon layer 1154, and described first mixes
Miscellaneous amorphous silicon layer 1153 and described second doped amorphous silicon layer 1154 keep at a certain distance away setting.
Preferably, projection on described underlay substrate 12 for described first doped amorphous silicon layer 1153 and described source electrode 113
Projection on described underlay substrate 12 overlaps；Projection on described underlay substrate 12 for described second doped amorphous silicon layer 1154
Overlap with described drain electrode 114 projections on described underlay substrate.
Please refer to Fig. 3 to Fig. 6, the system of the thin-film transistor array base-plate providing for the present invention one better embodiment
Make method, the method comprises the steps：
Step 101, offer one underlay substrate 22.
Wherein, described underlay substrate 22 can for printing opacity (as glass, quartz or the like) or light tight (as chip, pottery
Porcelain or the like) rigid inorganic material, can also be the pliability organic material such as plastic cement, rubber, polyester or Merlon.
Step 102, multiple thin film transistor (TFT)s 21 are formed on described underlay substrate 22.Described thin film transistor (TFT) 21 includes grid
Pole 211 and gate insulator 212, source electrode 213, drain electrode 214 and active layer 215, described source electrode 213 and described drain electrode 214 are respectively
Contact with described active layer 215, described active layer 215 includes CNT semiconductor layer 2151 and undoped amorphous silicon layer
2152, described undoped amorphous silicon layer 2152 is located at described CNT semiconductor layer 2151 and described source electrode 213 and described leakage
Between pole 214.
Described grid 211 is located on described underlay substrate 22, and described gate insulator 212 covers described grid 211 and institute
State underlay substrate 22, described active layer 215 is located on described gate insulator 212 and is correspondingly arranged in the upper of described grid 211
Side, described source electrode 213 and described drain electrode 214 are located on described active layer 215 and are respectively arranged at the relative of described active layer 215
Two ends.
The step forming described thin film transistor (TFT) 21 is as follows：
Step 1021, refer to Fig. 3, described grid 211 is formed first on described underlay substrate 22 and covers described grid
The gate insulator 212 of pole 211 and described underlay substrate 22.Specifically, can be to form one the on described underlay substrate 22
One metal level and the first photoresist layer, and described the first metal layer is patterned by a mask plate, to obtain described grid 211, then
One gate insulator 212 is laid on described grid 211, makes described gate insulator 212 cover described grid 211 and described lining
Substrate 22.
Step 1022, refer to Fig. 4, described CNT semiconductor layer 2151 is formed on described gate insulator 212.
Specifically, can be that self-assembling technique, catalystic pyrolysis, the method such as laser evaporization method are passed through on described gate insulator 212
Form described CNT semiconductor layer 2151 in TFT channel position.
Step 1023, refers to Fig. 5, forms undoped amorphous silicon layer on described CNT semiconductor layer 2151
2152nd, the first doped amorphous silicon layer 2153 and the second doped amorphous silicon layer 2154.Specifically, can be in described underlay substrate 22
Upper formation undoped non-crystalline silicon and doped amorphous silicon respectively, then pass through the technique such as exposure and etching, to obtain described undoped
Amorphous silicon layer 2152, described first doped amorphous silicon layer 2153 and described second doped amorphous silicon layer 2154.Described first doping
Amorphous silicon layer 2153 and described second doped amorphous silicon layer 2154 are located at the two ends of described undoped amorphous silicon layer 2152, institute respectively
State the first doped amorphous silicon layer 2153 and described second doped amorphous silicon layer 2154 to keep at a certain distance away setting.
Described CNT semiconductor layer 2151, described undoped amorphous silicon layer 2152 and described first doped amorphous silicon layer
2153rd, described second doped amorphous silicon layer 2154 constitutes described active layer 215.
Projection on described underlay substrate 22 for the described CNT semiconductor layer 2151 and described undoped amorphous silicon layer
2152 projections on described underlay substrate 22 overlap.
Step 1024, refer to Fig. 6, respectively in described first doped amorphous silicon layer 2153 and described second doped amorphous silicon
Source electrode 213 and drain electrode 214 are formed on layer 2154.Specifically, can be that one layer of second metal is laid now on described underlay substrate
Layer, then passes through a mask plate and patterns second metal layer, to obtain described source electrode 213 and described drain electrode 214.
Described first doped amorphous silicon layer 1153 is located between described source electrode 113 and described undoped amorphous silicon layer 1152,
Described second doped amorphous silicon layer 1154 is located between described drain electrode 114 and described undoped amorphous silicon layer 1152.
Described source electrode 213 and described drain electrode 214 projections on described underlay substrate 22 are located at described undoped non-crystalline silicon
Layer 2152 in the projection on described underlay substrate, simultaneously as described CNT semiconductor layer 2151 is in described substrate base
Projection on described underlay substrate 22 overlaps with described undoped amorphous silicon layer 2152 for projection on plate 22, so described source electrode
213 and described drain electrode 214 projections on described underlay substrate 22 be similarly positioned in described CNT semiconductor layer 2151 in institute
State in the projection on underlay substrate 22.
Projection on described underlay substrate 12 for described first doped amorphous silicon layer 1153 and described source electrode 113 are in described lining
Projection on substrate 12 overlaps；Projection on described underlay substrate 12 for described second doped amorphous silicon layer 1154 and described leakage
Projection on described underlay substrate for the pole 114 overlaps.
Thin-film transistor array base-plate provided in an embodiment of the present invention, its manufacture method and display floater, in film crystal
The active layer being made up of CNT semiconductor layer and undoped amorphous silicon layer is set in pipe, and undoped amorphous silicon layer is set
It is placed between CNT semiconductor layer and source electrode and drain electrode.So, when thin film transistor (TFT) is opened, mainly pass through in active layer
CNT semiconductor layer conductive, CNT semiconductor layer has higher electron mobility, and forms larger ON state
Electric current, when thin film transistor (TFT) cuts out, leakage current is mainly discharged by the undoped amorphous silicon layer in active layer, has relatively
Little leakage current, so that thin film transistor (TFT) has higher switching current ratio.
The above is the preferred embodiment of the present invention it is noted that for those skilled in the art
For, on the premise of without departing from principle of the present invention, some improvements and modifications can also be made, these improvements and modifications
Should be regarded as protection scope of the present invention.
Claims (9)
1. a kind of thin-film transistor array base-plate, described thin-film transistor array base-plate includes underlay substrate and is located at described substrate
Multiple thin film transistor (TFT)s on substrate, described thin film transistor (TFT) includes grid on underlay substrate, gate insulator, source
Pole, drain electrode and active layer, described source electrode and described drain electrode contact with described active layer respectively it is characterised in that described active layer
Including CNT semiconductor layer and undoped amorphous silicon layer, described undoped amorphous silicon layer is located at described CNT quasiconductor
Between layer and described source electrode and described drain electrode.
2. thin-film transistor array base-plate as claimed in claim 1 is it is characterised in that described CNT semiconductor layer is in institute
Projection on described underlay substrate overlaps with described undoped amorphous silicon layer for the projection stating on underlay substrate, described source electrode and institute
State drain electrode and be located at described undoped amorphous silicon layer in the projection on described underlay substrate in the projection on described underlay substrate.
3. thin-film transistor array base-plate as claimed in claim 1 is it is characterised in that described active layer also includes the first doping
Amorphous silicon layer and the second doped amorphous silicon layer, described first doped amorphous silicon layer is located at described source electrode and described undoped non-crystalline silicon
Between layer, described second doped amorphous silicon layer is located between described drain electrode and described undoped amorphous silicon layer, and described first mixes
Miscellaneous amorphous silicon layer and the second doped amorphous silicon layer interval setting.
4. thin-film transistor array base-plate as claimed in claim 3 is it is characterised in that described first doped amorphous silicon layer is in institute
The projection on described underlay substrate overlaps with described source electrode to state projecting on underlay substrate；Described second doped amorphous silicon layer exists
Projection on described underlay substrate overlaps with described drain electrode for projection on described underlay substrate.
5. a kind of display device is it is characterised in that include the array base palte as described in Claims 1-4.
6. a kind of manufacture method of thin-film transistor array base-plate is it is characterised in that methods described includes：
One underlay substrate is provided；
Multiple thin film transistor (TFT)s are formed on described underlay substrate, described thin film transistor (TFT) includes grid and gate insulator, source
Pole, drain electrode and active layer, described source electrode is contacted with described active layer respectively with described drain electrode, and described active layer includes CNT
Semiconductor layer and undoped amorphous silicon layer, described undoped amorphous silicon layer is located at described CNT semiconductor layer and described source electrode
And described drain electrode between.
7. manufacture method as claimed in claim 6 is it is characterised in that described CNT semiconductor layer is in described underlay substrate
On projection the projection on described underlay substrate overlaps with described undoped amorphous silicon layer, described source electrode and described drain electrode
Projection on described underlay substrate is with described undoped amorphous silicon layer in the projection on described underlay substrate.
8. manufacture method as claimed in claim 6 also includes it is characterised in that forming described active layer：
Form the first doped amorphous silicon layer between described source electrode and described undoped amorphous silicon layer, non-with described in described drain electrode
Form the second doped amorphous silicon layer between doped amorphous silicon layer, and described first doped amorphous silicon layer and the second doped amorphous silicon layer
Interval setting.
9. manufacture method as claimed in claim 8 is it is characterised in that described first doped amorphous silicon layer is in described underlay substrate
On projection the projection on described underlay substrate overlaps with described source electrode；Described second doped amorphous silicon layer is in described substrate base
Projection on described underlay substrate overlaps with described drain electrode for projection on plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610916022.1A CN106409840B (en) | 2016-10-20 | 2016-10-20 | A kind of thin-film transistor array base-plate, its production method and display panel |
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| CN109301023A (en) * | 2018-09-30 | 2019-02-01 | 京东方科技集团股份有限公司 | Photodiode and preparation method thereof, flat panel detector |
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| CN101582451A (en) * | 2008-05-16 | 2009-11-18 | 清华大学 | Thin film transistor |
| CN102394242A (en) * | 2011-11-29 | 2012-03-28 | 武汉大学 | Amorphous indium zinc oxide/carbon nanotube composite film transistor and preparation method thereof |
| CN102983176A (en) * | 2011-08-03 | 2013-03-20 | 伊格尼斯创新公司 | Thin film transistor including a nanoconductor layer |
| CN104779301A (en) * | 2015-04-24 | 2015-07-15 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method thereof, array substrate and display device |
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| CN101582451A (en) * | 2008-05-16 | 2009-11-18 | 清华大学 | Thin film transistor |
| CN102983176A (en) * | 2011-08-03 | 2013-03-20 | 伊格尼斯创新公司 | Thin film transistor including a nanoconductor layer |
| CN102394242A (en) * | 2011-11-29 | 2012-03-28 | 武汉大学 | Amorphous indium zinc oxide/carbon nanotube composite film transistor and preparation method thereof |
| CN104779301A (en) * | 2015-04-24 | 2015-07-15 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method thereof, array substrate and display device |
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