TW201721863A - Display device - Google Patents

Abstract

A display device is provided, which includes a substrate structure having a substrate with a plurality of pixels, and each of the pixels includes an apeture region. A metal oxide transistor is disposed on the substrate and includes a metal oxide semiconductor layer with a first channel region, a first gate electrode corresponding to the first channel region, and a silicon oxide insulating layer on the metal oxide semiconductor layer. The silicon oxide insulating layer includes an opening corresponding to the aperture region. A polysilicon transistor is disposed on the substrate. The display device also includes an opposite substrate structure, and a display media between the substrate structure and the opposite substrate structure.

Description

Display device

The present disclosure relates to display devices, and more particularly to their array substrate structures.

At present, the conventional thin film liquid crystal display (TFT-LCD) process can be divided into three major processes, the first segment is an array (Array) substrate process for driving and display signals, and the color filter substrate process, and the second segment is liquid crystal control. Filled and sealed liquid crystal panel (Cell) process; the third section is a modular assembly process of polarizer, backlight module and liquid crystal panel assembly. In the array substrate process, a hafnium oxide layer and a tantalum nitride layer are often used as an insulating layer between different conductive layers. However, the refractive index of the yttrium oxide layer and the tantalum nitride layer are different, and the interface between the two is easy to partially reflect light and cannot pass through completely. As a result, the aperture ratio of the pixel opening region of the array substrate is lowered.

In summary, there is a need for a new array substrate structure to overcome the above problems.

A display device according to an embodiment of the present invention includes: a substrate structure including: a substrate having a pixel, and the pixel has an open region; a metal oxide transistor disposed on the substrate and including: a metal oxide semiconductor layer having a first channel region; a first gate corresponding to the first channel region; and a yttria insulating layer on the metal oxide semiconductor layer, wherein the yttrium oxide insulating layer has an opening, and the opening is disposed corresponding to the open region; and the polysilicon transistor, Provided on the substrate; the opposite substrate structure; The display medium is located between the substrate structure and the opposite substrate structure.

A display device according to an embodiment of the present invention includes: a substrate structure including: a substrate having a pixel, and the pixel has an open region; a metal oxide transistor disposed on the substrate and including: a metal oxide semiconductor layer having a first channel region; a first gate corresponding to the first channel region; and a gate insulating layer between the first gate and the metal oxide semiconductor layer, wherein the gate insulating layer comprises a first layer of tantalum nitride a ruthenium oxide layer, the first ruthenium oxide layer is between the first tantalum nitride layer and the metal oxide semiconductor layer; the polycrystalline germanium transistor is disposed on the substrate; and the tantalum nitride insulating layer is located at the metal oxide transistor and the polysilicon The transistor, wherein the tantalum nitride insulating layer in the open region directly contacts the first tantalum nitride layer; the opposite substrate structure; and the display medium is located between the substrate structure and the opposite substrate structure.

14‧‧‧Lighting layer

10a‧‧‧Photo District

10b‧‧‧Drive circuit

11a‧‧‧Metal oxide crystal

11n, 11p‧‧‧ polycrystalline germanium transistors

11o‧‧‧Open area

13‧‧‧Substrate

15, 15a, 15b, 19a, 19b, 19c‧‧‧ buffer layer

17‧‧‧Polysilicon layer

17c‧‧‧Channel area

17d‧‧‧Bungee Area

17s‧‧‧ source area

21d, 29d, 43d‧‧‧ bungee

21s, 29s, 43s‧‧‧ source

21, 29g‧‧ ‧ gate

21', 29L3‧‧ ‧ gate line

23, 25‧‧‧ Interlayer dielectric layer

27‧‧‧Metal oxide semiconductor layer

29c‧‧‧Contact

29h, 43h, 45h‧‧‧through holes

29L1, 45L1, 45L3‧‧‧ source line

29L2, 45L2, 45L4‧‧‧汲polar line

31, 31a, 31b, 31c, 35, 35a, 35b, 41‧‧ ‧ insulation

32‧‧‧Back exposure process

33‧‧‧ openings

37‧‧‧Organic insulation

39‧‧‧Common electrode

43p‧‧‧ pixel electrodes

51‧‧‧Amorphous layer

53‧‧‧Doped layer

100a, 100b, 100c, 100d, 100e, 100f, 100g, 100h, 100i, 100j, 100k, 100l, 100m, 100n, 100o, 100p, 100q, 100r, 210a‧‧‧ array substrate structure

210b‧‧‧Display media

210c‧‧‧ opposite substrate structure

1 to 8 and 12 to 19 are cross-sectional views showing the structure of the array substrate in the embodiment of the present disclosure.

9A to 9J, 10A to 10C, and 11A to 11B are process cross-sectional views of the array substrate structure in the disclosed embodiment.

Figure 20 is a cross-sectional view showing the design of the bottom gate of both the polycrystalline germanium transistor and the metal oxide transistor in the embodiment of the present disclosure.

Figure 21 is a schematic view of a display device in an embodiment of the present disclosure.

Polycrystalline germanium transistors have high turn-on current (Ion) and high carrier mobility, while metal oxide semiconductor transistors have low turn-off current (Ioff) and good uniformity. The present disclosure integrates the above two, and simultaneously uses polycrystalline germanium transistors and gold in the panel. It is an oxide semiconductor transistor and is disposed in a display panel in accordance with the use characteristics of the transistor. For example, in a driving circuit, a polycrystalline germanium transistor and a metal oxide semiconductor transistor are simultaneously used, and the relative position may be a vertical connection or a horizontal electrical connection to form a desired circuit structure; or a polycrystalline germanium may be used in a pixel region. The transistor and the metal oxide semiconductor transistor can be used as circuit design for switching and compensation.

In the following embodiments, a polycrystalline germanium transistor is used in the driving circuit, and a metal oxide transistor is used in the pixel region to have both advantages.

In one embodiment, a cross-sectional view of the array substrate structure 100a is shown in FIG. In Fig. 1, the array substrate structure 100a is divided into a plurality of pixel regions 10a and a driving circuit 10b. Each of the pixel regions 10a has a metal oxide transistor 11a and an open region 11o, and the driving circuit 10b includes an n-type polycrystalline germanium transistor 11n and a p-type polycrystalline germanium transistor 11p. In other embodiments, the driver circuit 10b may have only an n-type polysilicon transistor 11n, or a p-type polysilicon transistor 11p, as desired. The array substrate structure 100a includes a substrate 13 which is a transparent material such as glass or plastic. The light shielding layer 14 is located on the substrate 13 and corresponds to the polysilicon layer 17 of the polycrystalline germanium transistors 11n and 11p and the metal oxide semiconductor layer 27 of the metal oxide transistor 11a, respectively, which may be made of a black resin or a metal such as chromium, and formed thereof. The method can be patterned by sputtering, layering, and the like by a process such as photolithography. The buffer layer 15 is located on the light shielding layer 14 and may be made of tantalum nitride, and may be formed by chemical vapor deposition (CVD). The buffer layer 19a is located on the buffer layer 15, and may be made of ruthenium oxide, and may be formed by chemical vapor deposition. The polysilicon layer 17 is located on the buffer layer 19a and corresponds to the polycrystalline germanium transistors 11n and 11p, and the material thereof may be a low temperature polysilicon (LTPS) layer. In one embodiment, after forming the polysilicon layer 17, the opaque photoresist pattern (not shown) formed by the lithography process can be used to protect the intermediate channel region 17c, and the ions are ionized to the sides of the channel region 17c to define the source region 17s. / bungee area 17d. The shading photoresist pattern can then be removed as appropriate, either by wet or dry stripping.

The buffer layer 19b is located on the polysilicon layer 17 and the buffer layer 19a, and may be made of ruthenium oxide, and may be formed by CVD. The gate 21 is located on the buffer layer 19b and may be made of a metal. The method is formed by sputtering a layer and then patterning by a process such as photolithography. For the polysilicon transistors 11n and 11p, the gate 21 corresponds to the channel region 17c, and the gate insulating layer between the channel region 17c and the gate 21 is the buffer layer 19b. The interlayer dielectric layer 23 is located on the gate 21 and the buffer layer 19b, and may be made of tantalum nitride, and may be formed by CVD. The interlayer dielectric layer 25 is located on the interlayer dielectric layer 23 and may be made of ruthenium oxide, and may be formed by CVD.

The metal oxide semiconductor layer 27 is located on the interlayer dielectric layer 25 and corresponds to the gate 21 of the metal oxide transistor 11a. The material thereof may be indium gallium zinc oxide (IGZO), and the formation method thereof may be micro-sputtering and layering. Process etching such as shadow etching. It is to be noted that the channel region of the metal oxide semiconductor layer 27 should not be exposed or contact with the tantalum nitride layer to avoid conversion from a semiconductor to a conductor. For the metal oxide transistor 11a, the gate insulating layer between the channel region (metal oxide semiconductor layer 27) and the gate 21 is interlayer dielectric layers 23 and 25, such as a hafnium oxide layer and a tantalum nitride layer. The double layer structure and the ruthenium oxide layer are located between the tantalum nitride layer and the metal oxide semiconductor layer 27. It should be noted that if the gate insulating layer is arranged in the reverse order (for example, the tantalum nitride layer is located between the tantalum oxide layer and the metal oxide semiconductor layer 27), the metal oxide semiconductor layer 27 will contact the tantalum nitride layer. Electrical performance is not good.

The source line 29L1, the drain line 29L2, the source 29s, and the drain 29d are formed on the interlayer dielectric layer 25. The source line 29L1 is located on the source region 17s, and is connected between the interlayer dielectric layer 25, the interlayer dielectric layer 23, and the via hole 29h of the buffer layer 19b. The drain line 29L2 is located on the drain region 17d, and passes between the interlayer dielectric layers 25, The interlayer dielectric layer 23 is connected to the via hole 29h of the buffer layer 19b. The source 29s and the drain 29d are respectively located on both sides of the metal oxide semiconductor layer 27. The through hole 29h can be formed by lithography and etching through the interlayer dielectric layer 27, the interlayer dielectric layer 25, and the buffer layer 19b to form a hole, and then filling the hole into the hole and layering the interlayer dielectric layer 27. Next, the metal layer is patterned by a process such as photolithography to define a source line 29L1, a drain line 29L2, a source 29s, and a drain 29d.

The insulating layer 31 is located on the interlayer dielectric layer 25, the metal oxide semiconductor layer 27, the source line 29L1, the drain line 29L2, the source 29s, and the drain 29d. The material thereof may be ruthenium oxide, and the formation method may be CVD. . The insulating layer 31 and the interlayer dielectric layer 25 have openings 33 corresponding to the opening regions 11o, which may be formed by a photolithography process. It should be noted that the exposure step in the above lithography process may be upwardly exposed from below, and the exposure step uses the light shielding layer 14, the source line 29L1, the drain line 29L2, the source 29s, and the drain 29d as a mask, that is, A mask can be omitted to save costs. After the lithography and etching process in the exposure direction, the edges of the ruthenium oxide layer such as the insulating layer 31 and the interlayer dielectric layer 25 are aligned with the edges of the mask. Since the gate 21 of the metal oxide transistor 11a itself can be shielded from light, the light shielding layer 14 in the metal oxide transistor 11a can be omitted as appropriate. In some embodiments, the opening 33 can extend further down through the interlayer dielectric layer 23, the buffer layer 19b, the buffer layer 19a, and even the buffer layer 15.

The insulating layer 35 is located in the insulating layer 31 and the opening 33, and the material thereof may be tantalum nitride, which may be formed by CVD. In this embodiment, the insulating layer 35 can directly contact the interlayer dielectric layer 23 via the opening 33. The organic insulating layer 37 is located on the insulating layer 35, and the forming method may be an spin coating method to provide an insulating surface for subsequent film lamination. The common electrode 39 is located on the organic insulating layer 37, and mainly corresponds to the pixel region 10a. The material of the common electrode 39 may be a transparent conductive material such as indium tin oxide (ITO), which may be formed by sputtering. After plating, the layer is patterned by a process such as photolithography. The insulating layer 41 is located on the common electrode 39 and the organic insulating layer 37, and may be made of tantalum nitride, and may be formed by CVD.

The pixel electrode 43p is located on the insulating layer 41. The partial pixel electrode 43p is located on the drain electrode 29d, and is connected between the insulating layer 41, the organic insulating layer 37, the insulating layer 35, and the through hole 43h of the insulating layer 31. The through hole 43h can be formed by lithography and etching through the insulating layer 41, the organic insulating layer 37, the insulating layer 35, and the insulating layer 31, and a transparent conductive material such as ITO is filled into the hole and layered on the insulating layer 41. on. Then, patterning is performed by a process such as photolithography to define the pixel electrode 43p.

The polysilicon transistors 11n and 11p of the driving circuit 10b in Fig. 1 belong to the top gate structure, and the metal oxide transistor 11a belongs to the bottom gate structure. In Fig. 1, a ruthenium oxide layer (e.g., insulating layer 31) on the metal oxide semiconductor layer 27, and ruthenium oxide interposed in the gate insulating layer interposed between the metal oxide semiconductor layer 27 and the gate electrode 21 The layer (such as the interlayer dielectric layer 25) has an opening 33 corresponding to the opening region 11o to reduce the number of interfaces between the yttrium oxide layer and the tantalum nitride layer in the opening region 11o, thereby improving the light transmittance of the array substrate structure 100a. It should be noted that the opening 33 may be formed in the driving circuit 10b in addition to the opening region 11o of the pixel region 10a, depending on the reticle design.

In the following embodiments, the same reference numerals are used for the elements of the foregoing embodiments, and the details are not described herein. In an embodiment, a cross-sectional view of the array substrate structure 100b is shown in FIG. In Fig. 2, the relative positions of the pixel region 10a, the driving circuit 10b, the metal oxide transistor 11a, the opening region 11o, and the polysilicon transistors 11n and 11p are similar to those of Fig. 1. The light shielding layer 14 is located on the substrate 13 and corresponds to the polysilicon layer 17 of the polycrystalline germanium transistors 11n and 11p and the metal oxide semiconductor layer 27 of the metal oxide transistor 11a, respectively. The buffer layer 15 is located on the light shielding layer 14, and the buffer layer 19a is located on the buffer layer 15. Polycrystalline germanium layer 17 (such as source region 17s, The channel region 17c and the drain region 17d) are located on the buffer layer 19a and correspond to the polysilicon transistors 11n and 11p. The buffer layer 19b is located on the polysilicon layer 17 and the buffer layer 19a, and the gate 21 is located on the buffer layer 19b. For the polysilicon transistors 11n and 11p, the gate 21 is located on the channel region 17c with a gate insulating layer such as a buffer layer 19b.

The interlayer dielectric layer 23 is on the gate 21, and the interlayer dielectric layer 25 is on the interlayer dielectric layer 23. The metal oxide semiconductor layer 27 is on the interlayer dielectric layer 25 and corresponds to the gate 21 of the metal oxide transistor 11a. For the metal oxide transistor 11a, the gate insulating layer between the channel region (metal oxide semiconductor layer 27) and the gate 21 is the interlayer dielectric layers 23 and 25. The source line 29L1, the drain line 29L2, the source 29s, and the drain 29d are located on the interlayer dielectric layer 25. The source line 29L1 is located on the source region 17s, and is connected between the interlayer dielectric layer 25, the interlayer dielectric layer 23, and the via hole 29h of the buffer layer 19b. The drain line 29L2 is located on the drain region 17d, and is connected between the interlayer dielectric layer 25, the interlayer dielectric layer 23, and the via hole 29h of the buffer layer 19b. The source 29s and the drain 29d are respectively located on both sides of the metal oxide semiconductor layer 27.

The interlayer dielectric layer 25 has an opening 33 corresponding to the opening region 11o, and the forming method thereof may be a photolithography etching process. It should be noted that the exposure step in the above lithography process may be upwardly exposed from below, and the exposure step uses the light shielding layer 14, the source line 29L1, the drain line 29L2, the source 29s, and the drain 29d as a mask, that is, A mask can be omitted to save costs. After the lithography and etching process in this exposure direction, the edges of the interlayer dielectric layer 25 (yttria layer) will be aligned with the edges of the mask. Since the gate 21 of the metal oxide transistor 11a itself can be shielded from light, the light shielding layer 14 in the metal oxide transistor 11a can be omitted as appropriate. In some embodiments, the opening 33 can extend further down through the interlayer dielectric layer 23, the buffer layer 19b, the buffer layer 19a, and even the buffer layer 15.

The organic insulating layer 37 is located in the interlayer dielectric layer 25, the metal oxide semiconductor layer 27, the source line 29L1, the drain line 29L2, the source 29s, the drain 29d, and the opening 33. The common electrode 39 is located on the organic insulating layer 37, and mainly corresponds to the pixel region 10a. The insulating layer 41 is located on the common electrode 39 and the organic insulating layer 37. The pixel electrode 43p is located on the insulating layer 41. The partial pixel electrode 43p is located on the drain electrode 29d, and is connected to the through hole 43h of the organic insulating layer 37 through the insulating layer 41 therebetween. In this embodiment, the organic insulating layer 37 may directly contact the interlayer dielectric layer 23 via the opening 33. The polycrystalline germanium transistors 11n and 11p of the driving circuit 10b in Fig. 2 belong to the top gate structure, and the metal oxide transistor 11a belongs to the bottom gate structure. In FIG. 2, a ruthenium oxide layer (such as the interlayer dielectric layer 25) interposed between the MOS insulating layer 27 and the gate insulating layer 21 has an opening 33 corresponding to the opening region 11o to reduce the opening. The number of interfaces between the ruthenium oxide layer and the tantalum nitride layer in the region 11o, thereby improving the light transmittance of the array substrate structure 100b.

In an embodiment, a cross-sectional view of the array substrate structure 100c is shown in FIG. In Fig. 3, the relative positions of the pixel region 10a, the driving circuit 10b, the metal oxide transistor 11a, the opening region 11o, and the polysilicon transistors 11n and 11p are similar to those of Fig. 1. The light shielding layer 14 is located on the substrate 13 and corresponds to the polysilicon layer 17 of the polycrystalline germanium transistors 11n and 11p and the metal oxide semiconductor layer 27 of the metal oxide transistor 11a, respectively. In this embodiment, the light shielding layer 14 corresponding to the metal oxide transistor is simultaneously used as the gate of the metal oxide transistor. Therefore, the material of the light shielding layer 14 must be a conductive material such as metal, and the formation method can be performed by depositing a layer. Process patterning such as lithography etching.

The buffer layer 15 is located on the substrate 13 and the light shielding layer 14, the buffer layer 19a is located on the buffer layer 15, and the polysilicon layer 17 (such as the source region 17s, the channel region 17c, and the drain region 17d) is located on the buffer layer 19a and corresponds to the polysilicon layer. The transistors 11n and 11p. The buffer layer 19b is located on the polysilicon layer 17 and the buffer layer 19a, and the gate 21 and the gate line 21' are located on the buffer layer 19b. For the polysilicon transistors 11n and 11p, the gate 21 is located on the channel region 17c with a gate insulating layer such as a buffer layer 19b. In the metal oxide transistor 11a, the gate line 21' and the light shielding layer 14 are connected to each other through the buffer holes 19b, 19a and the through holes 21h of 15. The via hole 21h may be formed by forming a opening through the buffer layers 19b, 19a, and 15 by a lithography and etching process, and depositing a metal filling opening and layering on the buffer layer 19b. The gate layer 21 and the gate line 21' are formed by patterning the metal layer on the buffer layer 19b by a photolithography process.

The interlayer dielectric layer 23 is located on the gate 21, the gate line 21', and the buffer layer 19b. The interlayer dielectric layer 25 is on the interlayer dielectric layer 23. The metal oxide semiconductor layer 27 is on the interlayer dielectric layer 25 and corresponds to the gate of the metal oxide transistor 11a (light shielding layer 14 / gate 21). For the metal oxide transistor 11a, the gate insulating layer between the channel region (metal oxide semiconductor layer 27) and the gate (light shielding layer 14 / gate 21) is an interlayer dielectric layer 25, an interlayer dielectric layer 23. A buffer layer 19b, a buffer layer 19a, and a buffer layer 15. The source line 29L1, the drain line 29L2, the source 29s, and the drain 29d are located on the interlayer dielectric layer 25. The source line 29L1 is located on the source region 17s, and is connected between the interlayer dielectric layer 25, the interlayer dielectric layer 23, and the via hole 29h of the buffer layer 19b. The drain line 29L2 is located on the drain region 17d, and is connected between the interlayer dielectric layer 25, the interlayer dielectric layer 23, and the via hole 29h of the buffer layer 19b. The source 29s and the drain 29d are respectively located on both sides of the metal oxide semiconductor layer 27.

The insulating layer 31 is located on the source line 29L1, the drain line 29L2, the source 29s, the drain 29d, the metal oxide semiconductor layer 27, and the interlayer dielectric layer 25. The insulating layer 31 and the interlayer dielectric layer 25 have openings 33 corresponding to the opening regions 11o, which may be formed by a photolithography process. It is worth noting that the exposure step in the above lithography process can be performed below. The exposure is upward, and the exposure step uses the light shielding layer 14, the source line 29L1, the drain line 29L2, and the source 29s as a mask, thereby omitting a mask and saving cost. After the lithography and etching process in this exposure direction, the edges of the insulating layer 31 and the interlayer dielectric layer 25 (yttria layer) will be aligned with the edges of the mask. In some embodiments, the opening 33 can extend further down through the interlayer dielectric layer 23, the buffer layer 19b, the buffer layer 19a, and even the buffer layer 15.

The insulating layer 35 is located in the insulating layer 31 and the opening 33 and contacts the interlayer dielectric layer 23. The organic insulating layer 37 is located on the insulating layer 35. The common electrode 39 is located on the organic insulating layer 37, and mainly corresponds to the pixel region 10a. The insulating layer 41 is located on the common electrode 39 and the organic insulating layer 37. The pixel electrode 43p is located on the insulating layer 41. The partial pixel electrode 43p is located on the drain electrode 29d, and is connected between the insulating layer 41, the organic insulating layer 37, the insulating layer 35, and the through hole 43h of the insulating layer 31. The polycrystalline germanium transistors 11n and 11p of the driving circuit 10b in Fig. 3 belong to the top gate structure, and the metal oxide transistor 11a belongs to the bottom gate structure. In FIG. 3, a ruthenium oxide layer (such as interlayer dielectric layer 25) interposed between a MOS insulating layer 27 and a gate insulating layer (such as interlayer dielectric layer 25), and a metal The yttrium oxide layer (such as the insulating layer 31) on the oxide semiconductor layer 27 has an opening 33 corresponding to the opening region 11o to reduce the number of interfaces between the yttrium oxide layer and the tantalum nitride layer in the opening region 11o, thereby improving the light of the array substrate structure 100c. Penetration.

In an embodiment, a cross-sectional view of the array substrate structure 100d is shown in FIG. In Fig. 4, the relative positions of the pixel region 10a, the driving circuit 10b, the metal oxide transistor 11a, the opening region 11o, and the polysilicon transistors 11n and 11p are similar to those of Fig. 1. The light shielding layer 14 is located on the substrate 13 and corresponds to the polysilicon layer 17 of the polycrystalline germanium transistors 11n and 11p and the metal oxide semiconductor layer 27 of the metal oxide transistor 11a, respectively. In this embodiment, the light shielding layer 14 of the metal oxide transistor serves as a gate at the same time. Therefore, the material of the light shielding layer 14 must be a conductive material such as metal.

The buffer layer 15 is located on the substrate 13 and the light shielding layer 14, and the buffer layer 19a is located on the buffer layer 15. The polysilicon layer 17 (e.g., the source region 17s, the channel region 17c, and the drain region 17d) is located on the buffer layer 19a and corresponds to the polysilicon transistors 11n and 11p. The metal oxide semiconductor layer 27 is on the buffer layer 19a and corresponds to the gate of the metal oxide transistor 11a (light shielding layer 14). The buffer layer 19b is located on the polysilicon layer 17, the metal oxide semiconductor layer 27, and the buffer layer 19a. The gate 21 and the gate line 21' are located on the buffer layer 19b, and the source 21s and the drain 21d pass through the buffer layer 19b to contact both sides of the metal oxide semiconductor layer 27. For the polysilicon transistors 11n and 11p, the gate 21 is located on the channel region 17c with a gate insulating layer such as a buffer layer 19b. For the metal oxide transistor 11a, the gate insulating layer between the channel region (metal oxide semiconductor layer 27) and the gate (light shielding layer 14) is the buffer layer 19a and the buffer layer 15. In the metal oxide transistor 11a, the gate line 21' and the light shielding layer 14 are connected to each other through the buffer holes 19b, 19a and the through holes 21h of 15.

The interlayer dielectric layer 23 is located on the gate 21, the gate line 21', the source 21s, the drain 21d, and the buffer layer 19b. The interlayer dielectric layer 25 is on the interlayer dielectric layer 23. The source line 29L1, the drain line 29L2, and the contact 29c are located on the interlayer dielectric layer 25. The source lines 29L1 of the polysilicon transistors 11n and 11p are located on the source region 17s, and are connected between the interlayer dielectric layer 25, the interlayer dielectric layer 23, and the via hole 29h of the buffer layer 19b. The gate lines 29L2 of the polycrystalline germanium transistors 11n and 11p are located on the drain region 17d, and are connected between the interlayer dielectric layer 25, the interlayer dielectric layer 23, and the via hole 29h of the buffer layer 19b. The source line 29L1 of the metal oxide transistor 11a is located on the source 21s, and is connected between the interlayer via holes 29h passing through the interlayer dielectric layer 25 and the interlayer dielectric layer 23. The contact 29c of the metal oxide transistor 11a is located on the drain 21d with the interlayer interposed therebetween. The electric layer 25 is connected to the through hole 29h of the interlayer dielectric layer 23.

The interlayer dielectric layer 25, the interlayer dielectric layer 23, the buffer layer 19b, and the buffer layer 19a have openings 33 corresponding to the opening regions 11o, which may be formed by a photolithography process. It should be noted that the exposure step in the above lithography process can be upwardly exposed from below, and the exposure step uses the light shielding layer 14, the source line 29L1, and the drain line 29L2 as a mask, thereby omitting a mask and saving cost. . After the lithography and etching process in this exposure direction, the edges of the interlayer dielectric layer 25, the buffer layer 19b, and the buffer layer 19a (the yttria layer) will be aligned with the edges of the mask. In some embodiments, the opening 33 can extend further down through the buffer layer 15.

The insulating layer 35 is located in the interlayer dielectric layer 25 and the opening 33 and contacts the buffer layer 15. The organic insulating layer 37 is located on the insulating layer 35. The common electrode 39 is located on the organic insulating layer 37, and mainly corresponds to the pixel region 10a. The insulating layer 41 is located on the common electrode 39 and the organic insulating layer 37. The pixel electrode 43p is located on the insulating layer 41. The partial pixel electrode 43p is located on the contact 29c, and is connected between the insulating layer 41, the organic insulating layer 37, and the through hole 43h of the insulating layer 35. The polycrystalline germanium transistors 11n and 11p of the driving circuit 10b in Fig. 4 belong to the top gate structure, and the metal oxide transistor 11a belongs to the bottom gate structure. In Fig. 4, a ruthenium oxide layer (e.g., buffer layers 19b and 19a) interposed in a gate insulating layer between the MOS layer 27 and the gate (light shielding layer 14), and a metal oxide semiconductor layer The yttrium oxide layer on 27 (such as the interlayer dielectric layer 25) has an opening 33 corresponding to the opening region 11o to reduce the number of interfaces between the yttrium oxide layer and the tantalum nitride layer in the opening region 11o, thereby improving light penetration of the array substrate structure 100d. degree.

In an embodiment, a cross-sectional view of the array substrate structure 100e is shown in FIG. In Fig. 5, the relative positions of the pixel region 10a, the driving circuit 10b, the metal oxide transistor 11a, the opening region 11o, and the polysilicon transistors 11n and 11p are the same as those in the first pattern. like. The light shielding layer 14 is located on the substrate 13 and corresponds to the polysilicon layer 17 of the polycrystalline germanium transistors 11n and 11p and the metal oxide semiconductor layer 27 of the metal oxide transistor 11a, respectively. In this embodiment, the light shielding layer 14 of the metal oxide transistor serves as a gate at the same time, and therefore the material of the light shielding layer 14 must be a conductive material such as metal.

The buffer layer 15 is located on the substrate 13 and the light shielding layer 14. The polysilicon layer 17 (e.g., the source region 17s, the channel region 17c, and the drain region 17d) is located on the buffer layer 15 and corresponds to the polysilicon transistors 11n and 11p. The buffer layer 19b is located on the polysilicon layer 17 and the buffer layer 19a. The gate 21 and the gate line 21' are located on the buffer layer 19b. For the polysilicon transistors 11n and 11p, the gate 21 is located on the channel region 17c with a gate insulating layer such as a buffer layer 19b. In the metal oxide transistor 11a, the gate line 21' and the light shielding layer 14 are connected to each other through the buffer holes 19b, 19a and the through holes 21h of 15. The metal oxide semiconductor layer 27 is on the buffer layer 19b and corresponds to the gate of the metal oxide transistor 11a (light shielding layer 14). For the metal oxide transistor 11a, the gate insulating layer between the channel region (metal oxide semiconductor layer 27) and the gate (light shielding layer 14) is the buffer layers 19b, 19a, and 15.

The interlayer dielectric layer 25 is located on the buffer layer 19b, the gate 21, the gate line 21', and the metal oxide semiconductor layer 27. The interlayer dielectric layer 25, the buffer layer 19b, and the buffer layer 19a have openings 33 corresponding to the opening regions 11o, and the formation method thereof may be a photolithography etching process. It should be noted that the exposure step in the above lithography process can be upwardly exposed from below, and the exposure step uses the light shielding layer 14, the source line 29L1, the drain line 29L2, and the gate line 21' as a mask. Save money by omitting a mask. After the lithography and etching process in this exposure direction, the edges of the interlayer dielectric layer 25, the buffer layer 19b, and the buffer layer 19a (the yttria layer) will be aligned with the edges of the mask. In some embodiments, the opening 33 can extend further down through the buffer layer 15.

The interlayer dielectric layer 23 is located in the interlayer dielectric layer 25 and the opening 33 and contacts the buffer layer 15. The source line 29L1, the drain line 29L2, and the contact 29c are located on the interlayer dielectric layer 23. The source lines 29L1 of the polysilicon transistors 11n and 11p are located on the source region 17s, and are connected to each other through the interlayer dielectric layer 23, the interlayer dielectric layer 25, and the via hole 29h of the buffer layer 19b. The gate lines 29L2 of the polycrystalline germanium transistors 11n and 11p are located on the drain region 17d, and are connected to each other through the interlayer dielectric layer 23, the interlayer dielectric layer 25, and the via hole 29h of the buffer layer 19b. The source line 29L1 of the metal oxide transistor 11a is located on one side of the metal oxide semiconductor layer 27, and is connected between the interlayer via holes 29h passing through the interlayer dielectric layer 23 and the interlayer dielectric layer 25. The contact 29c of the metal oxide transistor 11a is located on the other side of the metal oxide semiconductor layer 27, and is connected between the interlayer via holes 29h passing through the interlayer dielectric layer 23 and the interlayer dielectric layer 25.

The insulating layer 35 is located on the source line 29L1, the drain line 29L2, the contact 29c, and the interlayer dielectric layer 23. The organic insulating layer 37 is located on the insulating layer 35. The common electrode 39 is located on the organic insulating layer 37, and mainly corresponds to the pixel region 10a. The insulating layer 41 is located on the common electrode 39 and the organic insulating layer 37. The pixel electrode 43p is located on the insulating layer 41. The partial pixel electrode 43p is located on the contact 29c, and is connected between the insulating layer 41, the organic insulating layer 37, and the through hole 43h of the insulating layer 35. The polysilicon transistors 11n and 11p of the driving circuit 10b in Fig. 5 belong to the top gate structure, and the metal oxide transistor 11a belongs to the bottom gate structure. In Fig. 5, a ruthenium oxide layer (e.g., buffer layers 19b and 19a) interposed in a gate insulating layer between the MOS layer 27 and the gate (light shielding layer 14), and a metal oxide semiconductor layer The yttrium oxide layer on 27 (such as the interlayer dielectric layer 25) has an opening 33 corresponding to the opening region 11o to reduce the number of interfaces between the yttrium oxide layer and the tantalum nitride layer in the opening region 11o, thereby improving light penetration of the array substrate structure 100e. degree.

In an embodiment, a cross-sectional view of the array substrate structure 100f is as shown in FIG. Shown. In Fig. 6, the relative positions of the pixel region 10a, the driving circuit 10b, the metal oxide transistor 11a, the opening region 11o, and the polysilicon transistors 11n and 11p are similar to those of Fig. 1. The light shielding layer 14 is located on the substrate 13 and corresponds to the polysilicon layer 17 of the polycrystalline germanium transistors 11n and 11p and the metal oxide semiconductor layer 27 of the metal oxide transistor 11a, respectively. In this embodiment, the light shielding layer 14 of the metal oxide transistor serves as a gate at the same time, and therefore the material of the light shielding layer 14 must be a conductive material such as metal.

The buffer layer 19a is located on the substrate 13 and the light shielding layer 14, the buffer layer 15 is on the buffer layer 19a, and the buffer layer 19b is on the buffer layer 15. The polysilicon layer 17 (e.g., the source region 17s, the channel region 17c, and the drain region 17d) is located on the buffer layer 19b and corresponds to the polysilicon transistors 11n and 11p. The buffer layer 19c is located on the polysilicon layer 17 and the buffer layer 19b, and may be made of ruthenium oxide, and may be formed by CVD. The gate 21, the source 21s, and the drain 21d are located on the buffer layer 19b, and the material thereof may be metal. The method may be formed by depositing a layer and then patterning by a process such as photolithography. For the polysilicon transistors 11n and 11p, the gate 21 is located on the channel region 17c with a gate insulating layer such as a buffer layer 19c interposed therebetween. The metal oxide semiconductor layer 27 is located on the buffer layer 19b between the source 21s and the drain 21d and corresponds to the gate of the metal oxide transistor 11a (light shielding layer 14). For the metal oxide transistor 11a, the gate insulating layer between the channel region (metal oxide semiconductor layer 27) and the gate (light shielding layer 14) is the buffer layers 19c, 19b, 15, and 19a.

The interlayer dielectric layer 25 is located on the buffer layer 19c, the gate 21, the source 21s, the drain 21d, and the metal oxide semiconductor layer 27. The interlayer dielectric layer 25, the buffer layer 19c, the buffer layer 19b, the buffer layer 15, and the buffer layer 19a have openings 33 corresponding to the opening regions 11o, which may be formed by a photolithography process. It should be noted that the exposure step in the above lithography process can be exposed upward from the bottom, and the exposure step uses the light shielding layer 14 and the source. Since the polar line 29L1, the drain line 29L2, the source 21s, and the drain 21d serve as a mask, a mask can be omitted and cost can be saved. After the lithography and etching process in this exposure direction, the edges of the interlayer dielectric layer 25, the buffer layer 19c, the buffer layer 19b, and the buffer layer 19a (the yttria layer) will be aligned with the edges of the mask.

The interlayer dielectric layer 23 is located in the interlayer dielectric layer 25 and the opening 33 and contacts the substrate 13. The source line 29L1, the drain line 29L2, and the contact 29c are located on the interlayer dielectric layer 23. The source lines 29L1 of the polysilicon transistors 11n and 11p are located on the source region 17s, and are connected between the interlayer dielectric layer 23, the interlayer dielectric layer 25, and the via hole 29h of the buffer layer 19c. The gate lines 29L2 of the polycrystalline germanium transistors 11n and 11p are located on the drain region 17d, and are connected between the interlayer dielectric layer 23, the interlayer dielectric layer 25, and the via hole 29h of the buffer layer 19c. The source line 29L1 of the metal oxide transistor 11a is located on the source 21s, and is connected between the interlayer via holes 29h passing through the interlayer dielectric layer 23 and the interlayer dielectric layer 25. The contact 29c of the metal oxide transistor 11a is located on the drain 21d, and is connected between the interlayer via hole 29h passing through the interlayer dielectric layer 23 and the interlayer dielectric layer 25.

The insulating layer 35 is located on the source line 29L1, the drain line 29L2, the contact 29c, and the interlayer dielectric layer 23. The organic insulating layer 37 is located on the insulating layer 35. The common electrode 39 is located on the organic insulating layer 37, and mainly corresponds to the pixel region 10a. The insulating layer 41 is located on the common electrode 39 and the organic insulating layer 37. The pixel electrode 43p is located on the insulating layer 41. The partial pixel electrode 43p is located on the contact 29c, and is connected between the insulating layer 41, the organic insulating layer 37, and the through hole 43h of the insulating layer 35. The polycrystalline germanium transistors 11n and 11p of the driving circuit 10b in Fig. 6 belong to the top gate structure, and the metal oxide transistor 11a belongs to the bottom gate structure. In Fig. 6, a ruthenium oxide layer (e.g., buffer layers 19c, 19b, and 19a) interposed in a gate insulating layer between the metal oxide semiconductor layer 27 and the gate (light shielding layer 14), and metal oxide a ruthenium oxide layer on the semiconductor layer 27 (eg, interlayer dielectric layer 25) The opening 33 corresponds to the opening region 11o to reduce the number of interfaces between the yttrium oxide layer and the tantalum nitride layer in the opening region 11o, thereby improving the light transmittance of the array substrate structure 100f.

In an embodiment, a cross-sectional view of the array substrate structure 100g is shown in FIG. In Fig. 7, the relative positions of the metal oxide transistor 11a, the opening region 11o, and the n-type polysilicon transistor 11n are similar to those of Fig. 1. This embodiment may further comprise a p-type polycrystalline germanium transistor 11p, or a n-type polycrystalline germanium transistor 11n may be replaced with a p-type polycrystalline germanium transistor 11p, as desired. The buffer layer 15 is on the substrate 13, and the buffer layer 19a is on the buffer layer 15. The polysilicon layer 17 (e.g., the source region 17s, the channel region 17c, and the drain region 17d) is located on the buffer layer 19a and corresponds to the polycrystalline germanium transistor 11n. The buffer layer 19b is formed on a portion of the polysilicon layer 17, and the gate 21 is formed on the buffer layer 19b. For the polysilicon transistor 11n, the gate 21 is located on the channel region 17c, and is separated by a gate insulating layer such as a buffer layer 19b. The interlayer dielectric layer 23 is located on the gate 21, the source region 17s, the drain region 17d, and the buffer layer 19a. The interlayer dielectric layer 25 is on the interlayer dielectric layer 23.

The contact 29c, the gate line 29L3, and the gate 29g are located on the interlayer dielectric layer 23. The contact 29c of the polysilicon transistor 11n is located on the source region 17s (or the drain region 17d), and is connected between the via holes 29h passing through the interlayer dielectric layers 25 and 23. The gate line 29L3 of the polysilicon transistor 11n is located on the gate 21, and is connected between the through holes 29h passing through the interlayer dielectric layers 25 and 23.

The insulating layer 35a is located on the contact 29c, the gate line 29L3, and the gate 29g, and the material thereof may be tantalum nitride, and the formation method may be CVD. The insulating layer 31a is located on the insulating layer 35a, and the material thereof may be yttrium oxide, and the forming method may be CVD. The metal oxide semiconductor layer 27 is on the insulating layer 31a and corresponds to the gate 29g of the metal oxide transistor 11a. Channel region (metal oxide) for metal oxide transistor 11a The gate insulating layer between the semiconductor layer 27) and the gate 29g is an insulating layer 31a and 35a. The source 43s and the drain 43d are respectively located on both sides of the metal oxide semiconductor layer 27, and the material thereof may be metal, and the forming method may be patterning by sputtering, layering, and the like by a process such as lithography and etching. The insulating layer 31b is located on the source electrode 43s, the drain electrode 43d, the metal oxide semiconductor layer 27, and the insulating layer 31a. The material thereof may be ruthenium oxide, and the formation method may be CVD. The insulating layers 31a and 31b have openings 33 corresponding to the opening regions 11o, which may be formed by a photolithography process. In some embodiments, the opening 33 can further pass down through the insulating layer 35a, the interlayer dielectric layer 25, the interlayer dielectric layer 23, the buffer layer 19a, or even the buffer layer 15.

The insulating layer 35b is located inside the insulating layer 31b and the opening 33 and contacts the insulating layer 35a. The material of the insulating layer 35b may be tantalum nitride, and the forming method may be CVD. The organic insulating layer 37 is on the insulating layer 35b, and the insulating layer 41 is on the organic insulating layer 37. The source line 45L1 and the drain line 45L2 are located on the insulating layer 41, and the material thereof may be a metal, an alloy, or other conductive material. The source line 45L1 of the polycrystalline germanium transistor 11n is located on the contact 29c on the left side with the insulating layer 41, the organic insulating layer 37, the insulating layer 35b, the insulating layer 31b, the insulating layer 31a, and the insulating layer 35a interposed therebetween. The through holes 45h are connected. The drain line 45L2 of the polycrystalline germanium transistor 11n is located on the contact 29c on the right side with the insulating layer 41, the organic insulating layer 37, the insulating layer 35b, the insulating layer 31b, the insulating layer 31a, and the insulating layer 35a interposed therebetween. The through holes 45h are connected. The source line 45L3 of the metal oxide transistor is located on the source electrode 43s, and is connected between the insulating layer 41, the organic insulating layer 37, the insulating layer 35b, and the through hole 45h of the insulating layer 31b. The drain line 45L4 of the metal oxide transistor is located on the drain electrode 43d, and is connected between the insulating layer 41, the organic insulating layer 37, the insulating layer 35b, and the via hole 45h of the insulating layer 31b.

In Fig. 7, the polycrystalline germanium transistor 11n belongs to the top gate structure, and the metal The oxide transistor 11a belongs to the bottom gate structure. In Fig. 7, a ruthenium oxide layer (e.g., insulating layer 31a) interposed in the gate insulating layer between the metal oxide semiconductor layer 27 and the gate electrode 29g, and a ruthenium oxide layer on the metal oxide semiconductor layer 27 The insulating layer 31b has an opening 33 corresponding to the opening region 11o to reduce the number of interfaces between the yttrium oxide layer and the tantalum nitride layer in the opening region 11o, thereby improving the light transmittance of the array substrate structure 100g.

In an embodiment, a cross-sectional view of the array substrate structure 100h is shown in FIG. In Fig. 8, the relative positions of the metal oxide transistor 11a, the opening region 11o, and the n-type polysilicon transistor 11n are similar to those of Fig. 1. This embodiment may further comprise a p-type polycrystalline germanium transistor 11p, or a n-type polycrystalline germanium transistor 11n may be replaced with a p-type polycrystalline germanium transistor 11p, as desired. The buffer layer 15 is on the substrate 13, and the buffer layer 19a is on the buffer layer 15. The polysilicon layer 17 (e.g., the source region 17s, the channel region 17c, and the drain region 17d) is located on the buffer layer 19a and corresponds to the polycrystalline germanium transistor 11n. The buffer layer 19b is formed on a portion of the polysilicon layer 17, and the gate 21 is formed on the buffer layer 19b. For the polysilicon transistor 11n, the gate 21 is located on the channel region 17c, and is separated by a gate insulating layer such as a buffer layer 19b. The interlayer dielectric layer 23 is located on the gate 21, the source region 17s, the drain region 17d, and the buffer layer 19a. The interlayer dielectric layer 25 is on the interlayer dielectric layer 23.

The contact 29c, the gate line 29L3, and the gate 29g are located on the interlayer dielectric layer 23. The contact 29c of the polysilicon transistor 11n is located on the source region 17s (or the drain region 17d), and is connected between the via holes 29h passing through the interlayer dielectric layers 25 and 23. The gate line 29L3 of the polysilicon transistor 11n is located on the gate 21, and is connected between the through holes 29h passing through the interlayer dielectric layers 25 and 23.

The insulating layer 35a is located on the contact 29c, the gate line 29L3, and the gate 29g. The insulating layer 31a is located on the insulating layer 35a. Metal oxide semiconductor layer 27 is located The edge layer 31a corresponds to the gate 29g of the metal oxide transistor 11a. For the metal oxide transistor 11a, the gate insulating layer between the channel region (metal oxide semiconductor layer 27) and the gate 29g is the insulating layers 31a and 35a. The insulating layer 31b is located on the metal oxide semiconductor layer 27 and the insulating layer 31a.

The source 43s and the drain 43d are respectively located on the insulating layer 31b on both sides of the metal oxide semiconductor layer 27, and are connected to both sides of the metal oxide semiconductor layer via via holes penetrating the insulating layer 31b. The material of the source 43s and the drain 43d may be metal, and the forming method may be: after the lithography etching insulating layer 31b is formed with an opening, depositing a metal in the opening and layering on the insulating layer 31b, and then patterning by a micro-etching process. The metal layer forms a source 43s and a drain 43d. The insulating layer 31c is located on the source electrode 43s, the drain electrode 43d, the metal oxide semiconductor layer 27, and the insulating layer 31b. The material of the insulating layer 31c may be ruthenium oxide, which may be formed by CVD. The insulating layers 31a, 31b, and 31c have openings 33 corresponding to the opening regions 11o, and the forming method thereof may be a photolithography etching process. In some embodiments, the opening 33 can further pass down through the insulating layer 35a, the interlayer dielectric layer 25, the interlayer dielectric layer 23, the buffer layer 19a, or even the buffer layer 15.

The insulating layer 35b is located inside the insulating layer 31c and the opening 33 and contacts the insulating layer 35a. The organic insulating layer 37 is on the insulating layer 35b, and the insulating layer 41 is on the organic insulating layer 37. The source line 45L1 and the drain line 45L2 are located on the insulating layer 41, and the material thereof may be a metal, an alloy, or other conductive material. The source line 45L1 of the polycrystalline germanium transistor 11n is located on the left contact 29c with the insulating layer 41, the organic insulating layer 37, the insulating layer 35b, the insulating layer 31c, the insulating layer 31b, the insulating layer 31a, and The through holes 45h of the insulating layer 35a are connected. The drain line 45L2 of the polycrystalline germanium transistor 11n is located on the contact 29c on the right side, passing between the insulating layer 41, the organic insulating layer 37, the insulating layer 35b, the insulating layer 31c, the insulating layer 31b, the insulating layer 31a, and Through hole of insulating layer 35a 45h connection. The source line 45L3 of the metal oxide transistor is located on the source electrode 43s, and is connected between the insulating layer 41, the organic insulating layer 37, the insulating layer 35b, and the through hole 45h of the insulating layer 31c. The drain line 45L4 of the metal oxide transistor is located on the drain electrode 43d, and is connected between the insulating layer 41, the organic insulating layer 37, the insulating layer 35b, and the via hole 45h of the insulating layer 31c.

In Fig. 8, the polycrystalline germanium transistor 11n belongs to the top gate structure, and the metal oxide transistor 11a belongs to the bottom gate structure. In Fig. 8, a ruthenium oxide layer (e.g., insulating layer 31a) interposed in the gate insulating layer between the metal oxide semiconductor layer 27 and the gate electrode 29g, and a ruthenium oxide layer on the metal oxide semiconductor layer 27 (e.g., the insulating layers 31b and 31c) have openings 33 corresponding to the opening regions 11o to reduce the number of interfaces between the yttrium oxide layer and the tantalum nitride layer in the opening region 11o, thereby improving the light transmittance of the array substrate structure 100g.

In one embodiment, a cross-sectional view of the array substrate structure 100i is shown in FIGS. 9A-9J. In Fig. 9A, the array substrate structure 100a is divided into a plurality of pixel regions 10a and a driving circuit 10b. Each of the pixel regions 10a has a metal oxide transistor 11a and an open region 11o, and the driving circuit 10b includes an n-type polycrystalline germanium transistor 11n and a p-type polycrystalline germanium transistor 11p. In other embodiments, the driver circuit 10b may have only an n-type polysilicon transistor 11n, or a p-type polysilicon transistor 11p, as desired. The light shielding layer 14 is formed on the substrate 13 and corresponds to the polysilicon layer 17 of the polycrystalline germanium transistors 11n and 11p and the metal oxide semiconductor layer 27 of the metal oxide transistor 11a, respectively. Next, a buffer layer 15 is formed on the light shielding layer 14, and a buffer layer 19a is formed on the buffer layer 15.

As shown in Fig. 9B, the polysilicon layer 17 of the polycrystalline germanium transistors 11n and 11p is formed on the buffer layer 19a, and corresponds to the polycrystalline germanium transistors 11n and 11p. The buffer layer 19A not covered by the polysilicon layer 17 can then be removed. In other embodiments, it may be retained The stamp layer 19A is on all of the buffer layers 15. In one embodiment, after forming the polysilicon layer 17, the opaque photoresist pattern (not shown) formed by the lithography process can be used to protect the intermediate channel region 17c, and ions are implanted on both sides of the channel region 17c to define the source region 17s. / bungee area 17d. The shading photoresist pattern can then be removed as appropriate, either by wet or dry stripping.

As shown in Fig. 9C, a buffer layer 19b is formed on the polysilicon layer 17 and the buffer layer 15, and a metal layer is formed on the buffer layer 19B. Next, the channel region 17c of the gate 21 corresponding to the polysilicon transistors 11n and 11p, and the light shielding layer 14 of the metal oxide transistor 11a are defined by a photolithography process, and the buffer layer 19b not covered by the gate 21 is removed. For the polysilicon transistors 11n and 11p, the gate 21 corresponds to the channel region 17c, and the gate insulating layer between the channel region 17c and the gate 21 is the buffer layer 19b.

As shown in Fig. 9D, an interlayer dielectric layer 23 is formed on the gate 21, the buffer layer 15, the source region 17s, and the source region 17d. An interlayer dielectric layer 25 is then formed over the interlayer dielectric layer 23. As shown in Fig. 9E, a metal oxide semiconductor layer 27 is formed on the interlayer dielectric layer 25 and corresponds to the gate 21 of the metal oxide transistor 11a. For the metal oxide transistor 11a, the gate insulating layer between the channel region (metal oxide semiconductor layer 27) and the gate 21 is the interlayer dielectric layers 23 and 25.

As shown in FIG. 9F, after the openings are formed through the interlayer dielectric layers 23 and 25 by the photolithography etching process, the metal is filled in the openings to form the via holes 29h and layered on the interlayer dielectric layer 25. Then, the metal layer is patterned by a process such as photolithography to define a source line 29L1, a drain line 29L2, a source 29s, and a drain 29d on the interlayer dielectric layer 25. The source line 29L1 is located on the source region 17s, and is connected between the interlayer dielectric layer 25, the interlayer dielectric layer 23, and the via hole 29h of the buffer layer 19b. The drain line 29L2 is located on the drain region 17d with the interlayer dielectric layer 25, the interlayer dielectric layer 23, and the buffer layer therebetween. The through holes 29h of 19b are connected. The source 29s and the drain 29d are respectively located on both sides of the metal oxide semiconductor layer 27.

As shown in Fig. 9G, an insulating layer 31 is subsequently formed on the interlayer dielectric layer 25, the metal oxide semiconductor layer 27, the source line 29L1, the drain line 29L2, the source 29s, and the drain 29d. Thereafter, a photoresist layer is formed on the insulating layer 31, and the photoresist layer is patterned by a backside exposure process 32 and a development process to form the photoresist pattern 30. The back surface exposure process does not require an additional mask, and the light shielding layer 14, the source region 17s, the drain region 17d, the source 29s, and the drain 29d are used as masks.

As shown in FIG. 9H, the photoresist pattern 30 is used as an etching mask, and the insulating layer 31 and the interlayer dielectric layer 25 which are not covered by the photoresist pattern 30 are removed by etching to form the opening 33. As shown in FIG. 9H, the opening 33 mainly corresponds to the opening area 11o, but may also correspond to the unmasked portion of the other photoresist pattern 30. As shown in Fig. 9H, the edges of the remaining insulating layer 31 and the interlayer dielectric layer 25 are aligned with the edges of the mask (e.g., source region 17s, drain region 17d, source 29s, and drain 9d). In some embodiments, the opening 33 can extend further down through the interlayer dielectric layer 23, or even the buffer layer 15.

As shown in FIG. 9I, the photoresist layer 30 is removed to form an insulating layer 35 in the insulating layer 31 and the opening 33, so that the insulating layer 35 contacts the interlayer dielectric layer 23. An organic insulating layer 37 is then formed on the insulating layer 35. As shown in Fig. 9H, a common electrode 39 is then formed on the organic insulating layer 37, which mainly corresponds to the pixel region 10a. Next, the insulating layer 41 is formed on the common electrode 39 and the organic insulating layer 37, and the holes are formed by lithography and etching the insulating layer 41, the organic insulating layer 37, the insulating layer 35, and the insulating layer 31. A transparent conductive material such as ITO is filled in the hole and layered on the insulating layer 41, and the ITO layer is patterned by a process such as photolithography to define the pixel electrode 43p. The array substrate structure 100i is thus completed.

The polysilicon transistors 11n and 11p of the driving circuit 10b of Fig. 9J belong to The top gate structure, and the metal oxide transistor 11a belongs to the bottom gate structure. In Fig. 9J, a ruthenium oxide layer (e.g., insulating layer 31) on the metal oxide semiconductor layer 27, and ruthenium oxide interposed in the gate insulating layer interposed between the metal oxide semiconductor layer 27 and the gate electrode 21 The layer (such as the interlayer dielectric layer 25) has an opening 33 corresponding to the opening region 11o to reduce the number of interfaces between the yttrium oxide layer and the tantalum nitride layer in the opening region 11o, thereby improving the light transmittance of the array substrate structure 100i.

In one embodiment, a cross-sectional view of the array substrate structure 100j is shown in FIGS. 10A through 10C. 10A is a structure according to FIG. 9G, in which the photoresist pattern 30 is used as an etching mask, and the insulating layer 31, the interlayer dielectric layer 25, the interlayer dielectric layer 23, and the buffer layer which are not covered by the photoresist pattern 30 are removed by etching. 15 forms an opening 33 to expose a portion of the substrate 13. As shown in Fig. 10A, the opening 33 mainly corresponds to the opening area 11o. As shown in FIG. 10B, an insulating layer 35 is then formed in the insulating layer 31 and the opening 33, and the insulating layer 35 contacts the substrate 13. An organic insulating layer 37 is then formed on the insulating layer 35. As shown in Fig. 10C, a common electrode 39 is formed on the organic insulating layer 37, which mainly corresponds to the pixel region 10a. Next, the insulating layer 41 is formed on the common electrode 39 and the organic insulating layer 37, and the holes are formed by lithography and etching the insulating layer 41, the organic insulating layer 37, the insulating layer 35, and the insulating layer 31. A transparent conductive material such as ITO is filled in the hole and layered on the insulating layer 41, and the ITO layer is patterned by a process such as photolithography to define the pixel electrode 43p. The array substrate structure 100j is thus completed.

The polysilicon transistors 11n and 11p of the driving circuit 10b of Fig. 10c belong to the top gate structure, and the metal oxide transistor 11a belongs to the bottom gate structure. In Fig. 10c, a hafnium oxide layer (e.g., insulating layer 31) on the metal oxide semiconductor layer 27, and a hafnium oxide layer interposed in the gate insulating layer interposed between the metal oxide semiconductor layer 27 and the gate electrode 21 The layer (such as the interlayer dielectric layer 25) has an opening 33 corresponding to the opening area 11o to reduce opening The number of interfaces between the ruthenium oxide layer and the tantalum nitride layer in the opening region 11o, thereby improving the light transmittance of the array substrate structure 100j.

In one embodiment, a cross-sectional view of the array substrate structure 100k is shown in FIGS. 11A-11B. 11A is a structure in which the organic insulating layer 37 is formed in the insulating layer 31 and the opening 33, and the organic insulating layer 37 is in contact with the substrate 13. As shown in Fig. 10B, a common electrode 39 is formed on the organic insulating layer 37, which mainly corresponds to the pixel region 10a. Next, the insulating layer 41 is formed on the common electrode 39 and the organic insulating layer 37, and the holes are formed by lithography and etching the insulating layer 41, the organic insulating layer 37, and the insulating layer 31. A transparent conductive material such as ITO is filled in the hole and layered on the insulating layer 41, and the ITO layer is patterned by a process such as photolithography to define the pixel electrode 43p. The array substrate structure 100k is thus completed.

The polysilicon transistors 11n and 11p of the driving circuit 10b of Fig. 11B belong to the top gate structure, and the metal oxide transistor 11a belongs to the bottom gate structure. In Fig. 10c, a hafnium oxide layer (e.g., insulating layer 31) on the metal oxide semiconductor layer 27, and a hafnium oxide layer interposed in the gate insulating layer interposed between the metal oxide semiconductor layer 27 and the gate electrode 21 The layer (such as the interlayer dielectric layer 25) has an opening 33 corresponding to the opening region 11o, so that the yttrium oxide layer is not present in the opening region 11o to reduce the occurrence of total reflection, thereby improving the light transmittance of the array substrate structure 100k.

In an embodiment, a cross-sectional view of the array substrate structure 100l is shown in FIG. In Fig. 12, the relative positions of the pixel region 10a, the driving circuit 10b, the metal oxide transistor 11a, the opening region 11o, and the polysilicon transistors 11n and 11p are similar to those of Fig. 1. The light shielding layer 14 is located on the substrate 13 and corresponds to the polysilicon layer 17 of the polycrystalline germanium transistors 11n and 11p and the metal oxide semiconductor layer 27 of the metal oxide transistor 11a, respectively.

The metal oxide semiconductor layer is on the light shielding layer 14 of the metal oxide transistor 11a. The buffer layer 19a is located on the light shielding layer 14, the substrate 13, and the metal oxide semiconductor layer 27 of the polycrystalline germanium transistors 11n and 11p. The buffer layer 15 is located on the buffer layer 19a. The polysilicon layer 17 (e.g., the source region 17s, the channel region 17c, and the drain region 17d) is located on the buffer layer 15 and corresponds to the polysilicon transistors 11n and 11p. The buffer layer 19b is located on the channel region 17c and the buffer layer 15 of the metal oxide transistor 11a. The gate 21 is located on the buffer layer 19b. For the polysilicon transistors 11n and 11p, the gate 21 corresponds to the channel region 17c, and the gate insulating layer between the channel region 17c and the gate 21 is the buffer layer 19b. For the metal oxide transistor 11a, the gate 21 corresponds to the channel region (metal oxide semiconductor layer 27), and the gate insulating layer therebetween is the buffer layers 19b, 15, and 19.

The buffer layers 15 and 19a have openings corresponding to the opening regions 11o, which may be formed by a photolithography process. It should be noted that the exposure step in the above lithography process can be upwardly exposed from below, and the exposure step uses the light shielding layer 14, the source line 29L1, and the drain line 29L2 as a mask, thereby omitting a mask and saving cost. . After the lithography and etching process in this exposure direction, the edges of the buffer layers 19b and 19a (yttria layer) will be aligned with the edges of the mask.

The interlayer dielectric layer 23 is located on the gate 21, the source region 17s, the drain region 17d, and the buffer layer 15, and the interlayer dielectric layer 23 directly contacts the substrate 13 via the opening. The source line 29L1, the drain line 29L2, and the contact 29c are located on the interlayer dielectric layer 23. The source lines 29L1 of the polysilicon transistors 11n and 11p are located on the source region 17s, and are connected between the through holes 29h passing through the interlayer dielectric layer 23. The gate lines 29L2 of the polycrystalline germanium transistors 11n and 11p are located on the drain region 17d, and are connected to each other with a via 29h passing through the interlayer dielectric layer 23. The source line 29L1 of the metal oxide transistor 11a is located on one side of the metal oxide semiconductor layer 27 with the interlayer dielectric layer 23, the buffer layer 15, and the like interposed therebetween. The through holes 29h of the punch layer 19a are connected. The contact 29c of the metal oxide transistor 11a is located on the other side of the metal oxide semiconductor layer 27, and is connected between the interlayer dielectric layer 23, the buffer layer 15, and the via hole 29h of the buffer layer 19a.

The insulating layer 35 is located on the interlayer dielectric layer 23 and the source line 29L1, the drain line 29L2, and the contact 29c. The organic insulating layer 37 is located on the insulating layer 35. The common electrode 39 is located on the organic insulating layer 37, and mainly corresponds to the pixel region 10a. The insulating layer 41 is located on the common electrode 39 and the organic insulating layer 37. The pixel electrode 43p is located on the insulating layer 41. The partial pixel electrode 43p is located on the contact 29c, and is connected between the insulating layer 41, the organic insulating layer 37, and the through hole 43h of the insulating layer 35. The polycrystalline germanium transistors 11n and 11p of the driving circuit 10b in Fig. 12 belong to the top gate structure, and the metal oxide transistor 11a belongs to the top gate structure. In Fig. 12, a ruthenium oxide layer (e.g., buffer layer 19a) interposed between the MOS insulating layer 27 and the gate insulating layer 21 has an opening corresponding opening area 11o to reduce the opening area 11o. The number of interfaces between the ruthenium oxide layer and the tantalum nitride layer improves the light transmittance of the array substrate structure 1001.

In one embodiment, a cross-sectional view of the array substrate structure 100m is shown in FIG. In Fig. 13, the relative positions of the pixel region 10a, the driving circuit 10b, the metal oxide transistor 11a, the opening region 11o, and the polysilicon transistors 11n and 11p are similar to those of Fig. 1. The light shielding layer 14 is located on the substrate 13 and corresponds to the polysilicon layer 17 of the polycrystalline germanium transistors 11n and 11p and the metal oxide semiconductor layer 27 of the metal oxide transistor 11a, respectively.

The buffer layer 15a is located on the light shielding layer 14, the substrate 13, and the metal oxide semiconductor layer 27 of the polycrystalline germanium transistors 11n and 11p, and may be made of tantalum nitride, and may be formed by CVD. The buffer layer 19a is located on the buffer layer 15a. The polysilicon layer 17 (such as the source region 17s, the channel region 17c, and the drain region 17d) is located on the buffer layer 19a, and corresponds to Polycrystalline germanium transistors 11n and 11p. The metal oxide semiconductor layer 27 is on the buffer layer 19a and corresponds to the metal oxide transistor 11a. The buffer layer 19b is located on the channel region 17c and the metal oxide semiconductor layer 27. The buffer layer 15b is located on the buffer layer 19b and may be made of tantalum nitride, and may be formed by CVD. The gate 21 is located on the buffer layer 15b. For the polysilicon transistors 11n and 11p, the gate 21 corresponds to the channel region 17c, and the gate insulating layer between the channel region 17c and the gate 21 is the buffer layers 15b and 19b. For the metal oxide transistor 11a, the gate 21 corresponds to the channel region (metal oxide semiconductor layer 27), and the gate insulating layer therebetween is the buffer layers 15b and 19b.

The buffer layers 15b, 19b, 19a, and 19b have openings corresponding to the opening regions 11o, which may be formed by a photolithography process. The interlayer dielectric layer 23 is located on the substrate 13, the gate 21, the source region 17s, the drain region 17d, and both sides of the metal oxide semiconductor layer 27. The source line 29L1, the drain line 29L2, and the contact 29c are located on the interlayer dielectric layer 23. The source lines 29L1 of the polysilicon transistors 11n and 11p are located on the source region 17s, and are connected between the through holes 29h passing through the interlayer dielectric layer 23. The gate lines 29L2 of the polycrystalline germanium transistors 11n and 11p are located on the drain region 17d, and are connected to each other with a via 29h passing through the interlayer dielectric layer 23. The source line 29L1 of the metal oxide transistor 11a is located on one side of the metal oxide semiconductor layer 27, and is connected between the holes 29h passing through the interlayer dielectric layer 23. The contact 29c of the metal oxide transistor 11a is located on the other side of the metal oxide semiconductor layer 27, and is connected between the through holes 29h passing through the interlayer dielectric layer 23.

The insulating layer 35 is located on the interlayer dielectric layer 23 and the source line 29L1, the drain line 29L2, and the contact 29c. The organic insulating layer 37 is located on the insulating layer 35. The common electrode 39 is located on the organic insulating layer 37, and mainly corresponds to the pixel region 10a. The insulating layer 41 is located on the common electrode 39 and the organic insulating layer 37. The pixel electrode 43p is located on the insulating layer 41. Part of the pixel electrode 43p is located on the contact 29c, passing between the insulating layer 41 and the organic The insulating layer 37 is connected to the through hole 43h of the insulating layer 35. The polycrystalline germanium transistors 11n and 11p of the driving circuit 10b in Fig. 13 belong to the top gate structure, and the metal oxide transistor 11a belongs to the top gate structure. In Fig. 13, a ruthenium oxide layer (e.g., buffer layer 19b) interposed between the MOS insulating layer 27 and the gate insulating layer 21 has an opening corresponding opening area 11o to reduce the opening area 11o. The number of interfaces between the ruthenium oxide layer and the tantalum nitride layer improves the light transmittance of the array substrate structure by 100 m.

The array substrate structure 100n of FIG. 14 is similar to that of FIG. 12 except that the insulating layer 35 and the interlayer dielectric layer 23 also have openings (the openings of the alignment buffer layers 15 and 19a), so that the organic insulating layer 37 contacts the substrate 13 via the opening. .

The array substrate structure 100o of Fig. 15 is similar to that of Fig. 12 except that the interlayer insulating layer 23 also has an opening (the opening of the alignment buffer layers 15 and 19a), so that the insulating layer 35 contacts the substrate 13 via the opening.

In an embodiment, a cross-sectional view of the array substrate structure 100p is shown in FIG. In Fig. 16, the relative positions of the pixel region 10a, the driving circuit 10b, the metal oxide transistor 11a, the opening region 11o, and the polysilicon transistors 11n and 11p are similar to those of Fig. 1. The light shielding layer 14 is located on the substrate 13 and corresponds to the polysilicon layer 17 of the polycrystalline germanium transistors 11n and 11p and the metal oxide semiconductor layer 27 of the metal oxide transistor 11a, respectively. In this embodiment, the light-shielding layer 14 of the metal oxide transistor serves as a gate at the same time. Therefore, the material of the light-shielding layer 14 must be a conductive material such as metal, and the formation method can be performed by depositing a layer and then patterning by a process such as photolithography.

The buffer layer 15 is located on the substrate 13 and the light shielding layer 14, the buffer layer 19a is located on the buffer layer 15, and the polysilicon layer 17 (such as the source region 17s, the channel region 17c, and the drain region 17d) is located on the buffer layer 19a and corresponds to the polysilicon layer. The transistors 11n and 11p. The buffer layer 19b is located on the polysilicon layer 17 and the buffer layer 19a, and the gate 21 and the gate line 21' are located at a slow level. Punching layer 19b. For the polysilicon transistors 11n and 11p, the gate 21 is located on the channel region 17c with a gate insulating layer such as a buffer layer 19b. In the metal oxide transistor 11a, the gate line 21' and the light shielding layer 14 are connected to each other through the buffer holes 19b, 19a and the through holes 21h of 15. The buffer layers 19a and 19b have openings corresponding to the opening regions 11o. The interlayer dielectric layer 23 is located on the gate 21, the gate line 21', and the buffer layer 19b, and directly contacts the buffer layer 15 via the openings of the buffer layers 19a and 19b.

The interlayer dielectric layer 25 is on the interlayer dielectric layer 23. The metal oxide semiconductor layer 27 is on the interlayer dielectric layer 25 and corresponds to the gate of the metal oxide transistor 11a (light shielding layer 14). For the metal oxide transistor 11a, the gate insulating layer between the channel region (metal oxide semiconductor layer 27) and the gate (light shielding layer 14) is an interlayer dielectric layer 25, an interlayer dielectric layer 23, and a buffer layer. 19b, buffer layer 19a, and buffer layer 15. The source line 29L1, the drain line 29L2, the source 29s, and the drain 29d are located on the interlayer dielectric layer 25. The source line 29L1 is located on the source region 17s, and is connected between the interlayer dielectric layer 25, the interlayer dielectric layer 23, and the via hole 29h of the buffer layer 19b. The drain line 29L2 is located on the drain region 17d, and is connected between the interlayer dielectric layer 25, the interlayer dielectric layer 23, and the via hole 29h of the buffer layer 19b. The source 29s and the drain 29d are respectively located on both sides of the metal oxide semiconductor layer 27.

The insulating layer 31 is located on the source line 29L1, the drain line 29L2, the source 29s, the drain 29d, the metal oxide semiconductor layer 27, and the interlayer dielectric layer 25. The insulating layer 35 is on the insulating layer 31. The insulating layer 35, the insulating layer 31, and the interlayer dielectric layer 25 have openings corresponding to the opening regions 11o, and the forming method thereof may be a photolithography etching process. It should be noted that the exposure step in the above lithography process can be upwardly exposed from below, and the exposure step uses the light shielding layer 14, the source line 29L1, the drain line 29L2, and the source 29s as a mask, which can be omitted. Photomasks save costs. Lithography and eclipse in this exposure direction After the engraving process, the edges of the insulating layer 31 and the interlayer dielectric layer 25 (yttria layer) will be aligned with the edges of the mask.

The organic insulating layer 37 is located on the insulating layer 35, and contacts the interlayer dielectric layer 23 via the insulating layer 35, the insulating layer 31, and the opening of the interlayer dielectric layer 25. The common electrode 39 is located on the organic insulating layer 37, and mainly corresponds to the pixel region 10a. The insulating layer 41 is located on the common electrode 39 and the organic insulating layer 37. The pixel electrode 43p is located on the insulating layer 41. The partial pixel electrode 43p is located on the drain electrode 29d, and is connected between the insulating layer 41, the organic insulating layer 37, the insulating layer 35, and the through hole 43h of the insulating layer 31. The polycrystalline germanium transistors 11n and 11p of the driving circuit 10b in Fig. 16 belong to the top gate structure, and the metal oxide transistor 11a belongs to the bottom gate structure. In Fig. 16, a ruthenium oxide layer (such as an interlayer dielectric layer 25, a buffer layer 19a, and a buffer) interposed between the MOS insulating layer 27 and the gate insulating layer (the light-shielding layer 14) The layer 9b) has an opening corresponding to the opening region 11o with the yttrium oxide layer (such as the insulating layer 31) on the metal oxide semiconductor layer 27 to reduce the number of interfaces between the yttrium oxide layer and the tantalum nitride layer in the opening region 11o, thereby improving the array. Light transmittance of the substrate structure 100p.

In an embodiment, a cross-sectional view of the array substrate structure 100q is shown in FIG. In Fig. 17, the relative positions of the pixel region 10a, the driving circuit 10b, the metal oxide transistor 11a, the opening region 11o, and the polysilicon transistors 11n and 11p are similar to those of Fig. 1. The light shielding layer 14 is located on the substrate 13 and corresponds to the polysilicon layer 17 of the polycrystalline germanium transistors 11n and 11p and the metal oxide semiconductor layer 27 of the metal oxide transistor 11a, respectively. In this embodiment, the light shielding layer 14 of the metal oxide transistor serves as a gate at the same time, and therefore the material of the light shielding layer 14 must be a conductive material such as metal.

The buffer layer 15 is located on the substrate 13 and the light shielding layer 14, and the buffer layer 19a is located on the buffer layer 15. Polycrystalline germanium layer 17 (such as source region 17s, channel region 17c, and drain The region 17d) is located on the buffer layer 19a and corresponds to the polycrystalline germanium transistors 11n and 11p. The metal oxide semiconductor layer 27 is on the buffer layer 19a and corresponds to the gate of the metal oxide transistor 11a (light shielding layer 14). The buffer layer 19b is located on the polysilicon layer 17, the metal oxide semiconductor layer 27, and the buffer layer 19a. The gate 21 and the gate line 21' are located on the buffer layer 19b, and the source 21s and the drain 21d pass through the buffer layer 19b to contact both sides of the metal oxide semiconductor layer 27. For the polysilicon transistors 11n and 11p, the gate 21 is located on the channel region 17c with a gate insulating layer such as a buffer layer 19b. For the metal oxide transistor 11a, the gate insulating layer between the channel region (metal oxide semiconductor layer 27) and the gate (light shielding layer 14) is the buffer layer 19a and the buffer layer 15. In the metal oxide transistor 11a, the gate line 21' and the light shielding layer 14 are connected to each other through the buffer holes 19b, 19a and the through holes 21h of 15. The buffer layers 19a and 19b have openings corresponding to the opening regions 11o. The interlayer dielectric layer 23 is located on the gate 21, the gate line 21', and the buffer layer 19b, and directly contacts the buffer layer 15 via the openings of the buffer layers 19a and 19b.

The interlayer dielectric layer 25 is on the interlayer dielectric layer 23. The source line 29L1, the drain line 29L2, and the contact 29c are located on the interlayer dielectric layer 25. The source lines 29L1 of the polysilicon transistors 11n and 11p are located on the source region 17s, and are connected between the interlayer dielectric layer 25, the interlayer dielectric layer 23, and the via hole 29h of the buffer layer 19b. The gate lines 29L2 of the polycrystalline germanium transistors 11n and 11p are located on the drain region 17d, and are connected between the interlayer dielectric layer 25, the interlayer dielectric layer 23, and the via hole 29h of the buffer layer 19b. The source line 29L1 of the metal oxide transistor 11a is located on the source 21s, and is connected between the interlayer via holes 29h passing through the interlayer dielectric layer 25 and the interlayer dielectric layer 23. The contact 29c of the metal oxide transistor 11a is located on the drain 21d, and is connected between the interlayer via hole 29h passing through the interlayer dielectric layer 25 and the interlayer dielectric layer 23.

The insulating layer 35 is on the interlayer dielectric layer 25. Insulating layer 35 and interlayer The dielectric layer 25 has an opening corresponding to the opening region 11o, and the forming method thereof may be a photolithography etching process. It should be noted that the exposure step in the above lithography process can be upwardly exposed from below, and the exposure step uses the light shielding layer 14, the source line 29L1, and the drain line 29L2 as a mask, thereby omitting a mask and saving cost. . After the lithography and etching process in this exposure direction, the edges of the interlayer dielectric layer 25 (yttria layer) will be aligned with the edges of the mask.

The organic insulating layer 37 is located on the insulating layer 35 and contacts the interlayer dielectric layer 23 via the insulating layer 35 and the opening of the interlayer dielectric layer 25. The common electrode 39 is located on the organic insulating layer 37, and mainly corresponds to the pixel region 10a. The insulating layer 41 is located on the common electrode 39 and the organic insulating layer 37. The pixel electrode 43p is located on the insulating layer 41. The partial pixel electrode 43p is located on the drain electrode 29d, and is connected between the insulating layer 41, the organic insulating layer 37, and the through hole 43h of the insulating layer 35. The polycrystalline germanium transistors 11n and 11p of the driving circuit 10b in Fig. 17 belong to the top gate structure, and the metal oxide transistor 11a belongs to the bottom gate structure. In Fig. 17, a ruthenium oxide layer (e.g., buffer layer 19a) interposed in the gate insulating layer between the metal oxide semiconductor layer 27 and the gate (light shielding layer 14), and the metal oxide semiconductor layer 27 The yttrium oxide layer (such as the interlayer dielectric layer 25 and the buffer layer 19b) has an opening corresponding opening region 11o to reduce the number of interfaces between the yttrium oxide layer and the tantalum nitride layer in the opening region 11o, thereby improving light transmission of the array substrate structure 100q. Permeability.

The array substrate structure 100r of FIG. 18 is similar to that of FIG. 16, except that the buffer layer 15, the buffer layer 19a, the buffer layer 19b, the interlayer dielectric layer 23, the interlayer dielectric layer 25, the insulating layer 31, and the insulating layer 35 have The opening corresponds to the opening region 11o, and thus the organic insulating layer 37 formed on the insulating layer 35 contacts the substrate 13 via the opening. In Fig. 18, the opening region 11o does not have an interface between the ruthenium oxide layer and the tantalum nitride layer, so that the light transmittance of the array substrate structure 100r can be improved.

In the first embodiment, the polycrystalline germanium transistor 11n and the metal oxide transistor 11a are both designed with a bottom gate. The gate 21 is located on the substrate 13, and each corresponds to the germanium transistor 11n and the metal oxide transistor 11a. The buffer layer 15 is located on the gate 21 and the substrate, the buffer layer 19a is on the buffer layer 15, and the polysilicon layer 17 (such as the source region 17s, the channel region 17c, and the drain region 17d) is located on the buffer layer 19a. The buffer layer 19b is located on the polysilicon layer 17 and the buffer layer 19a. The source line 29L1, the drain line 29L2, the source 29s, and the drain 29d are located on the buffer layer 19b. The source line 29L1 is located on the source region 17s, and is connected between the two via holes 29h passing through the buffer layer 19b. The drain line 29L2 is located on the drain region 17d, and is connected between the two via holes 29h passing through the buffer layer 19b. The source 29s and the source 29d are located on both sides of the metal oxide semiconductor layer. The buffer layers 19a and 19b have openings corresponding to the opening regions 11o. As for the remaining elements such as the pixel electrode and the common electrode, reference may be made to the foregoing embodiment. In Fig. 19, the ruthenium oxide layer (e.g., buffer layers 19a and 19b) in the gate insulating layer between the MOS layer 27 and the gate electrode 21 has openings corresponding to the opening regions 11o, which can reduce the yttrium oxide layer and nitrogen. The number of interfaces of the ruthenium layer improves the light transmittance of the array substrate structure.

In one embodiment, the polysilicon layer 11 of the polycrystalline germanium transistor 11n (or 11p) may be covered with an amorphous germanium layer 51 on both sides, and the doped germanium layer 53 is on the amorphous germanium layer 51, as shown in FIG. Show.

In one embodiment, the display device 200 includes an array substrate structure 210a, a counter substrate structure 210c, and a display medium 210b interposed between the two. The array substrate structure may be the array substrate structure in any of the foregoing embodiments. The display medium 210b may be a liquid crystal layer or an organic light emitting layer. The opposite substrate structure 210c may be a color filter substrate or a transparent substrate.

Although the present invention has been disclosed above in several embodiments, it is not In order to limit the invention, any person skilled in the art can make any modifications and refinements without departing from the spirit and scope of the invention, and therefore the scope of the invention is defined by the appended claims. The definition is subject to change.

14‧‧‧Lighting layer

10a‧‧‧Photo District

10b‧‧‧Drive circuit

11a‧‧‧Metal oxide crystal

11n, 11p‧‧‧ polycrystalline germanium transistors

11o‧‧‧Open area

13‧‧‧Substrate

15, 19a, 19b, 19c‧‧‧ buffer layer

17‧‧‧Polysilicon layer

17c‧‧‧Channel area

17d‧‧‧Bungee Area

17s‧‧‧ source area

21‧‧‧ gate

23, 25‧‧‧ Interlayer dielectric layer

27‧‧‧Metal oxide semiconductor layer

29d‧‧‧Bungee

29h, 43h‧‧‧through hole

29L1‧‧‧ source line

29L2‧‧‧汲polar line

29s‧‧‧ source

31, 35, 41‧‧‧ insulation

33‧‧‧ openings

37‧‧‧Organic insulation

39‧‧‧Common electrode

43p‧‧‧ pixel electrodes

100a‧‧‧Array substrate structure

Claims (17)

A display device comprising: a substrate structure comprising: a substrate having a pixel, and the pixel has an open region; a metal oxide transistor disposed on the substrate and including: a metal oxide semiconductor layer Having a first channel region; a first gate corresponding to the first channel region; and a tantalum oxide insulating layer on the metal oxide semiconductor layer, wherein the yttrium oxide insulating layer has an opening and the opening And corresponding to the open area; and a polycrystalline germanium transistor disposed on the substrate; a pair of substrate structures; and a display medium between the substrate structure and the opposite substrate structure. The display device of claim 1, wherein the polycrystalline germanium transistor is located in a driving circuit of the substrate structure, the metal oxide transistor is located in the pixel, and the polycrystalline germanium transistor drives the metal oxide Transistor. The display device of claim 1, wherein the polycrystalline germanium transistor comprises: a polysilicon semiconductor layer having a second channel region; and a second gate corresponding to the second channel region; wherein the polysilicon semiconductor a layer is between the substrate and the second gate, And the metal oxide semiconductor layer is located on the substrate and the first gate. The display device of claim 3, wherein the substrate structure further comprises a light shielding layer disposed between the polysilicon semiconductor layer and the substrate. The display device of claim 4, wherein the first gate is located between the metal oxide semiconductor layer and the substrate, and the first gate is in the same layer as the light shielding layer. The display device of claim 3, wherein the polycrystalline germanium transistor comprises an amorphous germanium layer on the poly germanium semiconductor layer. The display device of claim 1, wherein the substrate structure further comprises a tantalum nitride insulating layer on the metal oxide transistor and the polysilicon transistor, wherein the tantalum nitride is insulated in the open region The layer is in direct contact with the substrate. The display device of claim 1, wherein the substrate structure further comprises an organic insulating layer on the metal oxide transistor and the polysilicon transistor, and the organic insulating layer directly contacts the opening region Substrate. The display device of claim 1, wherein an edge of the yttrium oxide insulating layer is aligned with an edge of the first gate or an edge of a first source and a first drain, wherein the The first source and the first drain are located on both sides of the first channel region. The display device of claim 1, wherein a second gate of the polycrystalline germanium transistor is located in one of the polycrystalline germanium transistors The bulk layer is between the substrate and the first gate of the metal oxide transistor is between the metal oxide semiconductor layer and the substrate. The display device of claim 1, wherein the metal oxide semiconductor transistor comprises a gate insulating layer between the metal oxide semiconductor layer and the first gate, the gate insulating layer comprising a first An osmium oxide layer, and the first ruthenium oxide layer has an opening corresponding to the open region. A display device comprising: a substrate structure comprising: a substrate having a pixel, and the pixel has an open region; a metal oxide transistor disposed on the substrate and including: a metal oxide semiconductor layer Having a first channel region; a first gate corresponding to the first channel region; and a gate insulating layer between the first gate and the metal oxide semiconductor layer, wherein the gate insulating layer a first tantalum nitride layer and a first tantalum oxide layer are disposed between the first tantalum nitride layer and the metal oxide semiconductor layer; a polycrystalline germanium transistor is disposed on the substrate And a tantalum nitride insulating layer on the metal oxide transistor and the polycrystalline germanium transistor, wherein the tantalum nitride insulating layer directly contacts the first tantalum nitride layer in the open region; a pair of substrate structures And a display medium between the substrate structure and the opposite substrate structure. The display device of claim 12, wherein the polycrystalline germanium transistor comprises: a polysilicon semiconductor layer having a second channel region; and a second gate corresponding to the second channel region; wherein the polysilicon semiconductor Located between the substrate and the second gate, the metal oxide semiconductor layer is located on the substrate and the first gate. The display device of claim 13, wherein the polycrystalline germanium transistor further comprises an amorphous germanium layer on the poly germanium semiconductor layer. The display device of claim 12, wherein the substrate structure further comprises a light shielding layer disposed between the polysilicon semiconductor layer and the substrate, and the first gate is located between the IGZO layer and the substrate and The light shielding layer is in the same layer. The display device of claim 13, wherein an edge of the yttrium oxide insulating layer is aligned with an edge of the first gate or an edge of a first source and a first drain, wherein the The first channel region is located between the first source and the first drain. The display device of claim 12, wherein a second gate of the polycrystalline germanium transistor is located between the polycrystalline germanium semiconductor layer of the polycrystalline germanium transistor and the substrate, and the metal oxide transistor is A gate is located between the metal oxide semiconductor layer and the substrate.