CN106409661A - Deep level fast ionization conduction device and manufacturing method thereof - Google Patents

Abstract

The invention discloses a deep-level fast ionization conduction device and a manufacturing method thereof, belonging to the technical field of semiconductor device manufacturing technology. The present invention includes an N-type semiconductor substrate, the front of the N-type semiconductor substrate is a P-type diffusion region, and a cathode P ⁺ region, a cathode N ⁺ region and a P ⁺ guard ring are distributed on the P-type diffusion region, and in the said P-type diffusion region The cathode P ⁺ area, the cathode N ⁺ area and the P ⁺ guard ring cover the cathode metal electrode; the anode P ⁺ area, the anode N ⁺ area and the N ⁺ guard ring are distributed on the back of the N-type semiconductor substrate, and the anode P ⁺ area , the anode N ⁺ region and the N ⁺ guard ring cover the anode metal electrode. The device in the present invention has a very high working voltage and working current, and the deep-level trap will quickly release ionized electrons, with high current rising rate and fast conduction speed, and can switch thousands of amperes in sub-nanosecond time The current has high reliability and can be widely used in high-power pulse source systems.

Description

Deep level fast ionization conduction device and manufacturing method thereof

technical field

The invention belongs to the technical field of semiconductor device manufacturing technology, and in particular relates to a deep-level fast ionization conduction device and a manufacturing method thereof.

Background technique

Pulse power technology originated in the 1940s and 1950s and was initially used in the field of national defense research. In the 1960s, JCMartin and his research team applied the Blumlein transmission line technology to flash X-ray radiography, making the pulse power technology enter the practical stage. Subsequently, the pulse power technology developed rapidly, the peak power of a single pulse exceeded 10 ¹⁴ W, and the pulse width ranged from μm to ns or even ps. At present, with the technological progress and the continuous expansion of application scope in related fields such as material science, switching technology, and energy storage technology, pulse power technology has gained a broader development space.

In pulsed power systems, conventional switches include spark gaps, thyratrons, vacuum tubes, and explosive switches. These traditional switches are widely used in pulsed power systems, and the technology is relatively mature. However, these traditional switches have some insurmountable shortcomings, such as short working life, bulky switches, poor synchronization, and susceptibility to interference. In addition, switches such as spark gaps and thyratrons consume a lot of power and require a huge cooling system; while switches such as vacuum tubes have extremely low repetition rates. With the rapid development of the semiconductor industry, semiconductor solid-state switches are increasingly used in the field of power electronics. Semiconductor solid-state switches have the advantages of small size, long life, and stable operation. From the earliest thyristors to later GTO, GCT, IGBT, and MOSFET semiconductor switches, they have shown a tendency to completely replace traditional switches. However, these semiconductor switches still have certain defects. Although GTO and GCT have high operating voltage, their repetition frequency is very low; MOSFETs have high operating frequency, but their operating voltage is low; Complicated circuits generate trigger signals. When multi-level series and parallel connections are used, the trigger system will become very complicated, which will bring great difficulties to use and maintenance.

Contents of the invention

The technical problem to be solved by the present invention is to provide a deep-level rapid ionization conduction device, which only needs to be triggered by pulses, does not require a complicated trigger system, and has a high operating voltage and current, and a deep-level trap The ionized electrons will be released quickly, the current rise rate is high, the conduction speed is fast, and the current of thousands of amperes can be switched in sub-nanosecond time, with high reliability, and can be widely used in high-power pulse source systems middle.

In order to solve the above-mentioned technical problems, the technical solution adopted by the present invention is: a deep-level rapid ionization conduction device, comprising an N-type semiconductor substrate, the front side of the N-type semiconductor substrate is a P-type diffusion region, so A cathode P ⁺ region, a cathode N ⁺ region and a P ⁺ guard ring are distributed on the P-type diffusion region, and a cathode metal electrode is covered on the cathode P ⁺ region, cathode N ⁺ region and P ⁺ guard ring; the N-type semiconductor An anode P ⁺ region, an anode N ⁺ region and an N ⁺ guard ring are distributed on the back of the substrate, and the anode metal electrode is covered on the anode P ⁺ region, the anode N ⁺ region and the N ⁺ guard ring.

In a further technical solution, the N-type semiconductor substrate is an N-type Si material, the resistivity is 90Ω·cm, and the thickness is 400-450 μm; the depth of the P-type diffusion region on the front side of the N-type semiconductor substrate is 50-100 μm .

In a further technical solution, the depth of the cathode P ⁺ region distributed on the P-type diffusion region is 15±5 μm, and the surface sheet resistance is 5-10Ω/□; the depth of the cathode N ⁺ region is 20±5 μm, and the surface sheet resistance is 0.1- 0.5Ω/□; the depth of P ⁺ guard ring is 15±5μm, and the surface sheet resistance is 5-10Ω/□.

In a further technical solution, the depth of the anode P ⁺ region distributed on the back of the N-type semiconductor substrate is 15±5 μm, and the surface sheet resistance is 5-10Ω/□; the depth of the anode N ⁺ region is 20±5 μm, and the surface sheet resistance is 0.1 -0.5Ω/□; the depth of the N ⁺ guard ring is 15±5μm, and the surface sheet resistance is 5-10Ω/□.

In a further technical solution, both the anode metal electrode and the cathode metal electrode of the device are molybdenum electrodes.

The present invention also provides a method for manufacturing a deep-level rapid ionization conduction device. The manufacturing method only needs to carry out photolithography on the front and back sides once, which reduces the complexity of the process, simplifies the process flow, is simple in process, and does not require complex Process equipment, easy to implement; and compatible with existing silicon process technology, no additional cost will be added.

In order to solve the above-mentioned technical problems, the technical solution adopted by the present invention is: a method for manufacturing a deep-level fast ionization conduction device, comprising the following steps:

(1) cleaning and drying the N-type semiconductor substrate;

(2) P-type high-temperature diffusion doping on the front side;

(3) Use wet etching to remove the surface oxide layer;

(4) fixing the doped surface of the N-type semiconductor substrate, and polishing and thinning the undoped side;

(5) forming diffusion mask patterns on both sides of the N-type semiconductor substrate;

(6) Forming N+ and P+ diffusion regions on both sides of the N-type semiconductor substrate at the same time;

(7) growing metallic nickel layers on both sides of the N-type semiconductor substrate, and annealing to form ohmic contact electrodes;

(8) The chip is sintered on the metal molybdenum sheet to form a cathode metal electrode and an anode metal electrode;

(9) The edge of the chip forms an angled terminal, and silicon rubber is used to protect the edge of the chip.

Wherein, in the step (2), the P-type high-temperature diffusion doping impurities are Al and B, the thermal diffusion temperature is 1100-1300° C., and the diffusion time is 15-20 h.

Wherein, the method for forming N+ and P+ diffusion regions on both sides of the N-type semiconductor substrate simultaneously in the step (6) is:

1) Use a phosphorus source for high-temperature diffusion, the pre-diffusion time is 1-2h, and the temperature is 1000-1200°C;

2) HF solution wet etching to remove the surface oxide layer,

3) Boron source is used for high temperature diffusion, the thermal diffusion time is 15-20h, and the temperature is 1100-1300°C, simultaneously forming P ⁺ guard ring, cathode N ⁺ area, cathode P ⁺ area, N ⁺ guard ring, and anode P ⁺ area , Anode N ⁺ area.

Wherein, in the step (7), the metal nickel layer is grown on both sides of the N-type semiconductor substrate, and the annealing to form the ohmic contact electrode includes:

1) Metal nickel is grown on both sides of the N-type semiconductor substrate by molecular beam epitaxy, with a thickness of

2) In N ₂ atmosphere, anneal at 600-700°C for 15-20min to form ohmic contact electrodes.

Wherein, in the step (9), the edge of the chip forms a grinding angle terminal, and adopting silicon rubber to protect the edge of the chip includes,

1) Use M14 SiC abrasive to grind and shape the edge of the chip to form two angles of 5°±5° and 25°±5°;

2) Apply silicone rubber evenly on the edge of the chip;

3) The chip with silicone rubber is cured at room temperature for 20 hours, and then cured at 150-200° C. for 20 hours.

The beneficial effects produced by adopting the above-mentioned technical scheme are:

The deep-level fast ionization conduction device provided by the present invention is a two-terminal device. When an overvoltage pulse 2 to 3 times higher than the forward blocking voltage is applied to both ends of the device, it has an ultra-fast voltage rise rate. , the deep energy level trap inside the device will release ionized electrons, causing a huge amount of plasma in the device, making the device conduct rapidly at a sub-nanosecond speed, and capable of switching thousands of amperes in a sub-nanosecond time current, has high reliability, and can be applied to high-power pulse source systems; the device in the present invention is pulse-triggered, and the trigger is simple, the working voltage is higher than > 5KV, the working current is higher than > 10KA, and the current rise rate is higher than > 100kA/μs, and conducts rapidly at a sub-nanosecond speed, it is very suitable for use in pulse power systems, and will have a wide range of applications in waste liquid and gas treatment, nano-engineering, biomedicine, high-power lasers, mining exploration and other fields prospect.

The manufacturing method of the deep-level rapid ionization conduction device provided by the present invention only needs to carry out photolithography on the front and back sides once, which reduces the complexity of the process, simplifies the process flow, has a simple process, and does not require complicated process equipment. Easy to implement; and compatible with existing silicon process technologies at no additional cost.

Description of drawings

1 is a schematic diagram of a deep-level fast ionization conduction device provided by the present invention;

Fig. 2 is a schematic diagram of the angled terminal structure of the deep-level rapid ionization conduction device provided by the present invention;

Fig. 3 is the schematic diagram of front cathode region and back anode region of N-type semiconductor substrate provided by the present invention;

Fig. 4 is the schematic diagram of front cathode region and back anode region of N-type semiconductor substrate provided by the present invention;

Fig. 5 is the schematic diagram of front cathode region and back anode region of N-type semiconductor substrate provided by the present invention;

Fig. 6 is the schematic diagram of front cathode region and back anode region of N-type semiconductor substrate provided by the present invention;

Fig. 7 is a schematic diagram of the manufacturing method of the deep-level fast ionization conduction device provided by the present invention;

Fig. 8 is a schematic diagram of a method for manufacturing a deep-level fast ionization conduction device provided by the present invention;

Fig. 9 is a schematic diagram of a method for manufacturing a deep-level fast ionization conduction device provided by the present invention;

Fig. 10 is a schematic diagram of a method for manufacturing a deep-level fast ionization conduction device provided by the present invention;

Fig. 11 is a schematic diagram of the manufacturing method of the deep-level fast ionization conduction device provided by the present invention;

In the figure: 1. N-type semiconductor substrate, 2. P-type diffusion region, 3. P ⁺ guard ring, 4. Cathode N ⁺ region, 5. Cathode P ⁺ region, 6. Cathode metal electrode, 7. N ⁺ protection ring, 8, anode P ⁺ area, 9, anode N ⁺ area, 10, anode metal electrode, 11, grinding angle terminal, 12, _SiO2 oxide layer, 13, metal nickel layer, 14, lead-tin solder.

detailed description

The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

It should be noted that, in the drawings, for convenience of illustration, the thicknesses of layers and regions are enlarged or reduced, and the shown size ratios do not represent actual size ratios. Although these figures do not accurately reflect the actual size of the material structure, they still completely reflect the mutual positional relationship between the various regions and structures.

Example 1

Fig. 1, Fig. 2, Fig. 3 are schematic diagrams of the first kind of deep-level fast ionization conduction device provided by the embodiment of the present invention, which specifically includes an N-type semiconductor substrate 1, and the front side of the N-type semiconductor substrate 1 is P Type diffusion region 2, cathode P+ region 5, cathode N+ region 4 and P+ guard ring 3 are distributed on P-type diffusion region 2, cathode metal electrode 6 is covered on cathode P+ region 5, cathode N+ region 4 and P+ guard ring 3; N Anode P+ region 8, anode N+ region 9 and N+ protection ring 7 are distributed on the back side of type semiconductor substrate 1, and anode metal electrode 10 is covered on anode P+ region 8, anode N+ region 9 and N+ protection ring 7. The device described in the present invention has a very high working voltage and working current, and the deep level trap will quickly release ionized electrons, with high current rising rate and fast conduction speed, and can switch thousands of times in sub-nanosecond time. The ampere current has high reliability and can be widely used in high-power pulse source systems. It will have broad application prospects in the fields of waste liquid and gas treatment, nano-engineering, biomedicine, high-power lasers, and mining exploration.

Wherein, the N-type semiconductor substrate 1 is made of N-type Si material, the resistivity is 90Ω·cm, and the thickness is 400-450 μm, and the depth of the P-type diffusion region 2 is 50-100 μm.

Among them, the cathode P ⁺ region 5 and the cathode N ⁺ region 4 distributed on the P-type diffusion region 2 are shown in Figure 3A, wherein the depth of the cathode P ⁺ region 5 is 15±5μm, and the surface sheet resistance is 5-10Ω/□; the cathode N ⁺ The depth of zone 4 is 20±5 μm, and the surface sheet resistance is 0.1-0.5Ω/□; the depth of P ⁺ guard ring 3 is 15±5 μm, and the surface sheet resistance is 5-10Ω/□.

Further, the anode P ⁺ region 8 and the anode N ⁺ region 9 distributed on the back of the N-type semiconductor substrate 1 are shown in Figure 3B, wherein the anode P ⁺ region 8 has a depth of 15±5 μm and a surface sheet resistance of 5-10Ω/□; the anode The depth of the N ⁺ region 9 is 20±5 μm, and the surface sheet resistance is 0.1-0.5Ω/□; the depth of the N ⁺ guard ring 7 is 15±5 μm, and the surface sheet resistance is 5-10Ω/□.

Further, both the anode metal electrode 10 and the cathode metal electrode 6 are metal molybdenum electrodes.

Further, two angles are adopted for the edge grinding terminal 11 of the N-type semiconductor substrate 1, which are respectively 5°±5° and 25°±5°.

The device of the present invention is pulse trigger, simple trigger, working voltage higher than > 5KV, working current higher than > 10KA, current rising rate higher than > 100kA/μs, and rapid conduction at sub-nanosecond speed, very suitable for pulse in the power system.

Example 2

Figure 1, Figure 2, and Figure 4 are schematic diagrams of the second deep-level fast ionization conduction device provided by the embodiment of the present invention. The structure in this embodiment is basically the same as that of Embodiment 1, except that Embodiment 2 The cathode P ⁺ region 5 and the cathode N ⁺ region 4 distributed on the middle P-type diffusion region 2 are shown in Figure 4C, and the anode P ⁺ region 8 and anode N ⁺ region 9 distributed on the back of the N-type semiconductor substrate 1 are shown in Figure 4D.

Example 3

Figure 1, Figure 2, and Figure 5 are schematic diagrams of the third deep-level fast ionization conduction device provided by the embodiment of the present invention. The structure in this embodiment is basically the same as that of Embodiment 1, except that Embodiment 3 The cathode P ⁺ region 5 and the cathode N ⁺ region 4 distributed on the middle P-type diffusion region 2 are shown in Figure 5E, and the anode P ⁺ region 8 and anode N ⁺ region 9 distributed on the back of the N-type semiconductor substrate 1 are shown in Figure 5F.

Example 4

Figure 1, Figure 2, and Figure 6 are schematic diagrams of the fourth deep-level fast ionization conduction device provided by the embodiment of the present invention. The structure in this embodiment is basically the same as that of Embodiment 1, except that Embodiment 4 The cathode P ⁺ region 5 and cathode N ⁺ region 4 distributed on the P-type diffusion region 2 are shown in Figure 6G, and the anode P ⁺ region 8 and anode N ⁺ region 9 distributed on the back of the N-type semiconductor substrate 1 are shown in Figure 6H.

The present invention also provides a method for manufacturing a deep-level fast ionization conduction device, the method comprising the following process flow:

(1) Cleaning and drying the N-type semiconductor substrate 1. The cleaning steps are: ultrasonic cleaning for 5-10 minutes, soaking in the boiling solution of HCl+HNO ₃ for 5-10 minutes, soaking in H ₂ O+H ₂ O ₂ + Soak in NH ₄ OH boiling solution for 5-10min, soak in deionized water for 5-10min, and then dry.

(2) As shown in Figure 7, P-type high-temperature diffusion doping is performed on the front side, using Al and B as the diffusion source, the thermal diffusion temperature is 1100-1300°C, the diffusion time is 15-20h, and the diffusion depth is 80-100μm to form a P-type diffusion District 2.

(3) Use HF solution for wet etching to remove the surface oxide layer.

(4) Fixing the doped side of the substrate, polishing and thinning the undoped side, and thinning the N-type semiconductor substrate 1 to a thickness of 400-450 μm.

(5) As shown in Figure 8, high temperature wet oxygen oxidation is used, and the oxidation temperature is 1100-1300° C. to form a SiO ₂ oxide layer 12 of 0.5-2 μm. Spin-coat photoresist on both sides of the substrate, etch _SiO2 through photolithography and wet processes, remove the SiO2 oxide layer 12, make patterns on the surface of the N-type semiconductor substrate 1, and form diffusion on both sides of the N-type semiconductor substrate 1 mask graphics.

(6) As shown in Figure 9, the phosphorus source is used for high-temperature diffusion, the pre-diffusion time is 1-2 hours, and the temperature is 1000-1200°C. Use HF solution wet etching to remove the surface oxide layer, and then use boron source for high-temperature diffusion. The thermal diffusion time is 15-20h and the temperature is 1100-1300°C. At the same time, P ⁺ protection ring 3, cathode N ⁺ area 4, and cathode P are formed. ⁺ region 5, N ⁺ guard ring 7, anode P ⁺ region 8, anode N ⁺ region 9.

(7) as shown in Figure 10, the metal nickel layer 13 is grown on both sides of the substrate respectively by molecular beam epitaxy, with a thickness of In _N2 atmosphere, anneal at 600-700°C for 15-20min to form ohmic contact electrodes.

(8) As shown in Figure 11, the chip is cut and scribed according to the designed size, and the chip is sintered on the metal molybdenum sheet with lead-tin solder 14 to form the cathode metal electrode 6 and the anode metal electrode 10.

(9) As shown in FIG. 2 , use M14 SiC abrasive to grind and shape the edge of the chip to form two angle grinding terminals 11 of 5°±5° and 25°±5°. Spread silicone rubber evenly on the edge of the chip, cure the chip with silicone rubber at room temperature for 20 hours, and then cure it at 150-200°C for 20 hours.

The manufacturing method only needs one front and back photolithography, which reduces the complexity of the process, simplifies the process flow, is simple, does not require complicated process equipment, and is easy to implement; it is also compatible with existing silicon process technology without adding additional cost.

Above, the technical scheme provided by the present invention has been introduced in detail. In the present invention, specific examples have been used to illustrate the implementation of the present invention. The descriptions of the above embodiments are only used to help understand the present invention. It should be pointed out that for those skilled in the art As far as people are concerned, on the premise of not departing from the principle of the present invention, some improvements can also be made to the present invention, and these improvements also fall within the protection scope of the claims of the present invention.

Claims (10)

1. a kind of quick ionization conduction device of deep energy level it is characterised in that including N-type semiconductor substrate (1), partly lead by described N-type The front of body substrate (1) is p type diffusion region (2), described p type diffusion region (2) is upper be distributed negative electrode P+ area (5), negative electrode N+ area (4) and P+ protection ring (3), in described negative electrode P+ area (5), negative electrode N+ area (4) and P+ protection ring (3) upper covering cathodic metal electrode (6)； The back side distributed anode P+ area (8) of described N-type semiconductor substrate (1), anode N+ area (9) and N+ protection ring (7), in anode P+ area (8), anode metal electrodes (10) are covered on anode N+ area (9) and N+ protection ring (7).

2. the quick ionization conduction device of deep energy level according to claim 1 is it is characterised in that described N-type semiconductor substrate (1) it is N-type Si material, resistivity is 90 Ω cm, thickness is 400-450 μm；The p-type in described N-type semiconductor substrate (1) front The depth of diffusion region (2) is 50-100 μm.

3. the quick ionization conduction device of deep energy level according to claim 1 is it is characterised in that on described p type diffusion region (2) Negative electrode P+ area (5) depth of distribution is 15 ± 5 μm, and surface square resistance is 5-10 Ω/；Negative electrode N+ area (4) depth is 20 ± 5 μm, surface square resistance is 0.1-0.5 Ω/；P+ protection ring (3) depth be 15 ± 5 μm, surface square resistance be 5-10 Ω/ □.

4. the quick ionization conduction device of deep energy level according to claim 1 is it is characterised in that described N-type semiconductor substrate (1) anode P+ area (8) depth of back side distribution is 15 ± 5 μm, and surface square resistance is 5-10 Ω/；Anode N+ area (9) depth For 20 ± 5 μm, surface square resistance is 0.1-0.5 Ω/；N+ protection ring (7) depth is 15 ± 5 μm, and surface square resistance is 5-10Ω/□.

5. the quick ionization conduction device of deep energy level according to claim 1 is it is characterised in that the anode metal of described device Electrode (10) and cathodic metal electrode (6) are molybdenum electrode.

6. a kind of manufacture method of the quick ionization conduction device of deep energy level is it is characterised in that comprise the following steps：

(1) drying and processing is carried out to N-type semiconductor substrate (1)；

(2) front carries out p-type High temperature diffusion doping；

(3) adopt wet etching, remove surface oxide layer；

(4) the doping face of fixing N-type semiconductor substrate (1), undoped p one side is polished reduction processing；

(5) form diffusion mask figure on N-type semiconductor substrate (1) two sides；

(6) form N+ and P+ diffusion region on N-type semiconductor substrate (1) two sides simultaneously；

(7) N-type semiconductor substrate (1) two sides growth metal nickel dam (13), annealing forms Ohm contact electrode；

(8) chip is sintered on metal molybdenum sheet, forms cathodic metal electrode (6), anode metal electrodes (10)；

(9) chip edge forms angle lap terminal (11), using silicon rubber, chip edge is protected.

7. the manufacture method of the quick ionization conduction device of deep energy level according to claim 6 is it is characterised in that step (two) Middle p-type High temperature diffusion impurity is A1, B, and thermal diffusion temperature is 1100-1300 DEG C, and diffusion time is 15-20h.

8. the manufacture method of the quick ionization conduction device of deep energy level according to claim 6 is it is characterised in that step (six) In simultaneously N-type semiconductor substrate (1) two sides formed N+ and P+ diffusion region method be：

1) High temperature diffusion is carried out using phosphorus source, the prediffusion time is 1-2h, temperature is 1000-1200 DEG C；

2) HF solution wet etching removes surface oxide layer；

3) High temperature diffusion is carried out using boron source, thermal diffusion time is 15-20h, temperature is 1100-1300 DEG C, form P simultaneously⁺Protection Ring (3), negative electrode N⁺Area (4), negative electrode P⁺Area (5), N⁺Protection ring (7), anode P⁺Area (8), anode N⁺Area (9).

9. the manufacture method of the quick ionization conduction device of deep energy level according to claim 6 is it is characterised in that step (seven) Middle N-type semiconductor substrate (1) two sides grows metal nickel dam, and annealing forms Ohm contact electrode and includes：

1) pass through molecular beam epitaxy and grow metallic nickel on N-type semiconductor substrate (1) two sides respectively, thickness is

2) in N₂In atmosphere, at 600-700 DEG C, annealing 15-20min forms Ohm contact electrode.

10. the manufacture method of the quick ionization conduction device of deep energy level according to claim 6 is it is characterised in that step (9) chips edge forms angle lap terminal (11), using silicon rubber, chip edge is carried out with protection and includes,

1) angle lap the shape handles are carried out using the SiC abrasive material of M14 to chip edge, form 5 ° ± 5 ° and 25 ° of ± 5 ° of two angles；

2) in chip edge uniform application silicon rubber；

3) chip with silicon rubber is solidified 20h at room temperature, solidify 20h afterwards at 150-200 DEG C.