CN106409661B - The quick ionization conduction device of deep energy level and its manufacturing method - Google Patents
The quick ionization conduction device of deep energy level and its manufacturing method Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 claims abstract description 55
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 238000009792 diffusion process Methods 0.000 claims abstract description 49
- 229910052751 metal Inorganic materials 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 32
- 238000000034 method Methods 0.000 claims description 27
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 14
- 229920002379 silicone rubber Polymers 0.000 claims description 10
- 238000012545 processing Methods 0.000 claims description 8
- 238000009826 distribution Methods 0.000 claims description 7
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 6
- 229910052750 molybdenum Inorganic materials 0.000 claims description 6
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02697—Forming conducting materials on a substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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Abstract
The invention discloses a kind of quick ionization conduction device of deep energy level and its manufacturing methods, belong to semiconductor device technology manufacturing technology field.The present invention includes N-type semiconductor substrate, and the front of the N-type semiconductor substrate is p type diffusion region, is distributed cathode P on the p type diffusion region+Area, cathode N+Area and P+Protection ring, in the cathode P+Area, cathode N+Area and P+Covered cathode metal electrode on protection ring；The back side distributed anode P of the N-type semiconductor substrate+Area, anode N+Area and N+Protection ring, in anode P+Area, anode N+Area and N+Anode metal electrodes are covered on protection ring.Device in the present invention has very high operating voltage, operating current, quick release is gone out ionization electronics by Deep Level Traps, current-rising-rate is high, conducting speed is fast, the electric current of kiloampere can be switched within the time of subnanosecond grade, reliability with higher can be widely applied in high-power pulse source system.
Description
Technical field
The invention belongs to semiconductor device technology manufacturing technology field more particularly to a kind of quick ionization conduction devices of deep energy level
Part and its manufacturing method.
Background technique
Pulse Power Techniques originate from the 40-50 age in 20th century, are initially applied to national defence scientific research field.The sixties,
J.C.Martin and its research group take a picture Blumlein transmission line technology applied to flash X-ray, make Pulse Power Techniques
Into practical stage.Then, Pulse Power Techniques are developed by leaps and bounds, and pulse peak power is more than 1014W, pulse width from μm
To ns or even ps magnitude.Currently, with the technological progress and application of the related fieldss such as material science, switching technique, energy storage technology
The continuous expansion of range, Pulse Power Techniques obtain more wide development space.
In pulse power system, traditional switch has gap, thyratron, vacuum tube and explosive switch etc..These
For traditional switch using widely in pulse power system, technology is also more mature.But these traditional switch have
Be difficult to the shortcomings that overcoming, such as working life is short, volume of switch is huge, poor synchronization, vulnerable to interference.In addition gap, lock stream
The switching power loss such as pipe are larger, need huge cooling system；And the repetition rate of the switches such as vacuum tube is extremely low.With semiconductor work
The rapid development of industry, semiconductor solid-state switch is in field of power electronics using increasingly extensive.Semiconductor solid-state switch has body
Product is small, the service life is long, steady operation and other merits, opens from GTO, GCT, IGBT and MOSFET semiconductor of earliest thyristor finally
Close the trend for showing and replacing traditional switch comprehensively.But these semiconductor switch still have certain defect, though GTO, GCT work
Voltage is higher, but repetition rate is very low；MOSFET working frequency is higher, but operating voltage is lower；In addition, these devices are all
Three terminal device needs when work that trigger signal occurs with complicated circuit, and when using multistage series-parallel, triggering system will become
It is sufficiently complex, very big difficulty is brought to operation and maintenance.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of quick ionization conduction devices of deep energy level, it is only necessary to pass through pulse
It is triggered, is not needed complicated triggering system, while there is very high operating voltage, operating current, Deep Level Traps will be fast
Quick-release releases ionization electronics, and current-rising-rate is high, conducting speed is fast, and kiloampere can be switched within the time of subnanosecond grade
Electric current, reliability with higher can be widely applied in high-power pulse source system.
In order to solve the above technical problems, the technical solution used in the present invention is: a kind of quick ionization conduction device of deep energy level
Part, including N-type semiconductor substrate, the front of the N-type semiconductor substrate are p type diffusion region, are distributed yin on the p type diffusion region
Pole P+Area, cathode N+Area and P+Protection ring, in the cathode P+Area, cathode N+Area and P+Covered cathode metal electrode on protection ring；
The back side distributed anode P of the N-type semiconductor substrate+Area, anode N+Area and N+Protection ring, in anode P+Area, anode N+Area and N+
Anode metal electrodes are covered on protection ring.
Further technical solution, the N-type semiconductor substrate are N-type Si material, and resistivity is 90 Ω cm, with a thickness of
400-450μm；The depth of the positive p type diffusion region of N-type semiconductor substrate is 50-100 μm.
Further technical solution, the cathode P being distributed on the p type diffusion region+Area's depth is 15 ± 5 μm, surface square
Resistance is 5-10 Ω/；Cathode N+Area's depth is 20 ± 5 μm, and surface square resistance is 0.1-0.5 Ω/；P+Protection ring depth
It is 15 ± 5 μm, surface square resistance is 5-10 Ω/.
Further technical solution, the anode P of the N-type semiconductor substrate back distribution+Area's depth is 15 ± 5 μm, table
Face square resistance is 5-10 Ω/；Anode N+Area's depth is 20 ± 5 μm, and surface square resistance is 0.1-0.5 Ω/；N+Protection
Ring depth is 15 ± 5 μm, and surface square resistance is 5-10 Ω/.
Further technical solution, the anode metal electrodes and cathodic metal electrode of the device are molybdenum electrode.
The present invention also provides a kind of manufacturing method of the quick ionization conduction device of deep energy level, which only needs to carry out
Front and back sides photoetching, reduces process complexity, simplifies process flow, and simple process does not need complicated process equipment,
It is easily achieved；And it is compatible with existing silicon process technology, it not will increase additional cost.
In order to solve the above technical problems, the technical solution used in the present invention is: a kind of quick ionization conduction device of deep energy level
The manufacturing method of part, comprising the following steps:
(1) cleaning, drying processing is carried out to N-type semiconductor substrate；
(2) front carries out the doping of p-type High temperature diffusion；
(3) wet etching is used, surface oxide layer is removed；
(4) the doping face of fixed N-type semiconductor substrate undoped will carry out on one side polishing reduction processing；
(5) diffusion mask figure is formed on N-type semiconductor substrate two sides；
(6) N is formed on N-type semiconductor substrate two sides simultaneously+And P+Diffusion region；
(7) N-type semiconductor substrate two sides grows metal nickel layer, and annealing forms Ohm contact electrode；
(8) chip is sintered in metal molybdenum on piece, forms cathodic metal electrode, anode metal electrodes；
(9) chip edge forms angle lap terminal, is protected using silicon rubber to chip edge.
Wherein, p-type High temperature diffusion impurity is Al, B in step (2), and High temperature diffusion temperature is 1100-1300 DEG C, is expanded
Dissipating the time is 15-20h.
Wherein, N is formed on N-type semiconductor substrate two sides simultaneously in step (6)+And P+The method of diffusion region are as follows:
1) High temperature diffusion is carried out using phosphorus source, the High temperature diffusion time is 1-2h, and temperature is 1000-1200 DEG C；
2) HF solution wet etching removes surface oxide layer；
3) High temperature diffusion is carried out using boron source, the High temperature diffusion time is 15-20h, and temperature is 1100-1300 DEG C, while shape
At P+Protection ring, cathode N+Area, cathode P+Area, N+Protection ring, anode P+Area, anode N+Area.
Wherein, N-type semiconductor substrate two sides grows metal nickel layer in step (7), and annealing forms Ohm contact electrode packet
It includes:
1) metallic nickel is grown on N-type semiconductor substrate two sides respectively by molecular beam epitaxy, with a thickness of
2) in N2The 15-20min that anneals in atmosphere, at 600-700 DEG C forms Ohm contact electrode.
Wherein, chip edge forms angle lap terminal in step (9), carries out protection to chip edge using silicon rubber and includes,
1) angle lap the shape handles are carried out to chip edge using the SiC abrasive material of M14, forms 5 ° ± 5 ° and 25 ° ± 5 ° two
Angle；
2) silicon rubber is uniformly smeared in chip edge；
3) chip with silicon rubber is solidified into 20h at room temperature, solidifies 20h at 150-200 DEG C later.
The beneficial effects of adopting the technical scheme are that
The quick ionization conduction device of deep energy level provided by the present invention is a kind of two terminal device, is higher than when device both ends apply
The overvoltage pulse that 2~3 times of forward blocking voltage, when having ultrafast voltage build-up rate, device inside Deep Level Traps will discharge
Ionization electronics out is caused to generate flood tide plasma in device, device is connected rapidly with the speed of subnanosecond grade, can be in Asia
The electric current of upper kiloampere is switched in the time of nanosecond, reliability with higher can be applied in high-power pulse source system；
Device in the present invention is pulse-triggered, triggering is simple, operating voltage be higher than > 5KV, operating current be greater than > 10KA, electric current rise
Rate is higher than > it 100kA/ μ s and is connected rapidly with the speed of subnanosecond grade, it is highly suitable to be applied in pulse power system, useless
The fields such as liquid exhaust-gas treatment, nanometer engineering, biologic medical, high power laser, mining exploration will have wide practical use.
The manufacturing method of the quick ionization conduction device of deep energy level provided by the invention, the manufacturing method need to only carry out once just
Reverse side photoetching, reduces process complexity, simplifies process flow, and simple process does not need complicated process equipment, is easy to real
It is existing；And it is compatible with existing silicon process technology, it not will increase additional cost.
Detailed description of the invention
Fig. 1 is the schematic diagram of the quick ionization conduction device of deep energy level provided by the invention；
Fig. 2 is the schematic diagram of the quick ionization conduction device angle lap terminal structure of deep energy level provided by the invention；
Fig. 3 is N-type semiconductor substrate provided by the invention front cathodic region and back anode area schematic diagram；
Fig. 4 is N-type semiconductor substrate provided by the invention front cathodic region and back anode area schematic diagram；
Fig. 5 is N-type semiconductor substrate provided by the invention front cathodic region and back anode area schematic diagram；
Fig. 6 is N-type semiconductor substrate provided by the invention front cathodic region and back anode area schematic diagram；
Fig. 7 is the schematic diagram of the quick ionization conduction device manufacturing method of deep energy level provided by the invention；
Fig. 8 is the schematic diagram of the quick ionization conduction device manufacturing method of deep energy level provided by the invention；
Fig. 9 is the schematic diagram of the quick ionization conduction device manufacturing method of deep energy level provided by the invention；
Figure 10 is the schematic diagram of the quick ionization conduction device manufacturing method of deep energy level provided by the invention；
Figure 11 is the schematic diagram of the quick ionization conduction device manufacturing method of deep energy level provided by the invention；
In figure: 1, N-type semiconductor substrate, 2, p type diffusion region, 3, P+Protection ring, 4, cathode N+Area, 5, cathode P+Area, 6, yin
Pole metal electrode, 7, N+Protection ring, 8, anode P+Area, 9, anode N+Area, 10, anode metal electrodes, 11, angle lap terminal, 12,
SiO2Oxide layer, 13, metal nickel layer, 14, plumber's solder.
Specific embodiment
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
It should be noted that in the figure for convenience of explanation, having zoomed in or out the thickness of layer and region, illustrated dimension ratio
Example does not represent actual size proportionate relationship.Although these figures not can accurately reaction material structure actual size,
They have still completely reacted the mutual alignment relation between each region and structure.
Embodiment 1
As shown in Figure 1, Figure 2, Fig. 3 is the quick ionization conduction device schematic diagram of the first deep energy level provided in an embodiment of the present invention,
It specifically includes N-type semiconductor substrate 1, and the front of N-type semiconductor substrate 1 is p type diffusion region 2, is distributed yin on p type diffusion region 2
Pole P+Area 5, cathode N+Area 4 and P+Protection ring 3, in cathode P+Area 5, cathode N+Area 4 and P+Covered cathode metal electrode on protection ring 3
6；The back side distributed anode P of N-type semiconductor substrate 1+Area 8, anode N+Area 9 and N+Protection ring 7, in anode P+Area 8, anode N+Area 9
And N+Anode metal electrodes 10 are covered on protection ring 7.Device of the present invention has very high operating voltage, work electricity
Quick release is gone out ionization electronics by stream, Deep Level Traps, and current-rising-rate is high, conducting speed is fast, can subnanosecond grade when
The electric current of kiloampere on interior switch, reliability with higher can be widely applied in high-power pulse source system, in waste liquid
The fields such as exhaust-gas treatment, nanometer engineering, biologic medical, high power laser, mining exploration will have wide practical use.
Wherein, N-type semiconductor substrate 1 is N-type Si material, and resistivity is 90 Ω cm, and with a thickness of 400-450 μm, p-type expands
Dissipating 2 depth of area is 50-100 μm.
Wherein, the cathode P being distributed on p type diffusion region 2+Area 5 and cathode N+Area 4 such as Fig. 3 A, wherein cathode P+5 depth of area is
15 ± 5 μm, surface square resistance is 5-10 Ω/；Cathode N+4 depth of area is 20 ± 5 μm, and surface square resistance is 0.1-0.5
Ω/□；P+3 depth of protection ring is 15 ± 5 μm, and surface square resistance is 5-10 Ω/.
Further, the anode P of 1 back side of N-type semiconductor substrate distribution+Area 8 and anode N+Area 9 such as Fig. 3 B, Anodic P+
8 depth of area is 15 ± 5 μm, and surface square resistance is 5-10 Ω/；Anode N+9 depth of area is 20 ± 5 μm, surface square resistance
For 0.1-0.5 Ω/；N+7 depth of protection ring is 15 ± 5 μm, and surface square resistance is 5-10 Ω/.
Further, anode metal electrodes 10 and cathodic metal electrode 6 are metal molybdenum electrode.
Further, 1 edge angle lap terminal 11 of N-type semiconductor substrate use, two angles, respectively 5 ° ± 5 ° and 25 ° ±
5°。
Device of the present invention is pulse-triggered, triggering is simple, operating voltage be higher than > 5KV, operating current be greater than > 10KA, electric current
Climbing is higher than > it 100kA/ μ s and is connected rapidly with the speed of subnanosecond grade, it is highly suitable to be applied in pulse power system.
Embodiment 2
As shown in Figure 1, Figure 2, Fig. 4 is the quick ionization conduction device schematic diagram of second of deep energy level provided in an embodiment of the present invention,
Structure in the present embodiment is substantially the same manner as Example 1, the difference is that the cathode being distributed on p type diffusion region 2 in embodiment 2
P+Area 5 and cathode N+Such as Fig. 4 C of area 4, the anode P of 1 back side of N-type semiconductor substrate distribution+Area 8 and anode N+Area 9 such as Fig. 4 D.
Embodiment 3
As shown in Figure 1, Figure 2, Fig. 5 is the quick ionization conduction device schematic diagram of the third deep energy level provided in an embodiment of the present invention,
Structure in the present embodiment is substantially the same manner as Example 1, the difference is that the cathode being distributed on p type diffusion region 2 in embodiment 3
P+Area 5 and cathode N+Such as Fig. 5 E of area 4, the anode P of 1 back side of N-type semiconductor substrate distribution+Area 8 and anode N+Area 9 such as Fig. 5 F.
Embodiment 4
As shown in Figure 1, Figure 2, Fig. 6 is the quick ionization conduction device schematic diagram of the 4th kind of deep energy level provided in an embodiment of the present invention,
Structure in the present embodiment is substantially the same manner as Example 1, the difference is that the cathode being distributed on p type diffusion region 2 in embodiment 4
P+Area 5 and cathode N+Such as Fig. 6 G of area 4, the anode P of 1 back side of N-type semiconductor substrate distribution+Area 8 and anode N+Area 9 such as Fig. 6 H.
The present invention also provides a kind of manufacturing method of the quick ionization conduction device of deep energy level, this method includes following technique
Process:
(1) cleaning, drying processing, cleaning step are carried out to N-type semiconductor substrate 1 are as follows: ultrasonic cleaning 5-10min, in HCl
+HNO3Boiling solution in impregnate 5-10min, in H2O+H2O2+NH45-10min is impregnated in the boiling solution of OH, in deionized water
Soaking flushing 5-10min carries out drying and processing later.
(2) such as Fig. 7, front progress p-type High temperature diffusion doping, using Al, B as diffusion source, High temperature diffusion temperature is
1100-1300 DEG C, diffusion time 15-20h, 80-100 μm of diffusion depth, form p type diffusion region 2.
(3) wet etching is carried out using HF solution, removes surface oxide layer.
(4) fixed Substrate Doping face N-type semiconductor substrate 1 will be thinned undoped with polishing reduction processing is carried out on one side
To with a thickness of 400-450 μm.
(5) such as Fig. 8, using high temperature wet-oxygen oxidation, oxidizing temperature is 1100-1300 DEG C, forms 0.5-2 μm of SiO2Oxygen
Change layer 12.In the two-sided spin coating photoresist of substrate, SiO is corroded by photoetching process and wet processing2, remove SiO2Oxide layer 12,
1 surface of N-type semiconductor substrate makes figure, forms diffusion mask figure on 1 two sides of N-type semiconductor substrate.
(6) such as Fig. 9, High temperature diffusion is carried out using phosphorus source, the High temperature diffusion time is 1-2h, and temperature is 1000-1200 DEG C.
Surface oxide layer is removed using HF solution wet etching, High temperature diffusion is carried out using boron source later, the High temperature diffusion time is 15-
20h, temperature are 1100-1300 DEG C, are formed simultaneously P+Protection ring 3, cathode N+Area 4, cathode P+Area 5, N+Protection ring 7, anode P+Area
8, anode N+Area 9.
(7) such as Figure 10, metal nickel layer 13 is grown on substrate two sides respectively by molecular beam epitaxy, with a thickness ofIn N2In atmosphere, anneal 15-20min at 600-700 DEG C, forms Ohm contact electrode.
(8) such as Figure 11, chip is subjected to cutting scribing according to design size, is sintered chip using plumber's solder 14
Metal molybdenum on piece forms cathodic metal electrode 6, anode metal electrodes 10.
(9) such as Fig. 2, angle lap the shape handles is carried out to chip edge using the SiC abrasive material of M14, form 5 ° ± 5 ° and 25 °
The angle lap terminal 11 of ± 5 ° of two angles.Silicon rubber is uniformly smeared in chip edge, at room temperature by the chip with silicon rubber
Solidify 20h, solidifies 20h at 150-200 DEG C later.
The manufacturing method need to only carry out a front and back sides photoetching, reduce process complexity, simplify process flow, technique
Simply, complicated process equipment is not needed, it is easy to accomplish；And it is compatible with existing silicon process technology, not will increase it is additional at
This.
Technical solution provided by the invention is described in detail above, using specific case to the present invention in the present invention
Embodiment be expounded, the above embodiments are only used to help understand the present invention, it is noted that for this skill
For the technical staff in art field, without departing from the principle of the present invention, can also several improvement be carried out to the present invention, these
Improvement is also fallen within the protection scope of the claims of the present invention.
Claims (10)
1. a kind of quick ionization conduction device of deep energy level, which is characterized in that including N-type semiconductor substrate (1), the N-type is partly led
The front of body substrate (1) is p type diffusion region (2), is distributed cathode P on the p type diffusion region (2)+Area (5), cathode N+Area (4) and P+Protection ring (3), in the cathode P+Area (5), cathode N+Area (4) and P+Covered cathode metal electrode (6) on protection ring (3)；Institute
State the back side distributed anode P of N-type semiconductor substrate (1)+Area (8), anode N+Area (9) and N+Protection ring (7), in anode P+Area
(8), anode N+Area (9) and N+Anode metal electrodes (10) are covered on protection ring (7).
2. the quick ionization conduction device of deep energy level according to claim 1, which is characterized in that the N-type semiconductor substrate
It (1) is N-type Si material, resistivity is 90 Ω cm, with a thickness of 400-450 μm；The positive p-type of the N-type semiconductor substrate (1)
The depth of diffusion region (2) is 50-100 μm.
3. the quick ionization conduction device of deep energy level according to claim 1, which is characterized in that on the p type diffusion region (2)
The cathode P of distribution+Area's (5) depth is 15 ± 5 μm, and surface square resistance is 5-10 Ω/；Cathode N+Area's (4) depth is 20 ± 5 μ
M, surface square resistance are 0.1-0.5 Ω/；P+Protection ring (3) depth be 15 ± 5 μm, surface square resistance be 5-10 Ω/
□。
4. the quick ionization conduction device of deep energy level according to claim 1, which is characterized in that the N-type semiconductor substrate
(1) the anode P of back side distribution+Area's (8) depth is 15 ± 5 μm, and surface square resistance is 5-10 Ω/；Anode N+Area (9) depth
It is 20 ± 5 μm, surface square resistance is 0.1-0.5 Ω/；N+Protection ring (7) depth is 15 ± 5 μm, and surface square resistance is
5-10Ω/□。
5. the quick ionization conduction device of deep energy level according to claim 1, which is characterized in that the anode metal of the device
Electrode (10) and cathodic metal electrode (6) are molybdenum electrode.
6. a kind of manufacturing method of the quick ionization conduction device of deep energy level, which comprises the following steps:
(1) cleaning, drying processing is carried out to N-type semiconductor substrate (1)；
(2) front carries out the doping of p-type High temperature diffusion；
(3) wet etching is used, surface oxide layer is removed；
(4) the doping face of fixed N-type semiconductor substrate (1) undoped will carry out on one side polishing reduction processing；
(5) diffusion mask figure is formed on N-type semiconductor substrate (1) two sides；
(6) N+ and P is formed on N-type semiconductor substrate (1) two sides simultaneously+Diffusion region；
(7) N-type semiconductor substrate (1) two sides growth metal nickel layer (13), annealing form Ohm contact electrode；
(8) chip is sintered in metal molybdenum on piece, forms cathodic metal electrode (6), anode metal electrodes (10)；
(9) chip edge forms angle lap terminal (11), is protected using silicon rubber to chip edge.
7. the manufacturing method of the quick ionization conduction device of deep energy level according to claim 6, which is characterized in that step (2)
Middle p-type High temperature diffusion impurity is Al, B, and High temperature diffusion temperature is 1100-1300 DEG C, diffusion time 15-20h.
8. the manufacturing method of the quick ionization conduction device of deep energy level according to claim 6, which is characterized in that step (6)
In simultaneously N-type semiconductor substrate (1) two sides formed N+ and P+The method of diffusion region are as follows:
1) High temperature diffusion is carried out using phosphorus source, the High temperature diffusion time is 1-2h, and temperature is 1000-1200 DEG C；
2) HF solution wet etching removes surface oxide layer；
3) High temperature diffusion is carried out using boron source, the High temperature diffusion time is 15-20h, and temperature is 1100-1300 DEG C, is formed simultaneously P+It protects
Retaining ring (3), cathode N+Area (4), cathode P+Area (5), N+Protection ring (7), anode P+Area (8), anode N+Area (9).
9. the manufacturing method of the quick ionization conduction device of deep energy level according to claim 6, which is characterized in that step (7)
Middle N-type semiconductor substrate (1) two sides grows metal nickel layer, and annealing forms Ohm contact electrode and includes:
1) metallic nickel is grown on N-type semiconductor substrate (1) two sides respectively by molecular beam epitaxy, with a thickness of
2) in N2The 15-20min that anneals in atmosphere, at 600-700 DEG C forms Ohm contact electrode.
10. the manufacturing method of the quick ionization conduction device of deep energy level according to claim 6, which is characterized in that step
(9) chip edge forms angle lap terminal (11) in, carries out protection to chip edge using silicon rubber and includes,
1) angle lap the shape handles are carried out to chip edge using the SiC abrasive material of M14, forms 5 ° ± 5 ° and 25 ° of ± 5 ° of two angles；
2) silicon rubber is uniformly smeared in chip edge；
3) chip with silicon rubber is solidified into 20h at room temperature, solidifies 20h at 150-200 DEG C later.
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| US3996601A (en) * | 1974-07-15 | 1976-12-07 | Hutson Jerald L | Shorting structure for multilayer semiconductor switching devices |
| US4214255A (en) * | 1977-02-07 | 1980-07-22 | Rca Corporation | Gate turn-off triac with dual low conductivity regions contacting central gate region |
| CN103811471A (en) * | 2012-09-07 | 2014-05-21 | 联发科技（新加坡）私人有限公司 | Guard ring structure and method for forming the same |
| CN105304516A (en) * | 2015-09-22 | 2016-02-03 | 上海华虹宏力半导体制造有限公司 | PN junction dyeing method |
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| US7842971B2 (en) * | 2008-02-22 | 2010-11-30 | Intersil Americas Inc. | Silicon-controlled rectifier (SCR) device for high-voltage electrostatic discharge (ESD) applications |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3996601A (en) * | 1974-07-15 | 1976-12-07 | Hutson Jerald L | Shorting structure for multilayer semiconductor switching devices |
| US4214255A (en) * | 1977-02-07 | 1980-07-22 | Rca Corporation | Gate turn-off triac with dual low conductivity regions contacting central gate region |
| CN103811471A (en) * | 2012-09-07 | 2014-05-21 | 联发科技（新加坡）私人有限公司 | Guard ring structure and method for forming the same |
| CN105304516A (en) * | 2015-09-22 | 2016-02-03 | 上海华虹宏力半导体制造有限公司 | PN junction dyeing method |
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