CN106384717A - Formation method of fin-type field effect transistor - Google Patents
Formation method of fin-type field effect transistor Download PDFInfo
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- CN106384717A CN106384717A CN201510456542.4A CN201510456542A CN106384717A CN 106384717 A CN106384717 A CN 106384717A CN 201510456542 A CN201510456542 A CN 201510456542A CN 106384717 A CN106384717 A CN 106384717A
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- 230000005669 field effect Effects 0.000 title claims abstract description 66
- 238000000034 method Methods 0.000 title claims abstract description 46
- 230000015572 biosynthetic process Effects 0.000 title abstract description 16
- 239000000463 material Substances 0.000 claims abstract description 227
- 239000004065 semiconductor Substances 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 238000005530 etching Methods 0.000 claims abstract description 43
- 125000006850 spacer group Chemical group 0.000 claims description 137
- 238000005516 engineering process Methods 0.000 claims description 26
- 239000002243 precursor Substances 0.000 claims description 13
- 238000001312 dry etching Methods 0.000 claims description 10
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 5
- 239000002019 doping agent Substances 0.000 claims description 5
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 description 19
- 238000002955 isolation Methods 0.000 description 13
- 239000006227 byproduct Substances 0.000 description 11
- 238000010586 diagram Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 208000035985 Body Odor Diseases 0.000 description 2
- 206010055000 Bromhidrosis Diseases 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 238000002353 field-effect transistor method Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical group [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A formation method of a fin-type field effect transistor comprises the following steps of providing a semiconductor substrate possessing a grid-structure dense area and a grid-structure sparse area, wherein a semiconductor substrate surface of the grid-structure dense area has a first grid structure crossing a first fin portion; and a semiconductor substrate surface of the grid-structure sparse area has a second grid structure crossing a second fin portion; forming a side wall material layer, wherein the side wall material layer includes a first side wall material layer and a second side wall material layer; the first side wall material layer covers the first grid structure, the second grid structure, a first fin portion top surface and a second fin portion top surface; the second side wall material layer covers a first fin portion side wall and a second fin portion side wall; and the second side wall material layer is thinner than the first side wall material layer; and etching the side wall material layer to form a side wall, wherein the side wall completely covers side walls of the first grid structure and the second grid structure and completely exposes the first fin portion and the second fin portion. By using the formation method of the fin-type field effect transistor, performance of the fin-type field effect transistor is increased.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, to a kind of formation side of fin formula field effect transistor
Method.
Background technology
MOS transistor is one of most important element in modern integrated circuits.The basic knot of MOS transistor
Structure includes：Semiconductor substrate；Positioned at the grid structure of semiconductor substrate surface, positioned at grid structure side
Source region and the drain region being located in grid structure opposite side Semiconductor substrate in Semiconductor substrate.MOS transistor
By in grid applied voltage, adjusting and switching signal being produced by the electric current of grid structure bottom channel.
With the development of semiconductor technology, the control to channel current of the MOS transistor of traditional plane formula
Ability dies down, and causes serious leakage current.Fin formula field effect transistor (Fin FET) is a kind of emerging
Multi-gate device, it generally comprises the fin protruding from semiconductor substrate surface, fin described in covering part
Top surface and the grid structure of side wall, the source region in the fin of grid structure side and be located at grid
Drain region in the fin of structure opposite side.
The method forming fin formula field effect transistor includes：Semiconductor substrate, described Semiconductor substrate are provided
Surface has fin and the grid structure across described fin of projection, described grid structure covering part institute
State top surface and the side wall of fin；Form side wall in grid structure both sides side wall；With side wall and grid knot
Structure carries out ion implanting for mask to the fin of grid structure both sides and forms heavily doped source region and drain region.
Reduce further with characteristic size, prior art formed the performance of fin formula field effect transistor and
Reliability is poor.
Content of the invention
The problem that the present invention solves is to provide a kind of forming method of fin formula field effect transistor, improves fin
The performance of field-effect transistor.
For solving the above problems, the present invention provides a kind of forming method of fin formula field effect transistor, including：
There is provided Semiconductor substrate, Semiconductor substrate has grid structure compact district and grid structure rarefaction, grid
The semiconductor substrate surface of structure compact district has the first fin and the first grid knot across the first fin
Structure, the top surface of first grid structure covering part the first fin and side wall；Grid structure rarefaction
Semiconductor substrate surface has the second fin and the second grid structure across the second fin, and second grid is tied
The top surface of structure covering part second fin and side wall；Form spacer material layer, described spacer material layer
Cover grid structure compact district and grid structure rarefaction, described spacer material layer includes the first spacer material
Layer and the second spacer material layer, first spacer material layer cover first grid structure, second grid structure,
First fin top surface of first grid structure both sides and the second fin top of second grid structure both sides
Surface, the second spacer material layer covers the first fin side wall and the second grid knot of first grid structure both sides
Second fin side wall of structure both sides, and the thickness of described second spacer material layer is less than the first spacer material layer
Thickness；Etching spacer material layer, forms side wall, and described side wall is completely covered the side of first grid structure
The side wall of wall and second grid structure, and described side wall is completely exposed the first fin of first grid structure both sides
Portion surface and the second fin portion surface of second grid structure both sides.
Optionally, the step of the described spacer material layer of formation is：From first grid structure and second grid knot
Structure top is passed through the first precursor gas for forming spacer material layer；Before plasmarized described first
Drive bromhidrosis body；Described the first plasmarized precursor gas adsorb first first grid body structure surface,
Second grid body structure surface, the first fin top surface of first grid structure both sides and second grid structure
Second fin top surface of both sides, then adsorb the first fin side wall in first grid structure both sides and
Second fin side wall of second grid structure both sides；Described the first plasmarized precursor gas and the
One grid structure, second grid structure, the first fin and the second fin carry out chemical reaction, are formed described
Spacer material layer.
Optionally, dry etching board forms described spacer material layer.
Optionally, in described dry etching board, form described spacer material layer and etch described spacer material
The process of layer is carried out simultaneously.
Optionally, in described dry etching board, to described spacer material after the described spacer material layer of formation
Layer performs etching.
Optionally, the technological parameter of the described spacer material layer of formation is：Using gas be N2, N2Stream
Measure as 100sccm～500sccm, plasmarized source power is 500KeV～1500KeV, bias voltage is
0V.
Optionally, the technological parameter of the described spacer material layer of formation is：Using gas be CH4, CH4's
Flow is 100sccm～500sccm, and plasmarized source power is 500KeV～1500KeV, bias voltage
For 0V.
Optionally, the thickness of described first spacer material layer is 10nm～30nm.
Optionally, the thickness of described second spacer material layer is 5nm～25nm.
Optionally, etched using the technique that isotropism dry carving technology and anisotropy dry carving technology combine
Described spacer material layer.
Optionally, described side wall material is etched using isotropism dry carving technology after first anisotropy dry carving technology
The bed of material.
Optionally, the parameter of first anisotropy dry carving technology is：Using gas be CH3F、O2And He,
CH3The flow of F is 100sccm～250sccm, O2Flow be 50sccm～200sccm, the flow of He is
300sccm～500sccm, source radio-frequency power is 1000KeV～1800KeV, and biasing radio-frequency power is
200KeV～250KeV, etching cavity pressure is 50mtorr～100mtorr；Isotropism dry carving technology afterwards
Parameter is：Using gas include CH3F、CO2And Ar, CH3The flow of F is 50sccm～100sccm,
CO2Flow be 10sccm～60sccm, the flow of Ar is 300sccm～800sccm, and source radio-frequency power is
500KeV～1000KeV, biasing radio-frequency power is 0KeV～50KeV, and etching cavity pressure is
50mtorr～1000mtorr.
Optionally, also include：After forming described side wall, grid structure compact district formed the first source region and
First drain region, described first source region is located at the side wall of grid structure compact district and first grid structure side
First fin portion surface, described first drain region is located at the side wall of grid structure compact district and first grid structure is another
First fin portion surface of side；Form the second source region and the second drain region in grid structure rarefaction, described the
Two source regions are located at the side wall of grid structure rarefaction and the second fin portion surface of second grid structure side, institute
State the second drain region and be located at the side wall of grid structure rarefaction and the second fin table of second grid structure opposite side
Face.
Optionally, when grid structure compact district is used for type and the grid of the fin formula field effect transistor of formation
Structure rarefaction be used for the type of fin formula field effect transistor that formed identical when, described first source region, the
One drain region, the second source region and the second drain region are formed simultaneously.
Optionally, form described first source region, the step in the first drain region, the second source region and the second drain region is：
The first fin in first grid structure both sides and the second fin portion surface extension of second grid structure both sides
Growth source-drain area material layer；To described source-drain area material layer dopant ion；After dopant ion, to described source
Drain region material layer is made annealing treatment.
Optionally, when grid structure compact district and grid structure rarefaction are used for forming N-type fin field effect crystalline substance
During body pipe, the material of described source-drain area material layer is carborundum；When grid structure compact district and grid structure
When rarefaction is used for being formed p-type fin formula field effect transistor, the material of described source-drain area material layer is germanium
Silicon.
Optionally, when grid structure compact district and grid structure rarefaction are used for forming N-type fin field effect crystalline substance
During body pipe, described ion is N-type ion；When grid structure compact district and grid structure rarefaction are used for being formed
During p-type fin formula field effect transistor, described ion is p-type ion.
Compared with prior art, technical scheme has advantages below：
The forming method of the fin formula field effect transistor that the present invention provides, the spacer material thickness degree of formation divides
Cloth has differences, and specifically, described spacer material layer is in first grid body structure surface, second grid structure
The thickness on surface, the first fin top surface and the second fin top surface exists more than described spacer material layer
First fin sidewall surfaces and the thickness of the second fin sidewall surfaces, therefore, etch described spacer material layer
After can form side wall, described side wall is completely covered the side wall of first grid structure and second grid structure
Side wall and first fin portion surface of first grid structure both sides and second grid structure both sides are completely exposed
Second fin portion surface.Because described side wall is completely covered first grid structure side wall, so in first grid
Will not be in first grid structure side wall during the first fin portion surface epitaxial growth source-drain area material layer of structure both sides
Form source-drain area material layer；Because described side wall is completely covered second grid structure side wall, in second grid
Will not be in second grid structure side wall during the second fin portion surface epitaxial growth source-drain area material layer of structure both sides
Form source-drain area material layer.So as to improve the performance of fin formula field effect transistor.
Brief description
Fig. 1 is the structural representation of fin formula field effect transistor in one embodiment of the invention.
Fig. 2 to Fig. 8 is the structure of the forming process of fin formula field effect transistor in another embodiment of the present invention
Schematic diagram.
Specific embodiment
When the fin formula field effect transistor that prior art is formed reduces further with characteristic size, fin field
The Performance And Reliability of effect transistor is poor.
One embodiment of the invention provides a kind of forming method of fin formula field effect transistor, with reference to Fig. 1, bag
Include：There is provided Semiconductor substrate 100, described Semiconductor substrate 100 has grid structure compact district (I region)
With grid structure rarefaction (II region), Semiconductor substrate 100 surface of grid structure compact district has
One fin 120 and the first grid structure 130 across the first fin 120, first grid structure 130 covers
The top surface of part the first fin 120 and side wall；Semiconductor substrate 100 table of grid structure rarefaction
Face has the second fin 121 and the second grid structure 131 across the second fin 121, second grid structure
The top surface of 131 covering part the second fins 121 and side wall；Spacer material layer is formed using depositing operation,
Described spacer material layer covers first area and second area；Etching spacer material layer, forms side wall 140,
Described side wall 140 is located at first grid structure 130 sidewall surfaces and second grid structure 131 sidewall surfaces,
And described side wall is completely exposed the first fin 120 surface and the second gate of first grid structure 130 both sides
Second fin 121 surface of pole structure 131 both sides.
Research finds, the fin formula field effect transistor that said method is formed the reason still there is poor performance
In：
Described spacer material layer is used for forming covering first grid structure side wall and second grid structure side wall,
And first fin portion surface of first grid structure both sides and the second of second grid structure both sides is completely exposed
The side wall of fin portion surface.I.e. after forming spacer material layer, need the first of first grid structure both sides
The spacer material layer of the second fin portion surface of the spacer material layer of fin portion surface and second grid structure both sides
Remove.During generally adopting etching technics to remove above-mentioned part spacer material layer, described etching technics
Etch rate affected by etch by-products are how many, when more by-product is centered around side wall to be etched
Material surface and when not excluding, etch rate can decline.
Specifically, in the above embodiment of the present invention, because, in identical volume, first grid is tied
The area of the first fin of structure both sides is less than the area of the second fin of second grid structure both sides, so
In identical volume, the area covering the spacer material layer of the first fin side wall is less than covering the second fin side
The area of the spacer material layer of wall, etching covers the by-product that the spacer material layer of the first fin side wall produces
The by-product that the spacer material layer covering the second fin side wall less than etching produces, and cover the first fin side
The more difficult discharge of by-product after the spacer material layer etching of wall and the second fin side wall, so etching covering the
The speed of the spacer material layer of one fin is more than the speed that etching covers the spacer material layer of the second fin.
Therefore, the critical moment being completely exposed in the first fin portion surface of first grid structure both sides, second
Also there is part spacer material layer in the second fin portion surface of grid structure both sides, so that second grid knot
Second fin portion surface of structure both sides is fully exposed so that follow-up the first source region being formed in I region and the
One drain region and II region formed the second source region and the second drain region highly consistent, need increase offside
The etching degree of the walling bed of material, because the etching degree of the offside walling bed of material increases and adopts depositing operation shape
The thickness of the described spacer material layer becoming is more uniform, so in first grid structure and second grid structure side
The described side wall that wall surface is formed can expose part first grid structure side wall and second grid structure side wall
(with reference to the position 150 of dotted line mark in Fig. 1).Epitaxial growth technology is subsequently used to form first in I region
During source region and the first drain region, also can be in the position epitaxial growth material of first grid structure side wall exposure
The bed of material；Subsequently use epitaxial growth technology during II region forms the second source region and the second drain region,
The position epitaxial grown material layer that can expose in second grid structure side wall.Thus reducing fin field effect
The performance of transistor.
On this basis, another embodiment of the present invention provides a kind of formation side of fin formula field effect transistor
Method, including：There is provided Semiconductor substrate, Semiconductor substrate has grid structure compact district and grid structure is dilute
Thin area, the semiconductor substrate surface of grid structure compact district has the first fin and across the first fin
One grid structure, the top surface of first grid structure covering part the first fin and side wall；Grid structure
The semiconductor substrate surface of rarefaction has the second fin and the second grid structure across the second fin, the
The top surface of two grid structure covering part the second fins and side wall；Form spacer material layer, described side
The walling bed of material covers first area and second area, described spacer material layer include the first spacer material layer and
Second spacer material layer, first spacer material layer cover first grid structure, second grid structure, first
First fin top surface of grid structure both sides and the second fin top table of second grid structure both sides
Face, the second spacer material layer covers the first fin side wall and the second grid structure of first grid structure both sides
Second fin side wall of both sides, and the thickness of described second spacer material layer is less than the first spacer material layer
Thickness；Etching spacer material layer, forms side wall, and described side wall is completely covered the side wall of first grid structure
With the side wall of second grid structure, and described side wall is completely exposed the first fin of first grid structure both sides
Surface and the second fin portion surface of second grid structure both sides.
The side wall of first grid structure and the side wall of second grid structure are completely covered due to described side wall, and
Described side wall is completely exposed the first fin portion surface and the second grid structure both sides of first grid structure both sides
The second fin portion surface.So that subsequently using epitaxial growth technology to form the first source region and the first drain region in I region
During, it is to avoid in first grid structure side wall epitaxial grown material layer；So that subsequently being given birth to extension
During long technique forms the second source region and the second drain region in II region, it is to avoid in second grid structure
Side wall epitaxial grown material layer.So as to improve the performance of fin formula field effect transistor.
Understandable for enabling the above objects, features and advantages of the present invention to become apparent from, below in conjunction with the accompanying drawings
The specific embodiment of the present invention is described in detail.
In conjunction with referring to figs. 2 to Fig. 4, Fig. 3 is along the first fin bearing of trend (A-A1 in I region in Fig. 2
Axis) and II region the second fin bearing of trend (A2-A3 axis) profile；Fig. 4 is along figure
The profile of B-B1 axis in 2, described B-B1 diameter parallel is in first grid extensibility of structure direction and
Two grid structure bearing of trends, and described B-B1 axis by the first fin of first grid structure side and
Second fin of second grid structure side.There is provided Semiconductor substrate 200, Semiconductor substrate 200 has grid
Pole structure compact district (I region) and grid structure rarefaction (II region), the Semiconductor substrate 200 in I region
Surface has the first fin 220 and the first grid structure 230 across the first fin 220, the described first grid
The top surface of pole structure 230 covering part the first fin 220 and side wall；The Semiconductor substrate in II region
200 surfaces have the second fin 221 and a second grid structure 233 across the second fin 221, and described
The top surface of two grid structure 233 covering part the second fin 221 and side wall.
Described Semiconductor substrate 200 provides technique platform for being subsequently formed fin formula field effect transistor.
Described Semiconductor substrate 200 can be monocrystal silicon, polysilicon or non-crystalline silicon；Semiconductor substrate 200
Can also be the semi-conducting materials such as silicon, germanium, SiGe, GaAs；Described Semiconductor substrate 200 is permissible
It is body material or composite construction, such as silicon-on-insulator；Described Semiconductor substrate 200 is acceptable
It is other semi-conducting material, no longer illustrate one by one here.In the present embodiment, described Semiconductor substrate 200
Material be silicon.
Described Semiconductor substrate 200 includes I region and II region, and I region is used for being subsequently formed grid structure
Intensive fin formula field effect transistor, II region is used for being subsequently formed the sparse fin field effect of grid structure
Transistor.
The acting as of described first fin 220：There is provided carrier for being subsequently formed first grid structure；Described
The acting as of second fin 221：There is provided carrier for being subsequently formed second grid structure.
In the present embodiment, form described first fin 220 and the step of the second fin 221 is：Partly leading
Body substrate 200 surface forms the mask layer of patterning, and the mask layer of described patterning defines the first fin 220
Position with the second fin 221；With the mask layer of described patterning partly leading for mask etching segment thickness
Body substrate 200, forms the first fin 220 in I region, forms the second fin 221 in II region.
Because described first fin 220 and the second fin 221 are formed by etch semiconductor substrates 200,
So the first fin 220 is identical with the material of Semiconductor substrate 200 with the material of the second fin 221, institute
State the first fin 220 and the material of the second fin 221 is silicon.In other embodiments, described first
The material of fin 220 and the second fin 221 can be differed with the material of Semiconductor substrate 200.
In the present embodiment, three the first fins 220 are had as an example with I region, is had with II region
Three the second fins 221 as an example, do not represent the first fin 220 and the second fin in actual process
221 number.The first fin 220 and the concrete number of the second fin 221 can be selected as needed.
Described isolation structure 210 act as the first adjacent fin 220 of electric isolation, and electric isolation phase
The second adjacent fin 221.
The material of described isolation structure 210 includes silicon oxide or silicon oxynitride.In the present embodiment, isolation junction
The material of structure 210 is silicon oxide.
The step forming described isolation structure 210 is：Form the isolation structure covering I region and II region
Material layer (not shown), and the whole surface of described isolation structure material layer is higher than the first fin 220 and the
The top surface of two fins 221；Using flatening process, such as cmp, planarization described every
From structural material, with the top surface of the first fin 220 and the second fin 221 as stop-layer；Return and carve
Erosion portions of isolation structure material layer, forms isolation on Semiconductor substrate 200 surface in I region and II region
Structure 210, the surface of described isolation structure 210 is less than the top of the first fin 220 and the second fin 221
Surface.
Described first grid structure 230 includes across the first gate dielectric layer 231 of the first fin 220 and covers
Cover the first gate electrode layer 232 of the first gate dielectric layer 231.Wherein, the first gate dielectric layer 231 is located at I area
Isolation structure 210 surface in domain, the top surface of covering part the first fin 220 and side wall；Described
Two grid structures 233 include being situated between across the second gate dielectric layer 234 of the second fin 221 and covering second gate
Second gate electrode layer 235 of matter layer 234.Wherein, the second gate dielectric layer 234 is located at the isolation in II region
Structure 210 surface, the top surface of covering part the second fin 221 and side wall.
In the present embodiment, the material of described first gate dielectric layer 231 and the second gate dielectric layer 234 is oxidation
Silicon, the material of described first gate electrode layer 232 and the second gate electrode layer 235 is polysilicon.Other real
Apply in example, can also be：The material of described first gate dielectric layer 231 and the second gate dielectric layer 234 is high K
Dielectric material, the material of described first gate electrode layer 232 and the second gate electrode layer 235 is metal.
Form first grid structure 230 and the method for second grid structure 233 is：Using depositing operation shape
Become to cover I region and the gate dielectric material layer (not shown) in II region and the grid of cover grid layer of dielectric material
Electrode material layer (not shown)；Form patterned mask layer in described gate material layer surface (not scheming
Show), described patterned mask layer defines the position of first grid structure 230 and second grid structure 233；
With described patterned mask layer as mask, etch described gate dielectric material layer and described layer of gate electrode material,
Until exposing the first fin 220 and the top surface of the second fin 221, form first grid structure 230
With second grid structure 233.
In the present embodiment, two first grid structures 230 are had as an example with I region, with II region
There are two second grid structures 233 as an example, do not represent first grid structure 230 in actual process
Number with second grid structure 233.First grid structure 230 and second gate can be selected as needed
The number of pole structure 233.
In conjunction with reference to Fig. 5 and Fig. 6, wherein, Fig. 5 is the schematic diagram being formed on the basis of Fig. 3, and Fig. 6 is
The schematic diagram being formed on the basis of Fig. 4, forms spacer material layer, described spacer material layer cover I region and
II region, and described spacer material layer is in first grid structure 230 surface, second grid structure 233 table
The thickness in face, the first fin 220 top surface and the second fin 221 top surface is more than described side wall material
The bed of material is in the thickness of the first fin 220 sidewall surfaces and the second fin 221 sidewall surfaces.
The acting as of described spacer material layer：For being subsequently formed only covering first grid structure 230 side wall
Side wall with second grid structure 233 side wall.
Describe for convenience, described spacer material layer is divided into two parts to illustrate, be i.e. described side wall material
The bed of material includes the first spacer material layer 240 and the second spacer material layer 241, described first spacer material layer
240 cover first grid structures 230, second grid structure 233, the of first grid structure 230 both sides
Second fin 221 top surface of one fin 220 top surface and second grid structure 233 both sides, institute
State the first fin 220 side wall and that the second spacer material layer 241 covers first grid structure 230 both sides
The second fin 221 side wall of two grid structure 233 both sides, and the thickness of described second spacer material layer 241
Degree is less than the thickness of the first spacer material layer 240.
The thickness of described first spacer material layer 240 is 10nm～30nm, such as 10nm, 20nm, 30nm；
The thickness of described second spacer material layer 241 is 5nm～25nm, such as 5nm, 15nm, 25nm.
Forming the method that described spacer material layer adopts is：From first grid structure 230 and second grid knot
Structure 233 top is passed through the first precursor gas for forming spacer material layer, then by before described first
Drive bromhidrosis bulk plasmon, described the first plasmarized precursor gas are adsorbed from top to bottom first
In first grid structure 230 surface, second grid structure 233 surface, first grid structure 230 both sides
The first fin 220 top surface and second grid structure 233 both sides the second fin 221 top surface,
Then the first fin 220 side wall in first grid structure 230 both sides and second grid structure 233 are adsorbed
The second fin 221 side wall of both sides, described the first plasmarized precursor gas are tied with first grid
Structure 230, second grid structure 233, the first fin 220 and the second fin 221 carry out chemical reaction and shape
Become described spacer material layer.So that the spacer material layer being formed is in the direction perpendicular to Semiconductor substrate 200
On there is the difference of thickness, that is, the thickness of described second spacer material layer 241 is less than the first spacer material layer
240 thickness.
In the present embodiment, using forming described spacer material layer in dry etching board.
Dry etching board top has the first air inlet being passed through the first precursor gas and is passed through etching gas
The second air inlet, there is in dry etching board plasma gasifying device, support platform, dry etching board bottom
There is steam vent, described first precursor gas are passed through chamber from described first air inlet, the first presoma
Gas is in plasma in the presence of plasma gasifying device within the chamber, and described fin field effect is brilliant
Body pipe is positioned over support platform surface, the first precursor gas and first grid structure 230, second grid knot
The by-product of the formation after structure 233, the first fin 220 and the second fin 221 chemical reaction is arranged from steam vent
Go out chamber.Described second air inlet is used for subsequently being passed through etching gas.
In a specific embodiment, the technological parameter of the described spacer material layer of formation is：Using gas
For N2, N2Flow be 100sccm～500sccm, plasmarized source power is
500KeV～1500KeV, bias voltage is 0V.
In another specific embodiment, the technological parameter forming described spacer material layer is：Using gas
Body is CH4, CH4Flow be 100sccm～500sccm, plasmarized source power is
500KeV～1500KeV, bias voltage is 0V.
Thickness due to described second spacer material layer 241 is less than the thickness of the first spacer material layer 240,
Make during spacer material layer is to form side wall described in subsequent etching, all exposing the first fin
The top surface of 220 top surface and side wall and the second fin 221 and the critical moment of side wall, first
Also there is the spacer material layer of segment thickness in grid structure 230 and second grid structure 233 side wall, will not
Expose first grid structure 230 side wall and second grid structure 233 side wall so that the side that is subsequently formed
Wall can be completely covered first grid structure 230 side wall and second grid structure 233 side wall.
In conjunction with reference to Fig. 7 and Fig. 8, wherein, Fig. 7 is the schematic diagram being formed on the basis of Fig. 5, and Fig. 8 is
The schematic diagram being formed on the basis of Fig. 6, etches described spacer material layer, forms side wall 250, described side wall
The 250 side walls that first grid structure 230 is completely covered and the side wall of second grid structure 233, and described side
Wall 250 is completely exposed the first fin 220 surface and the second grid knot of first grid structure 230 both sides
Second fin 221 surface of structure 233 both sides.
The described spacer material layer of described etching is to form the process of side wall 250 and to be previously formed spacer material layer
Technique realize all in etching machine bench.For Simplified flowsheet, in the present embodiment, using at same quarter
Form described spacer material layer in erosion board and described spacer material layer is performed etching.
Specifically, form described spacer material layer and the process of the described spacer material layer of etching can be entered simultaneously
Row is it is also possible to perform etching to described spacer material layer after forming described spacer material layer again.This reality
Apply in example, for convenience of description each step, select after forming described spacer material layer again to described
Spacer material layer performs etching.In another embodiment, for Simplified flowsheet, form described side wall material
The process of the bed of material and the described spacer material layer of etching is carried out simultaneously.
Etch described spacer material layer formed side wall 250 technique be anisotropic dry carving technology and each to
The technique that same sex dry carving technology combines, is done using isotropism after such as first adopting anisotropy dry carving technology
Carving technology, or first adopt isotropism dry carving technology after adopt anisotropy dry carving technology.
In the present embodiment, adopt isotropism dry carving technology after first adopting anisotropy dry carving technology to described
Spacer material layer performs etching, and realizes isotropic etching or anisotropy by the value adjusting bias power
Etching.
Specifically, first the parameter using anisotropy dry carving technology is：Using gas include CH3F、O2
And He, CH3The flow of F is 100sccm～250sccm, O2Flow be 50sccm～200sccm, He
Flow be 300sccm～500sccm, source radio-frequency power be 1000KeV～1800KeV, bias radio frequency work(
Rate is 200KeV～250KeV, and etching cavity pressure is 50mtorr～100mtorr；Then using each to together
The parameter of property dry carving technology is：Using gas include CH3F、CO2And Ar, CH3The flow of F is
50sccm～100sccm, CO2Flow be 10sccm～60sccm, the flow of Ar is
300sccm～800sccm, source radio-frequency power is 500KeV～1000KeV, and biasing radio-frequency power is
0KeV～50KeV, etching cavity pressure is 50mtorr～1000mtorr.
Described side wall 250 needs to completely reveal the first fin 220 side of first grid structure 230 both sides
Second fin 221 sidewall surfaces of wall surface and second grid structure 233 both sides, reason is, covers
The the second spacer material layer 241 building the first fin 220 side wall is located at grid structure compact district, and covers the
Second spacer material layer 241 of two fin 221 side wall is located at grid structure rarefaction, covers the first fin
The area of the second spacer material layer 241 of 220 side walls is less than the second side wall covering the second fin 221 side wall
The area of material layer 241 is so that the second spacer material layer 241 of etching the first fin 220 side wall produces
By-product be less than etching the second fin 221 side wall the second spacer material layer 241 produce by-product,
And because the first fin 220 compares first grid structure 230 and second grid structure with the second fin 221
233 are located at relatively low position, and the by-product of formation is relatively difficult to discharge, and the enrichment of by-product can reduce etching
Speed, so the etch rate covering the second spacer material layer 241 of the first fin 220 side wall is more than cover
Cover the etch rate of the second spacer material layer 241 of the second fin 221 side wall；In first grid structure 230
The critical moment that the first fin 220 side wall of both sides is completely exposed, the of second grid structure 233 both sides
Two fin 221 side wall there remains part the second spacer material layer 241, so that subsequently close in grid structure
First source region of Ji Qu formation and the first drain region are with the second source region and second being formed in grid structure rarefaction
Drain region highly consistent, need to remove remaining for the second fin 221 side wall the second spacer material layer 241,
Second fin 221 side wall is also fully exposed.
In addition, in the present embodiment, the thickness due to the second spacer material layer 241 is less than the first spacer material
The thickness of layer 240, so during etching forms described side wall 250, in the first fin 220 side
The critical moment that wall and the second fin 221 side wall are all completely exposed, described first spacer material layer 240 is also
Be covered with first grid structure 230, second grid structure 233, the first of first grid structure 230 both sides
Second fin 221 top surface of fin 220 top surface and second grid structure 233 both sides.Therefore
Need continue etch described spacer material layer, with expose first grid structure 230 top surface, second
Grid structure 233 top surface, the first fin 220 top surface and the second fin 221 top surface,
Form described side wall 250, and described side wall 250 is completely covered first grid structure 230 side wall and second gate
Pole structure 233 side wall.
It should be noted that first grid structure 230 compares the first fin 220 with second grid structure 233
It is located at higher position with the second fin 221, to formed after described first spacer material layer 240 etching
By-product is easily drained, therefore to the first spacer material layer 240 etching covering first grid structure 230
Speed and to cover second grid structure 233 the first spacer material layer 240 etch rate basically identical.
In sum, in embodiments of the invention, it is capable of described side wall 250 and the first grid is completely covered
The side wall of pole structure 230 and the side wall of second grid structure 233, and described side wall 250 is completely exposed
First fin 220 surface of one grid structure 230 both sides and the second of second grid structure 233 both sides
Fin 221 surface.
After forming described side wall 250, I region formed the first source region (not shown) and the first drain region (not
Diagram), described first source region is located at the side wall 250 in I region and the first of first grid structure 230 side
Fin 220 surface, described first drain region is located at the side wall 250 in I region and first grid structure 230 is another
First fin 220 surface of side；II region formed the second source region (not shown) and the second drain region (not
Diagram), described second source region is located at the side wall 250 in II region and the second of second grid structure 233 side
Fin 221 surface, described second drain region is located at the side wall 250 in II region and second grid structure 233 is another
Second fin 221 surface of side.
In the present embodiment, I region is used for the type of fin formula field effect transistor being formed and II region is used for shape
The type of the fin formula field effect transistor becoming is identical, therefore can form described first source region, the first leakage simultaneously
Area, the second source region and the second drain region.
In the present embodiment, form described first source region, the step in the first drain region, the second source region and the second drain region
Suddenly it is：The first fin 220 surface and second grid structure 233 in first grid structure 230 both sides
The second fin 221 surface epitaxial growth source-drain area material layer of both sides；Described source-drain area material layer is adulterated
Ion；After dopant ion, described source-drain area material layer is made annealing treatment.
Wherein, the selection of described source-drain area material layer is used for the fin field effect being formed with I region and II region
Answer transistor types related, specifically, when I region and II region are used for forming N-type fin field effect crystalline substance
During body pipe, the material of described source-drain area material layer is carborundum；When I region and II region are used for forming P
During type fin formula field effect transistor, the material of described source-drain area material layer is SiGe.
The selection of described ion is also used for the fin formula field effect transistor type being formed with I region and II region
Correlation, specifically, when I region and II region N-type to be formed fin formula field effect transistor, described from
Son is N-type ion, such as P or As；When I region and II region are used for forming p-type fin field effect crystal
Guan Shi, described ion is p-type ion, such as B or In.
Wherein, described make annealing treatment as spike annealing.
It should be noted that describing for convenience, in the present embodiment, the source-drain area material layer in I region is fixed
Justice is the first source-drain area material layer, and the source-drain area material layer in II region is defined as the second source-drain area material layer；
The described ion of doping in described first source-drain area material layer is defined as the first ion, by described second source
In the material layer of drain region, the described ion of doping is defined as the second ion.In the present embodiment, the first source-drain area material
The material of the bed of material and the second source-drain area material layer is identical, and described first ion and the second ion are identical.
In other embodiments, I region is used for the type of fin formula field effect transistor being formed and II region is used
Type in the fin formula field effect transistor being formed differs, at this time, it may be necessary to be initially formed described first source region
With the first drain region, form the second source region and the second drain region afterwards, or be initially formed described second source region and second
Drain region, forms the first source region and the first drain region afterwards.
During I region forms the first source region and the first drain region, because described side wall 250 is completely covered
First grid structure 230 side wall, in the first fin 220 surface extension of first grid structure 230 both sides
Grow and will not form the first source-drain area material in first grid structure 230 side wall during the first source-drain area material layer
Layer；During II region forms the second source region and the second drain region, because described side wall 250 covers completely
Lid second grid structure 233 side wall, outside the second fin 221 surface of second grid structure 233 both sides
The second source-drain area material will not be formed in second grid structure 233 side wall during epitaxial growth the second source-drain area material layer
The bed of material.So as to improve the performance of fin formula field effect transistor.
In sum, the present invention has advantages below：
The forming method of the fin formula field effect transistor that the present invention provides, the spacer material thickness degree of formation divides
Cloth has differences, and specifically, described spacer material layer is in first grid body structure surface, second grid structure
The thickness on surface, the first fin top surface and the second fin top surface exists more than described spacer material layer
First fin sidewall surfaces and the thickness of the second fin sidewall surfaces, therefore, etch described spacer material layer
After can form side wall, described side wall is completely covered the side wall of first grid structure and second grid structure
Side wall and first fin portion surface of first grid structure both sides and second grid structure both sides are completely exposed
Second fin portion surface.Because described side wall is completely covered first grid structure side wall, so in first grid
Will not be in first grid structure side wall during the first fin portion surface epitaxial growth source-drain area material layer of structure both sides
Form source-drain area material layer；Because described side wall is completely covered second grid structure side wall, in second grid
Will not be in second grid structure side wall during the second fin portion surface epitaxial growth source-drain area material layer of structure both sides
Form source-drain area material layer.So as to improve the performance of fin formula field effect transistor.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, all can make various changes or modifications, therefore the guarantor of the present invention
Shield scope should be defined by claim limited range.
Claims (17)
1. a kind of forming method of fin formula field effect transistor is it is characterised in that include：
There is provided Semiconductor substrate, Semiconductor substrate has grid structure compact district and grid structure rarefaction, grid
The semiconductor substrate surface of pole structure compact district has the first fin and the first grid across the first fin
Structure, the top surface of first grid structure covering part the first fin and side wall；Grid structure is sparse
The semiconductor substrate surface in area has the second fin and a second grid structure across the second fin, and second
The top surface of grid structure covering part second fin and side wall；
Form spacer material layer, described spacer material layer covers grid structure compact district and grid structure rarefaction,
Described spacer material layer includes the first spacer material layer and the second spacer material layer, the first spacer material layer
Cover first grid structure, second grid structure, the first fin top table of first grid structure both sides
Face and the second fin top surface of second grid structure both sides, the second spacer material layer covers the first grid
First fin side wall of pole structure both sides and the second fin side wall of second grid structure both sides, and described
The thickness of the second spacer material layer is less than the thickness of the first spacer material layer；
Etching spacer material layer, forms side wall, and described side wall is completely covered the side wall and the of first grid structure
The side wall of two grid structures, and described side wall is completely exposed the first fin table of first grid structure both sides
Face and the second fin portion surface of second grid structure both sides.
2. the forming method of fin formula field effect transistor according to claim 1 is it is characterised in that form
The step of described spacer material layer is：From first grid structure and second grid structural top be passed through for
Form the first precursor gas of spacer material layer；Plasmarized described first precursor gas；Institute
State the first plasmarized precursor gas to adsorb first in first grid body structure surface, second grid
Body structure surface, the first fin top surface of first grid structure both sides and second grid structure both sides
Second fin top surface, then adsorbs the first fin side wall and second in first grid structure both sides
Second fin side wall of grid structure both sides；Described plasmarized the first precursor gas and first
Grid structure, second grid structure, the first fin and the second fin carry out chemical reaction, are formed described
Spacer material layer.
3. the forming method of fin formula field effect transistor according to claim 1 is it is characterised in that doing
Carve in board and form described spacer material layer.
4. the forming method of fin formula field effect transistor according to claim 3 is it is characterised in that in institute
State in dry etching board, form described spacer material layer and the process of the described spacer material layer of etching is entered simultaneously
OK.
5. the forming method of fin formula field effect transistor according to claim 3 is it is characterised in that in institute
State in dry etching board, after forming described spacer material layer, described spacer material layer is performed etching.
6. the forming method of fin formula field effect transistor according to claim 3 is it is characterised in that form
The technological parameter of described spacer material layer is：Using gas be N2, N2Flow be
100sccm～500sccm, plasmarized source power is 500KeV～1500KeV, and bias voltage is
0V.
7. the forming method of fin formula field effect transistor according to claim 3 is it is characterised in that form
The technological parameter of described spacer material layer is：Using gas be CH4, CH4Flow be
100sccm～500sccm, plasmarized source power is 500KeV～1500KeV, and bias voltage is
0V.
8. the forming method of fin formula field effect transistor according to claim 1 is it is characterised in that described
The thickness of the first spacer material layer is 10nm～30nm.
9. the forming method of fin formula field effect transistor according to claim 1 is it is characterised in that described
The thickness of the second spacer material layer is 5nm～25nm.
10. the forming method of fin formula field effect transistor according to claim 1 is it is characterised in that adopt
The technique that isotropism dry carving technology and anisotropy dry carving technology combine etches described spacer material
Layer.
The forming method of 11. fin formula field effect transistors according to claim 10 is it is characterised in that adopt
After first anisotropy dry carving technology, isotropism dry carving technology etches described spacer material layer.
The forming method of 12. fin formula field effect transistors according to claim 11 is it is characterised in that elder generation is each
The parameter of anisotropy dry carving technology is：Using gas be CH3F、O2And He, CH3The flow of F
For 100sccm～250sccm, O2Flow be 50sccm～200sccm, the flow of He is
300sccm～500sccm, source radio-frequency power is 1000KeV～1800KeV, and biasing radio-frequency power is
200KeV～250KeV, etching cavity pressure is 50mtorr～100mtorr；Isotropism dry etching work afterwards
The parameter of skill is：Using gas include CH3F、CO2And Ar, CH3The flow of F is
50sccm～100sccm, CO2Flow be 10sccm～60sccm, the flow of Ar is
300sccm～800sccm, source radio-frequency power is 500KeV～1000KeV, and biasing radio-frequency power is
0KeV～50KeV, etching cavity pressure is 50mtorr～1000mtorr.
The forming method of 13. fin formula field effect transistors according to claim 1 is it is characterised in that also wrap
Include：After forming described side wall, form the first source region and the first drain region in grid structure compact district, described
First source region is located at the side wall of grid structure compact district and the first fin table of first grid structure side
Face, described first drain region is located at the of the side wall of grid structure compact district and first grid structure opposite side
One fin portion surface；Form the second source region and the second drain region, described second source region in grid structure rarefaction
Side wall positioned at grid structure rarefaction and the second fin portion surface of second grid structure side, described
Two drain regions are located at the side wall of grid structure rarefaction and the second fin table of second grid structure opposite side
Face.
The forming method of 14. fin formula field effect transistors according to claim 13 is it is characterised in that work as grid
Pole structure compact district is used for the type of fin formula field effect transistor being formed and grid structure rarefaction is used for
Formed fin formula field effect transistor type identical when, described first source region, the first drain region, second
Source region and the second drain region are formed simultaneously.
The forming method of 15. fin formula field effect transistors according to claim 14 is it is characterised in that form
Described first source region, the step in the first drain region, the second source region and the second drain region are：In first grid knot
First fin of structure both sides and the second fin portion surface epitaxial growth source-drain area of second grid structure both sides
Material layer；To described source-drain area material layer dopant ion；After dopant ion, to described source-drain area material
Layer is made annealing treatment.
The forming method of 16. fin formula field effect transistors according to claim 15 is it is characterised in that work as grid
When pole structure compact district and grid structure rarefaction are used for being formed N-type fin formula field effect transistor, described
The material of source-drain area material layer is carborundum；When grid structure compact district and grid structure rarefaction are used for
When forming p-type fin formula field effect transistor, the material of described source-drain area material layer is SiGe.
The forming method of 17. fin formula field effect transistors according to claim 15 is it is characterised in that work as grid
When pole structure compact district and grid structure rarefaction are used for being formed N-type fin formula field effect transistor, described
Ion is N-type ion；When grid structure compact district and grid structure rarefaction are used for forming p-type fin
During field-effect transistor, described ion is p-type ion.
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| US20070057325A1 (en) * | 2005-09-13 | 2007-03-15 | International Business Machines Corporation | Semiconductor FinFET structures with encapsulated gate electrodes and methods for forming such semiconductor FinFET structures |
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| CN104465386A (en) * | 2013-09-24 | 2015-03-25 | 中芯国际集成电路制造(北京)有限公司 | Method for forming semiconductor structure |
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