CN106384717B - The forming method of fin formula field effect transistor - Google Patents
The forming method of fin formula field effect transistor Download PDFInfo
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- CN106384717B CN106384717B CN201510456542.4A CN201510456542A CN106384717B CN 106384717 B CN106384717 B CN 106384717B CN 201510456542 A CN201510456542 A CN 201510456542A CN 106384717 B CN106384717 B CN 106384717B
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- 230000005669 field effect Effects 0.000 title claims abstract description 69
- 238000000034 method Methods 0.000 title claims abstract description 52
- 239000000463 material Substances 0.000 claims abstract description 232
- 125000006850 spacer group Chemical group 0.000 claims abstract description 113
- 239000004065 semiconductor Substances 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 238000005530 etching Methods 0.000 claims description 36
- 238000005516 engineering process Methods 0.000 claims description 26
- 150000002500 ions Chemical class 0.000 claims description 24
- 239000002243 precursor Substances 0.000 claims description 14
- 238000001312 dry etching Methods 0.000 claims description 11
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical group [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims 1
- 229910003978 SiClx Inorganic materials 0.000 claims 1
- 229910052799 carbon Inorganic materials 0.000 claims 1
- 238000002955 isolation Methods 0.000 description 14
- 239000006227 byproduct Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 239000007772 electrode material Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical group [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of forming method of fin formula field effect transistor, comprising: provide the semiconductor substrate with gate structure compact district and gate structure rarefaction, the semiconductor substrate surface of gate structure compact district has the first grid structure across the first fin；The semiconductor substrate surface of gate structure rarefaction has the second grid structure across the second fin；Form spacer material layer, spacer material layer includes the first spacer material layer and second side walling bed of material, first spacer material layer covers first grid structure and second grid structure and the first fin top surface and the second fin top surface, second side walling bed of material covers the first fin side wall and the second fin side wall, second side walling bed of material are thinner than the first spacer material layer；Spacer material layer is etched, side wall is formed, the side wall is completely covered the side wall of first grid structure and second grid structure and the first fin and the second fin is completely exposed.The forming method of the fin formula field effect transistor improves the performance of fin formula field effect transistor.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of forming methods of fin formula field effect transistor.
Background technique
MOS transistor is one of most important element in modern integrated circuits.The basic structure of MOS transistor includes: half
Conductor substrate；Positioned at the gate structure of semiconductor substrate surface, source region and it is located in the semiconductor substrate of gate structure side
Drain region in the semiconductor substrate of the gate structure other side.For MOS transistor by applying voltage in grid, adjusting passes through gate structure
The electric current of bottom channel generates switching signal.
With the development of semiconductor technology, the MOS transistor of traditional plane formula dies down to the control ability of channel current,
Cause serious leakage current.Fin formula field effect transistor (Fin FET) is a kind of emerging multi-gate device, it generally comprises protrusion
In the fin of semiconductor substrate surface, the top surface of fin and the gate structure of side wall described in covering part are located at grid knot
Source region in the fin of structure side and the drain region in the fin of the gate structure other side.
The method for forming fin formula field effect transistor includes: offer semiconductor substrate, and the semiconductor substrate surface has
The fin and gate structure across the fin of protrusion, the top surface of fin described in the gate structure covering part and side
Wall；Side wall is formed in gate structure two sides side wall；It is carried out using side wall and gate structure as fin of the exposure mask to gate structure two sides
Ion implanting forms source region and the drain region of heavy doping.
As characteristic size further reduces, the prior art formed fin formula field effect transistor Performance And Reliability compared with
Difference.
Summary of the invention
Problems solved by the invention is to provide a kind of forming method of fin formula field effect transistor, and it is brilliant to improve fin field effect
The performance of body pipe.
To solve the above problems, the present invention provides a kind of forming method of fin formula field effect transistor, comprising: offer is partly led
Body substrate, semiconductor substrate have gate structure compact district and gate structure rarefaction, and the semiconductor of gate structure compact district serves as a contrast
Bottom surface has the first fin and the first grid structure across the first fin, first grid structure the first fin of covering part
Top surface and side wall；The semiconductor substrate surface of gate structure rarefaction has the second fin and across the second of the second fin
Gate structure, the top surface and side wall of second grid structure the second fin of covering part；Form spacer material layer, the side wall
Material layer covers gate structure compact district and gate structure rarefaction, and the spacer material layer includes the first spacer material layer and the
Two spacer material layers, the first spacer material layer cover first grid structure, second grid structure, first grid structure two sides the
Second fin top surface of one fin top surface and second grid structure two sides, second side walling bed of material cover first grid
First fin side wall of structure two sides and the second fin side wall of second grid structure two sides, and second side walling bed of material
Thickness of the thickness less than the first spacer material layer；Spacer material layer is etched, side wall is formed, first grid is completely covered in the side wall
The side wall of structure and the side wall of second grid structure, and the first fin table of first grid structure two sides is completely exposed in the side wall
Second fin portion surface in face and second grid structure two sides.
Optionally, the step of forming the spacer material layer are as follows: logical from first grid structure and second grid structural top
Enter to be used to form the first precursor gas of spacer material layer；Plasmarized first precursor gas；The plasma
First precursor gas of body is adsorbed on first grid body structure surface, second grid body structure surface, first grid structure first
First fin top surface of two sides and the second fin top surface of second grid structure two sides, are then adsorbed on first grid
First fin side wall of structure two sides and the second fin side wall of second grid structure two sides；Before described plasmarized first
It drives body gas to be chemically reacted with first grid structure, second grid structure, the first fin and the second fin, forms the side
The walling bed of material.
Optionally, the spacer material layer is formed in dry etching board.
Optionally, it in the dry etching board, forms the spacer material layer and etches the process of the spacer material layer
It carries out simultaneously.
Optionally, it in the dry etching board, forms the spacer material layer and the spacer material layer is carved later
Erosion.
Optionally, the technological parameter of the spacer material layer is formed are as follows: the gas used is N2, N2Flow be 100sccm
~500sccm, plasmarized source power are 500KeV~1500KeV, bias voltage 0V.
Optionally, the technological parameter of the spacer material layer is formed are as follows: the gas used is CH4, CH4Flow be
100sccm~500sccm, plasmarized source power are 500KeV~1500KeV, bias voltage 0V.
Optionally, the first spacer material layer with a thickness of 10nm~30nm.
Optionally, second side walling bed of material with a thickness of 5nm~25nm.
Optionally, the side wall is etched using the technique that isotropism dry carving technology and anisotropy dry carving technology combine
Material layer.
Optionally, the spacer material layer is etched using isotropism dry carving technology after first anisotropy dry carving technology.
Optionally, the parameter of first anisotropy dry carving technology are as follows: the gas used is CH3F、O2And He, CH3The flow of F is
100sccm~250sccm, O2Flow be 50sccm~200sccm, the flow of He is 300sccm~500sccm, source radio frequency
Power be 1000KeV~1800KeV, biasing radio-frequency power be 200KeV~250KeV, etching cavity pressure for 50mtorr~
100mtorr；The parameter of isotropism dry carving technology afterwards are as follows: the gas of use includes CH3F、CO2And Ar, CH3The flow of F is
50sccm~100sccm, CO2Flow be 10sccm~60sccm, the flow of Ar is 300sccm~800sccm, source radio frequency function
Rate be 500KeV~1000KeV, biasing radio-frequency power be 0KeV~50KeV, etching cavity pressure for 50mtorr~
1000mtorr。
Optionally, further includes: after forming the side wall, the first source region and the first drain region are formed in gate structure compact district,
First source region is located at the side wall of gate structure compact district and the first fin portion surface of first grid structure side, and described first
Drain region is located at the side wall of gate structure compact district and the first fin portion surface of the first grid structure other side；It is sparse in gate structure
Area forms the second source region and the second drain region, second source region are located at the side wall and second grid structure one of gate structure rarefaction
Second fin portion surface of side, second drain region be located at gate structure rarefaction side wall and the second grid structure other side
Two fin portion surfaces.
Optionally, the type and gate structure for the fin formula field effect transistor being used to form when gate structure compact district are sparse
When the type for the fin formula field effect transistor that area is used to form is identical, first source region, the first drain region, the second source region and second
Drain region is formed simultaneously.
Optionally, the step of forming first source region, the first drain region, the second source region and the second drain region are as follows: in the first grid
First fin of pole structure two sides and the second fin portion surface epitaxial growth source-drain area material layer of second grid structure two sides；It is right
The source-drain area material layer Doped ions；After Doped ions, the source-drain area material layer is made annealing treatment.
Optionally, when gate structure compact district and gate structure rarefaction are used to form N-type fin formula field effect transistor,
The material of the source-drain area material layer is silicon carbide；When gate structure compact district and gate structure rarefaction are used to form p-type fin
When formula field effect transistor, the material of the source-drain area material layer is SiGe.
Optionally, when gate structure compact district and gate structure rarefaction are used to form N-type fin formula field effect transistor,
The ion is N-type ion；When gate structure compact district and gate structure rarefaction are used to form p-type fin formula field effect transistor
When, the ion is P-type ion.
Compared with prior art, technical solution of the present invention has the advantage that
The forming method of fin formula field effect transistor provided by the invention, it is poor that the spacer material layer thickness profile of formation exists
It is different, specifically, the spacer material layer is in first grid body structure surface, second grid body structure surface, the first fin top surface
It is greater than the spacer material layer in the first fin sidewall surfaces and the second fin side wall table with the thickness of the second fin top surface
Therefore the thickness in face is capable of forming side wall after etching the spacer material layer, first grid structure is completely covered in the side wall
Side wall and the side wall of second grid structure and the first fin portion surface and second grid that first grid structure two sides are completely exposed
Second fin portion surface of structure two sides.Since first grid structure side wall is completely covered in the side wall, so in first grid knot
When the first fin portion surface epitaxial growth source-drain area material layer of structure two sides source-drain area material will not be formed in first grid structure side wall
The bed of material；Since second grid structure side wall is completely covered in the side wall, outside the second fin portion surface of second grid structure two sides
When prolonging growth source-drain area material layer source-drain area material layer will not be formed in second grid structure side wall.So as to improve fin
The performance of field effect transistor.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of fin formula field effect transistor in one embodiment of the invention.
Fig. 2 to Fig. 8 is the structural schematic diagram of the forming process of fin formula field effect transistor in another embodiment of the present invention.
Specific embodiment
When the fin formula field effect transistor that the prior art is formed is further reduced with characteristic size, fin field effect crystal
The Performance And Reliability of pipe is poor.
One embodiment of the invention provides a kind of forming method of fin formula field effect transistor, with reference to Fig. 1, comprising: provides
Semiconductor substrate 100, the semiconductor substrate 100 have gate structure compact district (region I) and the gate structure rarefaction (area II
Domain), 100 surface of semiconductor substrate of gate structure compact district has the first fin 120 and the first grid across the first fin 120
Pole structure 130, the top surface and side wall of 130 the first fin of covering part 120 of first grid structure；Gate structure rarefaction
100 surface of semiconductor substrate has the second fin 121 and the second grid structure 131 across the second fin 121, second grid knot
The top surface and side wall of 131 the second fin of covering part 121 of structure；Spacer material layer, the side wall are formed using depositing operation
Material layer covers first area and second area；Spacer material layer is etched, side wall 140 is formed, the side wall 140 is located at the first grid
131 sidewall surfaces of 130 sidewall surfaces of pole structure and second grid structure, and first grid structure 130 is completely exposed in the side wall
121 surface of the second fin of 131 two sides of 120 surface of the first fin and second grid structure of two sides.
The study found that the reason that the fin formula field effect transistor that the above method is formed still remains performance difference is:
The spacer material layer is used to form covering first grid structure side wall and second grid structure side wall, and completely sudden and violent
Reveal the side wall of the first fin portion surface of first grid structure two sides and the second fin portion surface of second grid structure two sides.Exist
After forming spacer material layer, need the spacer material layer and second grid of the first fin portion surface of first grid structure two sides
The spacer material layer of second fin portion surface of structure two sides removes.It generallys use etching technics and removes above-mentioned part spacer material layer
During, the etch rate of the etching technics is influenced by etch by-products are how many, when more by-product is centered around
Spacer material layer surface to be etched and when not excluding, etch rate can decline.
Specifically, in the above embodiment of the invention, due in identical volume, the of first grid structure two sides
The area of one fin is less than the area of the second fin of second grid structure two sides, so in identical volume, covering first
The area of the spacer material layer of fin side wall is less than the area of the spacer material layer of the second fin side wall of covering, etching covering first
The by-product that the spacer material layer of fin side wall generates is less than the pair that the spacer material layer of etching the second fin side wall of covering generates
Product, and the more difficult discharge of by-product after the spacer material layer etching of the first fin side wall and the second fin side wall is covered, so
The rate of the spacer material layer of etching the first fin of covering is greater than the rate of the spacer material layer of etching the second fin of covering.
Therefore, the critical moment that the first fin portion surface in first grid structure two sides is completely exposed, second grid structure
There is also part spacer material layers for second fin portion surface of two sides, in order to enable the second fin portion surface of second grid structure two sides
It is fully exposed, so that subsequent the first source region formed in the region I and the first drain region and the second source formed in the region II
Area is consistent with the height in the second drain region, needs to increase the etching degree of the opposite side walling bed of material, due to the etching of the opposite side walling bed of material
The thickness for the spacer material layer that degree is increased and formed using depositing operation is more uniform, so in first grid structure and the
The side wall that two gate structure sidewall surfaces are formed can expose part first grid structure side wall and second grid structure side
Wall (position 150 marked with reference to dotted line in Fig. 1).It is subsequent to form the first source region and the first leakage in the region I with epitaxial growth technology
It, also can be in the position epitaxial grown material layer of first grid structure side wall exposure during area；It is subsequent to use epitaxial growth technology
It, also can be in the position extension life of second grid structure side wall exposure during the region II forms the second source region and the second drain region
Long material layer.To reduce the performance of fin formula field effect transistor.
On this basis, another embodiment of the present invention provides a kind of forming methods of fin formula field effect transistor, comprising:
Semiconductor substrate is provided, semiconductor substrate has gate structure compact district and gate structure rarefaction, gate structure compact district
Semiconductor substrate surface has the first fin and the first grid structure across the first fin, first grid structure covering part the
The top surface and side wall of one fin；The semiconductor substrate surface of gate structure rarefaction has the second fin and across the second fin
The second grid structure in portion, the top surface and side wall of second grid structure the second fin of covering part；Spacer material layer is formed,
The spacer material layer covering first area and second area, the spacer material layer include the first spacer material layer and second side
The walling bed of material, the first spacer material layer cover first grid structure, second grid structure, first grid structure two sides the first fin
Second fin top surface of portion's top surface and second grid structure two sides, second side walling bed of material cover first grid structure
First fin side wall of two sides and the second fin side wall of second grid structure two sides, and the thickness of second side walling bed of material
Less than the thickness of the first spacer material layer；Spacer material layer is etched, side wall is formed, first grid structure is completely covered in the side wall
Side wall and second grid structure side wall, and the side wall be completely exposed the first fin portion surface of first grid structure two sides with
And the second fin portion surface of second grid structure two sides.
The side wall of first grid structure and the side wall of second grid structure, and the side wall are completely covered due to the side wall
The first fin portion surface of first grid structure two sides and the second fin portion surface of second grid structure two sides is completely exposed.So that
It is subsequent to use epitaxial growth technology during the region I forms the first source region and the first drain region, it avoids in first grid structure
Side wall epitaxial grown material layer；So that subsequent form the process of the second source region and the second drain region in the region II with epitaxial growth technology
In, it avoids in second grid structure side wall epitaxial grown material layer.So as to improve the performance of fin formula field effect transistor.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
In conjunction with referring to figs. 2 to Fig. 4, Fig. 3 is along the first fin of the region I extending direction (A-A1 axis) and the area II in Fig. 2
The sectional view of domain the second fin extending direction (A2-A3 axis)；Fig. 4 is the sectional view along B-B1 axis in Fig. 2, the B-B1
Axis is parallel to first grid structure extending direction and second grid structure extending direction, and the B-B1 axis passes through the first grid
First fin of pole structure side and the second fin of second grid structure side.Semiconductor substrate 200, semiconductor substrate are provided
200 have gate structure compact district (region I) and gate structure rarefaction (region II), 200 surface of semiconductor substrate in the region I
With the first fin 220 and across the first grid structure 230 of the first fin 220,230 covering part of first grid structure
The top surface and side wall of first fin 220；200 surface of semiconductor substrate in the region II has the second fin 221 and across the
The second grid structure 233 of two fins 221, the top surface of 233 second fin of covering part 221 of second grid structure and
Side wall.
The semiconductor substrate 200 provides technique platform to be subsequently formed fin formula field effect transistor.
The semiconductor substrate 200 can be monocrystalline silicon, polysilicon or amorphous silicon；Semiconductor substrate 200 be also possible to silicon,
The semiconductor materials such as germanium, SiGe, GaAs；The semiconductor substrate 200 can be body material, be also possible to composite construction,
Such as silicon-on-insulator；The semiconductor substrate 200 can also be other semiconductor materials, no longer illustrate one by one here.This implementation
In example, the material of the semiconductor substrate 200 is silicon.
The semiconductor substrate 200 includes the region I and the region II, and the region I is for being subsequently formed the intensive fin of gate structure
Formula field effect transistor, the region II is for being subsequently formed the sparse fin formula field effect transistor of gate structure.
The effect of first fin 220 are as follows: provide carrier to be subsequently formed first grid structure；Second fin
221 effect are as follows: provide carrier to be subsequently formed second grid structure.
In the present embodiment, the step of forming first fin 220 and the second fin 221 are as follows: in 200 table of semiconductor substrate
Face forms patterned mask layer, and the patterned mask layer defines the position of the first fin 220 and the second fin 221；With
The patterned mask layer is the semiconductor substrate 200 of mask etching segment thickness, forms the first fin 220 in the region I,
The region II forms the second fin 221.
Since first fin 220 and the second fin 221 are formed by etch semiconductor substrates 200, so first
Fin 220 is identical with the material of semiconductor substrate 200 with the material of the second fin 221, first fin 220 and the second fin
221 material is silicon.In other embodiments, the material of first fin 220 and the second fin 221 can be with semiconductor
The material of substrate 200 is not identical.
In the present embodiment, with the region I tool there are three the first fin 220 as an example, there are three the second fins with the region II tool
Portion 221 is not as an example, represent the number of the first fin 220 and the second fin 221 in actual process.It can according to need choosing
Select the specific number of the first fin 220 and the second fin 221.
The effect of the isolation structure 210 is adjacent the first fin 220 of electric isolation, and electric isolation it is adjacent second
Fin 221.
The material of the isolation structure 210 includes silica or silicon oxynitride.In the present embodiment, the material of isolation structure 210
Material is silica.
The step of forming isolation structure 210 are as follows: the isolation structure material layer in the formation covering region I and the region II is (not
Diagram), and the whole surface of the isolation structure material layer is higher than the top surface of the first fin 220 and the second fin 221；It adopts
With flatening process, such as chemical mechanical grinding, the isolation structure material layer is planarized, with the first fin 220 and the second fin
221 top surface is stop-layer；It is etched back to portions of isolation structure material layer, the semiconductor substrate 200 in the region I and the region II
Surface forms isolation structure 210, and the surface of the isolation structure 210 is lower than the top table of the first fin 220 and the second fin 221
Face.
The first grid structure 230 includes the first gate dielectric layer 231 and covering first grid Jie across the first fin 220
The first gate electrode layer 232 of matter layer 231.Wherein, the first gate dielectric layer 231 is located at 210 surface of isolation structure in the region I, covering
The top surface and side wall of the first fin of part 220；The second grid structure 233 includes across the second of the second fin 221
Second gate electrode layer 235 of the second gate dielectric layer 234 of gate dielectric layer 234 and covering.Wherein, the second gate dielectric layer 234 is located at II
210 surface of isolation structure in region, the second fin of covering part 221 top surface and side wall.
In the present embodiment, the material of first gate dielectric layer 231 and the second gate dielectric layer 234 is silica, described the
The material of one gate electrode layer 232 and the second gate electrode layer 235 is polysilicon.In other embodiments, it may also is that described first
The material of gate dielectric layer 231 and the second gate dielectric layer 234 is high K dielectric material, the first gate electrode layer 232 and second gate electricity
The material of pole layer 235 is metal.
The method for forming first grid structure 230 and second grid structure 233 are as follows: the covering area I is formed using depositing operation
The layer of gate electrode material (not shown) of the gate dielectric material layer (not shown) and cover grid layer of dielectric material in domain and the region II；Institute
It states gate material layer surface to be formed patterned mask layer (not shown), the patterned mask layer defines first grid knot
The position of structure 230 and second grid structure 233；Using the patterned mask layer as exposure mask, the gate dielectric material layer is etched
First grid is formed until exposing the top surface of the first fin 220 and the second fin 221 with the layer of gate electrode material
Structure 230 and second grid structure 233.
In the present embodiment, with the region I tool there are two first grid structure 230 as an example, there are two the with the region II tool
Two gate structures 233 are not as an example, represent of first grid structure 230 and second grid structure 233 in actual process
Number.It can according to need the number of selection first grid structure 230 and second grid structure 233.
In conjunction with reference Fig. 5 and Fig. 6, wherein Fig. 5 is the schematic diagram formed on the basis of Fig. 3, and Fig. 6 is shape on the basis of Fig. 4
At schematic diagram, form spacer material layer, the spacer material layer covering region I and the region II, and the spacer material layer exists
230 surface of first grid structure, 221 top of 233 surface of second grid structure, 220 top surface of the first fin and the second fin
The thickness on surface is greater than the spacer material layer in the thickness of 221 sidewall surfaces of 220 sidewall surfaces of the first fin and the second fin.
The effect of the spacer material layer are as follows: only cover 230 side wall of first grid structure and second gate for being subsequently formed
The side wall of 233 side wall of pole structure.
It is illustrated for the convenience of description, the spacer material layer is divided into two parts, i.e., the described spacer material layer includes
First spacer material layer 240 and second side walling bed of material 241, the first spacer material layer 240 cover first grid structure
230, second grid structure 233,220 top surface of the first fin of 230 two sides of first grid structure and second grid structure 233
221 top surface of the second fin of two sides, second side walling bed of material 241 cover the first of 230 two sides of first grid structure
221 side wall of the second fin of 233 two sides of 220 side wall of fin and second grid structure, and the thickness of second side walling bed of material 241
Spend the thickness less than the first spacer material layer 240.
The first spacer material layer 240 with a thickness of 10nm~30nm, such as 10nm, 20nm, 30nm；Second side wall
Material layer 241 with a thickness of 5nm~25nm, such as 5nm, 15nm, 25nm.
Form the method that the spacer material layer uses are as follows: from 233 top of first grid structure 230 and second grid structure
It is passed through the first precursor gas for being used to form spacer material layer, then that first precursor gas is plasmarized, institute
It states the first plasmarized precursor gas and is adsorbed on 230 surface of first grid structure, second grid knot first from top to bottom
233 surface of structure, 230 two sides of first grid structure 233 two sides of 220 top surface of the first fin and second grid structure second
Then 221 top surface of fin is adsorbed on 220 side wall of the first fin and second grid structure of 230 two sides of first grid structure
221 side wall of the second fin of 233 two sides, the first plasmarized precursor gas and first grid structure 230, second
Gate structure 233, the first fin 220 and the second fin 221 are chemically reacted and form the spacer material layer.So that being formed
Spacer material layer there are the difference of thickness, i.e., described second side walling bed of materials in the direction perpendicular to semiconductor substrate 200
Thickness of 241 thickness less than the first spacer material layer 240.
In the present embodiment, using forming the spacer material layer in dry etching board.
There is the first air inlet for being passed through the first precursor gas at the top of dry etching board and be passed through the second of etching gas
Air inlet, has plasmarized device, support platform in dry etching board, and dry etching machine bottom has a gas vent, and described first
Precursor gas is passed through chamber from first air inlet, and the first precursor gas is in chamber in the work of plasmarized device
It is in plasma under, the fin formula field effect transistor is placed in support platform surface, the first precursor gas and first
The by-product of formation after gate structure 230, second grid structure 233, the first fin 220 and the chemical reaction of the second fin 221
Chamber is discharged from gas vent.Second air inlet is passed through etching gas for subsequent.
In a specific embodiment, the technological parameter of the spacer material layer is formed are as follows: the gas used is N2, N2's
Flow is 100sccm~500sccm, and plasmarized source power is 500KeV~1500KeV, bias voltage 0V.
In another specific embodiment, the technological parameter of the spacer material layer is formed are as follows: the gas used is CH4,
CH4Flow be 100sccm~500sccm, plasmarized source power be 500KeV~1500KeV, bias voltage 0V.
Due to second side walling bed of material 241 thickness less than the first spacer material layer 240 thickness so that subsequent quarter
During losing the spacer material layer to form side wall, all expose top surface and the side wall of the first fin 220 with
And second fin 221 top surface and side wall critical moment, 233 side wall of first grid structure 230 and second grid structure
There is also the spacer material layers of segment thickness, will not expose 233 side of 230 side wall of first grid structure and second grid structure
Wall allows the side wall being subsequently formed that 233 side wall of 230 side wall of first grid structure and second grid structure is completely covered.
In conjunction with reference Fig. 7 and Fig. 8, wherein Fig. 7 is the schematic diagram formed on the basis of Fig. 5, and Fig. 8 is shape on the basis of Fig. 6
At schematic diagram, etch the spacer material layer, form side wall 250, first grid structure 230 is completely covered in the side wall 250
Side wall and second grid structure 233 side wall, and the first of 230 two sides of first grid structure is completely exposed in the side wall 250
221 surface of the second fin of 233 two sides of 220 surface of fin and second grid structure.
The etching spacer material layer is equal with the process for forming side wall 250 and the technique for being previously formed spacer material layer
It is realized in etching machine bench.In order to simplify technique, in the present embodiment, using forming the side wall material in the same etching machine bench
The bed of material simultaneously performs etching the spacer material layer.
Specifically, forming the process of the spacer material layer and the etching spacer material layer can carry out simultaneously, it can also
To be performed etching again to the spacer material layer after forming the spacer material layer.In the present embodiment, for ease of description
Each step, selection again perform etching the spacer material layer after forming the spacer material layer.In another implementation
In example, in order to simplify technique, forms the spacer material layer and etch the process of the spacer material layer while carrying out.
Etching the spacer material layer and forming the technique of side wall 250 is anisotropic dry carving technology and isotropism dry etching
The technique that technique combines, as first using using isotropism dry carving technology after anisotropy dry carving technology, or first using it is each to
Anisotropy dry carving technology is used after same sex dry carving technology.
In the present embodiment, first use isotropism dry carving technology to the spacer material using after anisotropy dry carving technology
Layer performs etching, and the value by adjusting bias power realizes isotropic etching or anisotropic etching.
Specifically, first using the parameter of anisotropy dry carving technology are as follows: the gas of use includes CH3F、O2And He, CH3F's
Flow is 100sccm~250sccm, O2Flow be 50sccm~200sccm, the flow of He is 300sccm~500sccm,
Source radio-frequency power is 1000KeV~1800KeV, and biasing radio-frequency power is 200KeV~250KeV, and etching cavity pressure is
50mtorr~100mtorr；Then the parameter of isotropism dry carving technology is used are as follows: the gas of use includes CH3F、CO2And Ar,
CH3The flow of F is 50sccm~100sccm, CO2Flow be 10sccm~60sccm, the flow of Ar be 300sccm~
800sccm, source radio-frequency power are 500KeV~1000KeV, and biasing radio-frequency power is 0KeV~50KeV, and etching cavity pressure is
50mtorr~1000mtorr.
The side wall 250 need to completely reveal 230 two sides of first grid structure 220 sidewall surfaces of the first fin and
221 sidewall surfaces of the second fin of 233 two sides of second grid structure, the reason is that, second side of covering 220 side wall of the first fin
The walling bed of material 241 is located at gate structure compact district, and second side walling bed of material 241 for covering 221 side wall of the second fin is located at grid
Pole structure rarefaction, the area for covering second side walling bed of material 241 of 220 side wall of the first fin are less than the second fin 221 of covering
The area of second side walling bed of material 241 of side wall, so that second side walling bed of material 241 of etching 220 side wall of the first fin generates
By-product be less than the by-product that second side walling bed of material 241 of etching 221 side wall of the second fin generates, and due to the first fin
220 compare first grid structure 230 with the second fin 221 and second grid structure 233 is located at lower position, the by-product of formation
Object is relatively difficult to be discharged, and the enrichment of by-product can reduce etch rate, so second side walling of covering 220 side wall of the first fin
The etch rate of the bed of material 241 is greater than the etch rate of second side walling bed of material 241 of covering 221 side wall of the second fin；First
The critical moment that 220 side wall of the first fin of 230 two sides of gate structure is completely exposed, the second of 233 two sides of second grid structure
221 side wall of fin there remains part second side walling bed of material 241, in order to enable subsequent first formed in gate structure compact district
Source region is consistent with the height in the second drain region with the second source region formed in gate structure rarefaction with the first drain region, needs second
The remaining second side walling bed of material 241 of 221 side wall of fin removes, and 221 side wall of the second fin is also fully exposed.
In addition, in the present embodiment, due to second side walling bed of material 241 thickness less than the first spacer material layer 240 thickness
Degree, so during etching forms side wall 250, it is complete in 220 side wall of the first fin and 221 side wall of the second fin
Exposed critical moment, the first spacer material layer 240 be also covered with first grid structure 230, second grid structure 233,
Second fin 221 of 233 two sides of 220 top surface of the first fin and second grid structure of 230 two sides of first grid structure
Top surface.Therefore need to continue to etch the spacer material layer, to expose 230 top surface of first grid structure, second gate
221 top surface of 233 top surface of pole structure, 220 top surface of the first fin and the second fin, forms the side wall 250,
And 233 side wall of 230 side wall of first grid structure and second grid structure is completely covered in the side wall 250.
It should be noted that first grid structure 230 compares the first fin 220 and the second fin with second grid structure 233
Portion 221 is located at higher position, is easily drained to the by-product that is formed after the first spacer material layer 240 etching, therefore to covering
The rate that first spacer material layer 240 of lid first grid structure 230 etches and the first side to covering second grid structure 233
The etch rate of the walling bed of material 240 is almost the same.
In conclusion can be realized the side wall 250 in the embodiment of the present invention and first grid structure 230 be completely covered
Side wall and second grid structure 233 side wall, and the first of 230 two sides of first grid structure is completely exposed in the side wall 250
221 surface of the second fin of 233 two sides of 220 surface of fin and second grid structure.
After forming the side wall 250, the first source region (not shown) and the first drain region (not shown) is formed in the region I, it is described
First source region is located at 220 surface of the first fin of 230 side of side wall 250 and first grid structure in the region I, first drain region
Positioned at 220 surface of the first fin of 230 other side of side wall 250 and first grid structure in the region I；The second source is formed in the region II
Area (not shown) and the second drain region (not shown), second source region are located at the side wall 250 and second grid structure 233 in the region II
221 surface of the second fin of side, second drain region are located at 233 other side of side wall 250 and second grid structure in the region II
221 surface of the second fin.
In the present embodiment, fin that the type for the fin formula field effect transistor that the region I is used to form and the region II are used to form
The type of formula field effect transistor is identical, therefore can be formed simultaneously first source region, the first drain region, the second source region and the second leakage
Area.
In the present embodiment, the step of forming first source region, the first drain region, the second source region and the second drain region are as follows: the
Outside 221 surface of the second fin of 233 two sides of 220 surface of the first fin and second grid structure of one gate structure, 230 two sides
Prolong growth source-drain area material layer；To the source-drain area material layer Doped ions；After Doped ions, to the source-drain area material layer into
Row annealing.
Wherein, the fin formula field effect transistor that the selection of the source-drain area material layer is used to form with the region I and the region II
Type is related, specifically, when the region I and the region II are used to form N-type fin formula field effect transistor, the source-drain area material layer
Material be silicon carbide；When the region I and the region II are used to form p-type fin formula field effect transistor, the source-drain area material layer
Material be SiGe.
The selection of the ion is also related to the fin formula field effect transistor type that the region II is used to form with the region I, tool
Body, when the region I and the region II N-type fin formula field effect transistor to be formed, the ion is N-type ion, such as P or As；Work as I
When region and the region II are used to form p-type fin formula field effect transistor, the ion is P-type ion, such as B or In.
Wherein, the annealing is spike annealing.
It should be noted that for the convenience of description, the source-drain area material layer in the region I is defined as first in the present embodiment
The source-drain area material layer in the region II is defined as the second source-drain area material layer by source-drain area material layer；By the first source-drain area material
The ion adulterated in the bed of material is defined as the first ion, and the ion adulterated in the second source-drain area material layer is defined
For the second ion.In the present embodiment, the first source-drain area material layer is identical with the material of the second source-drain area material layer, described first from
Son is identical with the second ion.
In other embodiments, the type for the fin formula field effect transistor that the region I is used to form and the region II are used to form
Fin formula field effect transistor type it is not identical, at this time, it may be necessary to be initially formed first source region and the first drain region, form afterwards
Two source regions and the second drain region, or it is initially formed second source region and the second drain region, it is rear to form the first source region and the first drain region.
During the region I forms the first source region and the first drain region, since first grid is completely covered in the side wall 250
230 side wall of structure, in 220 surface epitaxial growth the first source-drain area material layer of the first fin of 230 two sides of first grid structure
The first source-drain area material layer will not be formed in 230 side wall of first grid structure；The second source region and the second drain region are formed in the region II
During, since 233 side wall of second grid structure is completely covered in the side wall 250, the of 233 two sides of second grid structure
When two fins, 221 surface epitaxial growth the second source-drain area material layer the second source and drain will not be formed in 233 side wall of second grid structure
Area's material layer.So as to improve the performance of fin formula field effect transistor.
In conclusion the invention has the following advantages that
The forming method of fin formula field effect transistor provided by the invention, it is poor that the spacer material layer thickness profile of formation exists
It is different, specifically, the spacer material layer is in first grid body structure surface, second grid body structure surface, the first fin top surface
It is greater than the spacer material layer in the first fin sidewall surfaces and the second fin side wall table with the thickness of the second fin top surface
Therefore the thickness in face is capable of forming side wall after etching the spacer material layer, first grid structure is completely covered in the side wall
Side wall and the side wall of second grid structure and the first fin portion surface and second grid that first grid structure two sides are completely exposed
Second fin portion surface of structure two sides.Since first grid structure side wall is completely covered in the side wall, so in first grid knot
When the first fin portion surface epitaxial growth source-drain area material layer of structure two sides source-drain area material will not be formed in first grid structure side wall
The bed of material；Since second grid structure side wall is completely covered in the side wall, outside the second fin portion surface of second grid structure two sides
When prolonging growth source-drain area material layer source-drain area material layer will not be formed in second grid structure side wall.So as to improve fin
The performance of field effect transistor.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (17)
1. a kind of forming method of fin formula field effect transistor characterized by comprising
Semiconductor substrate is provided, semiconductor substrate has gate structure compact district and gate structure rarefaction, gate structure intensive
The semiconductor substrate surface in area has the first fin and the first grid structure across the first fin, first grid structure covering part
Divide the top surface and side wall of the first fin；The semiconductor substrate surface of gate structure rarefaction has the second fin and across the
The second grid structure of two fins, the top surface and side wall of second grid structure the second fin of covering part；
Form spacer material layer, the spacer material layer covering gate structure compact district and gate structure rarefaction, the side wall
Material layer includes the first spacer material layer and second side walling bed of material, and the first spacer material layer covers first grid structure, second
Table at the top of second fin of gate structure, the first fin top surface of first grid structure two sides and second grid structure two sides
Face, the first spacer material layer do not cover first grid structure two sides the first fin side wall and second grid structure two sides second
Fin side wall, second side walling bed of material cover the first fin side wall and the second grid structure two sides of first grid structure two sides
Second fin side wall, and the thickness of second side walling bed of material is less than the thickness of the first spacer material layer；
Spacer material layer is etched, side wall is formed, the side wall and second grid structure of first grid structure is completely covered in the side wall
Side wall, and the first fin portion surface and the second grid structure two sides of first grid structure two sides are completely exposed in the side wall
Second fin portion surface.
2. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that form the side wall material
The step of bed of material are as follows: the first forerunner for being used to form spacer material layer is passed through from first grid structure and second grid structural top
Body gas；Plasmarized first precursor gas；The first plasmarized precursor gas is adsorbed on first
First grid body structure surface, second grid body structure surface, first grid structure two sides the first fin top surface and second gate
Then second fin top surface of pole structure two sides is adsorbed on the first fin side wall and second gate of first grid structure two sides
Second fin side wall of pole structure two sides；The first plasmarized precursor gas and first grid structure, second gate
Pole structure, the first fin and the second fin are chemically reacted, and the spacer material layer is formed.
3. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that the shape in dry etching board
At the spacer material layer.
4. the forming method of fin formula field effect transistor according to claim 3, which is characterized in that in the dry etching board
In, it forms the spacer material layer and etches the process of the spacer material layer while carrying out.
5. the forming method of fin formula field effect transistor according to claim 3, which is characterized in that in the dry etching board
In, it forms the spacer material layer and the spacer material layer is performed etching later.
6. the forming method of fin formula field effect transistor according to claim 3, which is characterized in that form the side wall material
The technological parameter of the bed of material are as follows: the gas used is N2, N2Flow be 100sccm~500sccm, plasmarized source power is
500KeV~1500KeV, bias voltage 0V.
7. the forming method of fin formula field effect transistor according to claim 3, which is characterized in that form the side wall material
The technological parameter of the bed of material are as follows: the gas used is CH4, CH4Flow be 100sccm~500sccm, plasmarized source power
For 500KeV~1500KeV, bias voltage 0V.
8. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that the first side wall material
The bed of material with a thickness of 10nm~30nm.
9. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that second side walling
The bed of material with a thickness of 5nm~25nm.
10. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that use isotropism
The technique that dry carving technology and anisotropy dry carving technology combine etches the spacer material layer.
11. the forming method of fin formula field effect transistor according to claim 10, which is characterized in that using first respectively to different
Property dry carving technology after isotropism dry carving technology etch the spacer material layer.
12. the forming method of fin formula field effect transistor according to claim 11, which is characterized in that first anisotropic dry
The parameter of carving technology are as follows: the gas used is CH3F、O2And He, CH3The flow of F is 100sccm~250sccm, O2Flow be
The flow of 50sccm~200sccm, He are 300sccm~500sccm, and source radio-frequency power is 1000KeV~1800KeV, biasing
Radio-frequency power is 200KeV~250KeV, and etching cavity pressure is 50mtorr~100mtorr；Isotropism dry carving technology afterwards
Parameter are as follows: the gas of use includes CH3F、CO2And Ar, CH3The flow of F is 50sccm~100sccm, CO2Flow be
The flow of 10sccm~60sccm, Ar are 300sccm~800sccm, and source radio-frequency power is 500KeV~1000KeV, and biasing is penetrated
Frequency power is 0KeV~50KeV, and etching cavity pressure is 50mtorr~1000mtorr.
13. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that further include: form institute
After stating side wall, the first source region and the first drain region are formed in gate structure compact district, it is intensive that first source region is located at gate structure
The side wall in area and the first fin portion surface of first grid structure side, first drain region is located at the side wall of gate structure compact district
With the first fin portion surface of the first grid structure other side；The second source region and the second drain region, institute are formed in gate structure rarefaction
It states the second source region and is located at the side wall of gate structure rarefaction and the second fin portion surface of second grid structure side, second leakage
Area is located at the side wall of gate structure rarefaction and the second fin portion surface of the second grid structure other side.
14. the forming method of fin formula field effect transistor according to claim 13, which is characterized in that when gate structure is close
The fin field effect crystal that the type for the fin formula field effect transistor that Ji Qu is used to form and gate structure rarefaction are used to form
When the type of pipe is identical, first source region, the first drain region, the second source region and the second drain region are formed simultaneously.
15. the forming method of fin formula field effect transistor according to claim 14, which is characterized in that form described first
The step of source region, the first drain region, the second source region and the second drain region are as follows: the first fin and second in first grid structure two sides
Second fin portion surface epitaxial growth source-drain area material layer of gate structure two sides；To the source-drain area material layer Doped ions；It mixes
After heteroion, the source-drain area material layer is made annealing treatment.
16. the forming method of fin formula field effect transistor according to claim 15, which is characterized in that when gate structure is close
When Ji Qu and gate structure rarefaction are used to form N-type fin formula field effect transistor, the material of the source-drain area material layer is carbon
SiClx；When gate structure compact district and gate structure rarefaction are used to form p-type fin formula field effect transistor, the source-drain area
The material of material layer is SiGe.
17. the forming method of fin formula field effect transistor according to claim 15, which is characterized in that when gate structure is close
When Ji Qu and gate structure rarefaction are used to form N-type fin formula field effect transistor, the ion is N-type ion；When grid knot
When structure compact district and gate structure rarefaction are used to form p-type fin formula field effect transistor, the ion is P-type ion.
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| CN104183500A (en) * | 2014-08-15 | 2014-12-03 | 上海华力微电子有限公司 | Method for forming ion-implantation side wall protection layer on FinFET device |
| CN104465386A (en) * | 2013-09-24 | 2015-03-25 | 中芯国际集成电路制造(北京)有限公司 | Method for forming semiconductor structure |
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| CN104183500A (en) * | 2014-08-15 | 2014-12-03 | 上海华力微电子有限公司 | Method for forming ion-implantation side wall protection layer on FinFET device |
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