CN106356313B - The test method of landscape insulation bar double-pole-type transistor interfacial state and 5 port devices - Google Patents
The test method of landscape insulation bar double-pole-type transistor interfacial state and 5 port devices Download PDFInfo
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- CN106356313B CN106356313B CN201610972493.4A CN201610972493A CN106356313B CN 106356313 B CN106356313 B CN 106356313B CN 201610972493 A CN201610972493 A CN 201610972493A CN 106356313 B CN106356313 B CN 106356313B
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
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- G—PHYSICS
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Abstract
A kind of test method and 5 port devices of landscape insulation bar double-pole-type transistor interfacial state, the test method feature of landscape insulation bar double-pole-type transistor interfacial state is, test including channel region, beak area, polysilicon gate field plate region and field plate termination area charge pump current, when being tested, 5 port devices are first manufactured beside target devices on same wafer, system building is carried out to 5 port devices of auxiliary and test condition is set, finally carries out charge pump current test operation；A kind of 5 port devices of the test method for landscape insulation bar double-pole-type transistor interfacial state, it is characterized in that, including charge pump electric provides area and a charge pump special test electrode, the charge pump electric provides area and anode P+Area is in the top of N-type buffer area side by side, and is individually connected with charge pump special test electrode；The present invention can solve the problem of conventional method cannot test the interface damage in landscape insulation bar double-pole-type transistor polysilicon gate field plate region and field plate termination area.
Description
Technical field
The invention belongs to power semiconductor reliability fields, and in particular to a kind of landscape insulation bar double-pole-type transistor
The test method of interfacial state and 5 port devices.
Background technique
Landscape insulation bar double-pole-type transistor (lateral insulated gate bipolar transistor,
It LIGBT is) a kind of partly to lead bipolar transistor and the compound power that metal oxide semiconductor field effect tube is combined into
Body device has the characteristics that breakdown voltage is high, fan-out capability is strong and can integrate.Silicon (silicon on insulating layer
Insulator, SOI) technique has many advantages, such as that parasitic capacitance is small, isolation performance is good and integrated level is high.Therefore, it is based on SOI technology
LIGBT device be widely used in power integrated circuit field.However, due to the high temperature, high voltage, height of SOI-LIGBT device
Power operating condition, device are faced with the influence of serious hot carrier's effect.Hot carrier in jection will cause device oxide layer
And Si/SiO2The damage at interface generates interface trap and oxide trapped charge in device inside, leads to device electrical parameter
It degenerates.
Currently, charge pump (charge pumping, CP) test is that research device interface damage is most effective, most reliable side
Method, as shown in Fig. 2, its working principle is that: add a reversed bias voltage simultaneously in device source-drain electrode, gate electrode adds the pulse electricity of a variation
Pressure, in the ascent stage of the pulse voltage, channel surface is depleted and progresses into anti-type state, and electronics will be from source-drain area at this time
Channel is flowed into, a portion can be captured by interfacial state；When the decline stage device of the pulse voltage returns to accumulated state, ditch
Movable electronic in road is floated again due to the effect of source and drain reversed bias voltage returns to source region and drain region, but one be trapped in interfacial state
Point electronics is still trapped in interfacial state after channel disappearance due to moving back trap time constant with longer, finally with come
From the hole-recombination of substrate, thus produce substrate current, i.e. charge pump current Icp, it is directly proportional to interface state density, device
Part gate electrode area, the frequency of added gate pulse and participation generate the interfacial state energy range of charge pump current.Pass through public affairs
Formula 1 can calculating device interface state density.
DitFor interface state density, q is elementary charge, and f is gate pulse frequency, and W, L are respectively the width and length of channel, Δ E silicon
Energy difference of the surface in transoid and accumulation between fermi level.Therefore it is inswept to can reflect out grid voltage pulse for charge pump current
The average value of the density of energy band range interface states, so as to indirectly reflect the journey of the heated carrier effect damage of device
Degree.By the height variation of CP test curve before and after stress, the interfacial state number of device surface damage field can be extracted
Amount, and deviated by the left and right of CP curve before and after stress, then it can extract the thermoelectron or hot hole of damage position injection
Quantity.
Conventional SOI-LIGBT device architecture is as shown in Figure 4, in which: 1 is P type substrate, and 2 be buries oxide layer, and 3 be N-type drift
Area is moved, 4 be the area PXing Ti, and 5 be cathode P+Area, the area You Ti metal contact thereon 7,6 is cathode N+There is metallization cathode 8 in area thereon,
9 be gate oxide, and 10 be polysilicon gate, and 11 be passivation layer, and 12 be field oxide, and 13 be polysilicon, and 15 be anode P+Area, polycrystalline
Silicon 13 and anode P+Area 15 connects with metallization anode 16, and 14 be N-type buffer area.By the above structure it is found that SOI-LIGBT anode
It is the emitter of device inside parasitic triode, needing to emit junction voltage and reaching 0.7V can just open.In charge pump test wrapper
Under border, cathode and anode are grounded, and emitter junction is in zero bias condition, can not be made inside parasitic triode by anode P+Area 15
The PN junction formed with N-type drift region 3 is connected.Therefore, traditional SOI-LIGBT device only can just measure CP after channel unlatching
Electric current, so electric current can only be measured in channel region and beak area, to produce incomplete CP test result, nothing shown in Fig. 6
Method reflects the interfacial state of polysilicon gate field plate region and field plate termination.
For this purpose, we have proposed a kind of test sides for silicon-on-insulator lateral insulated gate bipolar transistor interfacial state
Method, in SOI-LIGBT device inside anode P+Increase charge pump electric by area and area, new construction device and traditional structure device are provided
Degradation mechanism it is identical, do not change device electrology characteristic and do not bring reduce pressure problem under the premise of, obtain
Complete CP test result.
Summary of the invention
The present invention provides the test method and 5 port devices of a kind of landscape insulation bar double-pole-type transistor interfacial state, can be
On the basis of not changing device electrology characteristic, each region of device inside especially polysilicon gate field plate region and field plate termination are tested out
The interface damage in area to solve SOI-LIGBT carries out that polysilicon gate field plate and field plate termination circle can not be measured when CP experiment
The problem of face state.
The present invention adopts the following technical scheme:
A kind of test method of landscape insulation bar double-pole-type transistor interfacial state, including channel region and beak area charge pump electricity
The test of stream, it is characterized in that, it further include the test of polysilicon gate field plate region and field plate termination area charge pump current, the polysilicon
The test of grid field plate region and field plate termination area charge pump current uses following methods:
First manufacture assists 5 port devices beside target devices on same wafer, and 5 port devices of the auxiliary are in tradition
Charge pump electric is set in the N-type buffer area of landscape insulation bar double-pole-type transistor, area is provided；System building is carried out again, will be assisted
5 port devices cathode N+Area and charge pump electric provide area and are shorted, and 5 areas port devices PXing Ti is being assisted to mention with charge pump electric
Reverse bias voltage is provided between donor site, gate electrode is used for external load pulses voltage, finally carry out polysilicon gate field plate region and
The test operation of field plate termination area charge pump current: the load pulses voltage on gate electrode makes field plate lower section N-type drift region in product
Switch between tired state and anti-type state, when N-type drift region is in accumulated state, if channel is opened at this time, cathode N+In area
Electronics will be flowed into polysilicon gate field plate region and field plate termination area by channel, and the electronics that charge pump electric is provided in area will flow through
N-type buffer area and N-type drift region are flowed into polysilicon gate field plate region and field plate termination area, if channel region is fail to open at this time,
Electronics needed for charge pump electric offer area is individually for the charge pump test offer in polysilicon gate field plate region and field plate termination area, two kinds
In the case of some electrons captured by polysilicon gate field plate region and field plate termination area interfacial state；When N-type drift region is in
Anti-type state, if channel is open state at this time, the movable electronic in polysilicon gate field plate region and field plate termination area is in reversed bias voltage
Under the action of drift return to cathode N+Area and charge pump electric provide area, if channel is in off state at this time, polysilicon gate field plate
The movable electronic in area and field plate termination area floated under the action of reversed bias voltage return to charge pump electric provide area be then trapped in
Electronics in polysilicon gate field plate region and field plate termination area interfacial state by with the hole-recombination from the area PXing Ti, generate charge pump
Thus electric current obtains the interfacial state of 5 port devices polysilicon gate field plate regions and field plate termination area of auxiliary, measured 5 end of auxiliary
The interfacial state in mouthpart part polysilicon gate field plate region and field plate termination area is target devices polysilicon gate field plate region and field plate termination
The interfacial state in area.
The test of channel region and beak area charge pump current uses following methods: the pulse electricity changed to gate electrode plus one
Pressure, when pulse voltage, which changes to, converts channel region between anti-type state and accumulated state, in the rising of the pulse voltage
Stage, channel surface are depleted and progress into anti-type state, and electronics will be from cathode N+Area and charge pump electric area flow into channel
Area and beak area, a portion can be captured by interfacial state；In the decline stage of the pulse voltage, device returns to accumulated state
When, the movable electronic in channel region and beak area floats under the action of reversed bias voltage returns to cathode N+Area and charge pump electric area,
Excess electron channel disappearance after be still trapped in interfacial state, and with the hole-recombination from the area PXing Ti, generate charge pump
Electric current is measured the charge pump current of channel region and beak area by galvanometer, is thus assisted 5 port devices channel regions and bird out
The interfacial state in the interfacial state in mouth area, measured 5 port devices channel region of auxiliary and beak area be target devices channel region and
The interfacial state in beak area.
A kind of 5 port devices of the test method for landscape insulation bar double-pole-type transistor interfacial state, comprising: p-type lining
Bottom, the P type substrate are equipped with buries oxide layer, and N-type drift region is equipped in buries oxide layer, and p-type body is equipped in N-type drift region
Area and N-type buffer area are equipped with anode P in the inside of N-type buffer area+Area is equipped with cathode P in the area PXing Ti+Area and cathode N+Area
And it is in the top in the area PXing Ti side by side, gate oxide and field oxide, and gate oxide are equipped on the surface of N-type drift region
One end and one end of field oxide offset, and the other end of the gate oxide is to cathode N+Area extends and terminates in cathode N+The side in area
Boundary, the other end of the field oxide is to anode P+Area extends and terminates in the anode P+The boundary in area, on the surface of gate oxide
Equipped with polysilicon gate and the polysilicon gate extends to the upper surface of field oxide, and the right upper of field oxide has polysilicon,
In field oxide, cathode P+Area, cathode N+Area, polysilicon gate, anode P+The surface in area is equipped with passivation layer, in anode P+Area and more
The surface of crystal silicon is connected with metallization anode, in cathode N+The surface in area is connected with metallization cathode, in cathode P+The surface in area connects
It is connected to the contact of body area metal, is connected with gate electrode in polycrystalline silicon gate surface, which is characterized in that further include that a charge pump electric mentions
Donor site and a charge pump special test electrode, the charge pump electric provide area and anode P+Area is in N-type buffer area side by side
Top, and the charge pump electric provide area be connected with charge pump special test electrode, cathode N+Area is mentioned with charge pump electric
Donor site is shorted, in cathode N+Area and charge pump electric, which provide, to be connected between area for providing the power supply of reverse bias voltage, institute
Stating charge pump electric and providing sector width is 1 μm -3 μm, and doping concentration is higher than the doping concentration of N-type buffer area.
Compared with prior art, the present invention has the advantage that
(1) the method for the present invention simple and quick can measure SOI-LIGBT device inside compared with existing charge pump test method
Each region interface state damage solves traditional SOI-LIGBT device and carries out that polysilicon gate field plate and field plate can not be measured when CP experiment
The problem of end interfaces state.When measuring the interfacial state quantity of polysilicon gate field plate region and field plate termination area, add on gate electrode
Pulse voltage switches N-type drift region 3 below field plate between accumulated state and anti-type state.If channel region can not be opened at this time
It opens, cathode N+Area 6 cannot provide electronics for polysilicon gate field plate region and field plate termination area, and electronics needed for charge pump is tested is by charge
It pumps electronics and the offer of area 17 is provided.When N-type drift region 3 is in accumulated state, electronics will flow through N-type buffering from charge pump electric area 17
Area 14 and N-type drift region 3 are flowed into polysilicon gate field plate region and field plate termination area, and a portion can be captureed by interfacial state at this
It obtains；When N-type drift region 3 is in anti-type state, the movable electronic in polysilicon gate field plate region and field plate termination area is due to reversed bias voltage
Effect float again and return to charge pump electric area 17 is provided, but be trapped in a part of electronics in interfacial state due to moving back with longer
Trap time constant is still trapped in interfacial state, finally with the hole-recombination from the area PXing Ti 4, to produce compound electric
Stream, i.e. charge pump current.Therefore, the present invention can be tested by charge pump and show polysilicon gate field plate region and field plate termination
Interfacial state, each region interface damage of research device inside, specifies device hot carrier degradation mechanism.This method measures complete CP
Electric current is as shown in fig. 7, and Fig. 6 show the imperfect CP current curve that conventional method measures.
(2) structure of the invention will not change device compared with the device of traditional SOI-LIGBT structure shown in Fig. 4
Electrical parameter and degradation mechanism can be used for assistant analysis device degradation mechanism.As shown in figure 8, structure of the invention and traditional structure
It compares, breakdown voltage is basically unchanged.As shown in figure 9, structure of the invention, compared with traditional structure, output characteristics is basically unchanged.
(3) structure of the invention provides charge pump electric to area 17 and is placed in N-type buffer area 4, mentions with by charge pump electric
Donor site 17 is placed on N-type drift region 3 and compares, and device has lower off-state leakage current and broader ON state safety operation area.
(4) manufacturing process of device architecture of the present invention is mutually compatible with traditional SOI-LIGBT manufacturing process, does not increase technique hardly possible
Degree and photoetching release, save the cost have very strong exploitativeness.
Detailed description of the invention
Fig. 1 is charge pump test method flow chart.
Fig. 2 is charge pump test schematic.
Fig. 3 is the charge pump test wiring diagram of SOI-LIGBT interfacial state.
Fig. 4 is traditional SOI-LIGBT device architecture schematic diagram.
Fig. 5 is the 5 port SOI-LIGBT device architecture schematic diagrames provided by the invention for carrying out charge pump experiment.
Fig. 6 is traditional SOI-LIGBT device CP test result figure.
Fig. 7 is that the CP test result of structure of the invention device and traditional SOI-LIGBT device compares figure.
Fig. 8 is the device of structure of the invention and the device OFF state breakdown characteristics test result of traditional SOI-LIGBT structure
Compare figure.
Fig. 9 be structure of the invention device compared with the I-V test result of the device of traditional SOI-LIGBT structure figure.
Specific embodiment
A kind of test method of landscape insulation bar double-pole-type transistor interfacial state, including channel region and beak area charge pump electricity
The test of stream, it is characterized in that, it further include the test of polysilicon gate field plate region and field plate termination area charge pump current, the polysilicon
The test of grid field plate region and field plate termination area charge pump current uses following methods:
5 port devices are first manufactured beside target devices on same wafer, 5 port devices of the auxiliary are traditional lateral
Setting charge pump electric provides area 17 in the N-type buffer area 14 of insulated gate bipolar transistor；System building, charge pump are carried out again
The instrument that we use of testing for testing interface states quantity is semi-conductor test instrument Keithley4200, from Keithley4200
Three leads of middle extraction, one is cathode N+Area 6 and charge pump electric provide area 17 and provide reverse bias voltage (5 ports of auxiliary
Device cathodes N+Area 6 and charge pump electric provide area 17 and are shorted, and share a conducting wire), an area piece-root grafting PXing Ti 4, in addition one is
Gate electrode 19 provides on-load voltage, and on-load voltage is that an electric voltage frequency and amplitude are fixed, and reference voltage variation, amplitude is greater than flat rubber belting
The pulse voltage of voltage and threshold voltage pressure difference, device each section flat-band voltage and threshold voltage are obtained by device simulation, this
In experiment, setting reference voltage changes to 5V from -20V, step-length 0.1V, and setting voltage amplitude is 8V, electric voltage frequency 1MHz,
Rising edge and failing edge are 10-7S, duty ratio 50%；Charge pump current is introduced to the in-built electrical flow table of Keithley4200,
Then Keithley4200 test interface be arranged test condition, including on-load voltage impulse amplitude, pulse frequency, duty ratio with
And test pattern, charge pump current is measured by Keithley4200 after being tested, records experimental data.Carry out polysilicon gate
When the test of field plate region and field plate termination area charge pump current, the load pulses voltage on gate electrode 19 makes N-type drift below field plate
Area 3 is moved to switch between accumulated state and anti-type state, when N-type drift region 3 is in accumulated state, if channel is opened at this time, yin
Pole N+Electronics in area 6 will be flowed into polysilicon gate field plate region and field plate termination area by channel, and charge pump electric provides area 17
In electronics will flow through N-type buffer area 14 and N-type drift region 3 is flowed into polysilicon gate field plate region and field plate termination area, if at this time
Channel region is fail to open, then charge pump electric provides the charge pump survey that area 17 is individually for polysilicon gate field plate region and field plate termination area
Examination provides required electronics, and some electrons are captureed by polysilicon gate field plate region and field plate termination area interfacial state in the case of two kinds
It obtains；When N-type drift region 3 is in anti-type state, if channel is open state at this time, polysilicon gate field plate region and field plate termination area
Movable electronic floats under the action of reversed bias voltage returns to cathode N+Area 6 and charge pump electric provide area 17, if channel is to close at this time
Closed state, then the movable electronic in polysilicon gate field plate region and field plate termination area floats under the action of reversed bias voltage returns to charge pump electricity
Son provides area 17, then, be trapped in electronics in polysilicon gate field plate region and field plate termination area interfacial state will with from the area PXing Ti
4 hole-recombination generates charge pump current, thus obtains 5 port devices polysilicon gate field plate regions of auxiliary and field plate termination area
The interfacial state in interfacial state, measured 5 port devices polysilicon gate field plate region of auxiliary and field plate termination area is that target devices are more
The interfacial state of crystal silicon grid field plate region and field plate termination area.
The test of channel region and beak area charge pump current uses following methods: the pulse electricity changed to gate electrode plus one
Pressure, when pulse voltage, which changes to, converts channel region between anti-type state and accumulated state, in the rising of the pulse voltage
Stage, channel surface are depleted and progress into anti-type state, and electronics will be from cathode N+Area 6 and charge pump electric area 17 flow into ditch
Road area and beak area, a portion can be captured by interfacial state；In the decline stage of the pulse voltage, device returns to accumulated state
When, the movable electronic in channel region and beak area floats under the action of reversed bias voltage returns to cathode N+Area 6 and charge pump electric area
17, excess electron channel disappearance after be still trapped in interfacial state, and with the hole-recombination from the area PXing Ti 4, generate electricity
Lotus pumps electric current, and the charge pump current of channel region and beak area is measured by galvanometer, is thus assisted 5 port devices channel regions out
With the interfacial state in beak area, the interfacial state in measured 5 port devices channel region of auxiliary and beak area is target devices channel
The interfacial state in area and beak area.
A kind of 5 port devices of the test method for landscape insulation bar double-pole-type transistor interfacial state, comprising: p-type lining
Bottom 1, the P type substrate 1 are equipped with buries oxide layer 2, and N-type drift region 3 is equipped in buries oxide layer 2, is set in N-type drift region 3
The area YouPXing Ti 4 and N-type buffer area 14 are equipped with anode P in the inside of N-type buffer area 14+Area 15 is equipped with yin in the area PXing Ti 4
Pole P+Area 5 and cathode N+Area 6 and the top for being in the area PXing Ti 4 side by side are equipped with gate oxide 9 and field on the surface of N-type drift region 3
Oxide layer 12, and one end of gate oxide 9 and one end of field oxide 12 offset, the other end of the gate oxide 9 is to cathode N+Area 6 extends and terminates in cathode N+The boundary in area 6, the other end of the field oxide 12 is to anode P+Area 15 extends and terminates in described
Anode P+The boundary in area 15 is equipped with polysilicon gate 10 on the surface of gate oxide 9 and the polysilicon gate 10 extends to field oxidation
The upper surface of layer 12, the right upper of field oxide 12 has polysilicon 13, in field oxide 12, cathode P+Area 5, cathode N+Area 6,
Polysilicon gate 10, anode P+The surface in area 15 is equipped with passivation layer 11, in anode P+Area 15 and the surface of polysilicon 13 are connected with metal
Change anode 16, in cathode N+The surface in area 6 is connected with metallization cathode 8, in cathode P+The surface in area 5 is connected with body area metal and connects
Touching 7, is connected with gate electrode 19 in polycrystalline silicon gate surface, which is characterized in that further includes that a charge pump electric provides area 17 and one
A charge pump special test electrode 18, the charge pump electric provide area 17 and anode P+Area 15 is in N-type buffer area 14 side by side
Top, and the charge pump electric provide area 17 be connected with charge pump special test electrode 18, cathode N+Area 6 and charge pump electricity
Son provides area 17 and is shorted, in cathode N+Area 6 and charge pump electric, which provide, to be connected between area 17 for providing reverse bias voltage
Power supply.
It is 1 μm -3 μm that the charge pump electric, which provides 17 width of area, and doping concentration is dense higher than the doping of N-type buffer area 14
Degree.
Claims (4)
1. a kind of test method of landscape insulation bar double-pole-type transistor interfacial state, including channel region and beak area charge pump current
Test, it is characterized in that, further include the test of polysilicon gate field plate region and field plate termination area charge pump current, the polysilicon gate
The test of field plate region and field plate termination area charge pump current uses following methods:
First manufacture assists 5 port devices beside target devices on same wafer, and 5 port devices of the auxiliary are in lateral isolation
Setting charge pump electric provides area (17) in the N-type buffer area (14) of grid bipolar junction transistor；System building is carried out again, will be assisted
5 port devices cathode N+Area (6) and charge pump electric provide area (17) and are shorted, and are assisting 5 areas port devices PXing Ti (4) and electricity
Lotus pump electronics, which provides, provides reverse bias voltage between area (17), gate electrode (19) is used for external load pulses voltage, most laggard
The test operation of row polysilicon gate field plate region and field plate termination area charge pump current: the load pulses voltage on gate electrode (19),
Switch N-type drift region (3) below field plate between accumulated state and anti-type state, when N-type drift region (3) are in accumulation shape
State, if channel is opened at this time, cathode N+Electronics in area (6) will be flowed into polysilicon gate field plate region and field plate termination by channel
Area, the electronics that charge pump electric provides in area (17) will flow through N-type buffer area (14) and N-type drift region (3) is flowed into polysilicon
Grid field plate region and field plate termination area, if channel region is fail to open at this time, charge pump electric provides area (17) and is individually for polysilicon
The test of the charge pump in grid field plate region and field plate termination area provides required electronics, and some electrons are by polycrystalline in the case of two kinds
Si-gate field plate region and the capture of field plate termination area interfacial state；When N-type drift region (3) is in anti-type state, if channel is to open at this time
The movable electronic in state, polysilicon gate field plate region and field plate termination area floats under the action of reversed bias voltage returns to cathode N+Area (6)
There is provided area (17) with charge pump electric, if channel is in off state at this time, polysilicon gate field plate region and field plate termination area can
Dynamic electronics float under the action of reversed bias voltage to be returned to charge pump electric offer area (17) and is then trapped in polysilicon gate field plate region
And the electronics in field plate termination area interfacial state will generate charge pump current with the hole-recombination for coming from the area PXing Ti (4), thus
To the interfacial state of 5 port devices polysilicon gate field plate regions and field plate termination area of auxiliary, measured 5 port devices polysilicon of auxiliary
The interfacial state in grid field plate region and field plate termination area is the interfacial state of target devices polysilicon gate field plate region and field plate termination area.
2. the test method of landscape insulation bar double-pole-type transistor interfacial state according to claim 1, which is characterized in that ditch
The test of road area and beak area charge pump current uses following methods: the pulse voltage changed to gate electrode plus one, when pulse electricity
Pressure changes to when converting channel region between anti-type state and accumulated state, in the ascent stage of the pulse voltage, channel table
Face is depleted and progresses into anti-type state, and electronics will be from cathode N+Area (6) and charge pump electric area (17) flow into channel region and
Beak area, a portion can be captured by interfacial state；In the decline stage of the pulse voltage, when device returns to accumulated state, ditch
Movable electronic in road area and beak area floats under the action of reversed bias voltage returns to cathode N+Area (6) and charge pump electric area
(17), excess electron channel disappearance after be still trapped in interfacial state, and with come from the area PXing Ti (4) hole-recombination, produce
Raw charge pump current, the charge pump current of channel region and beak area is measured by galvanometer, is thus assisted 5 port devices ditches out
The interfacial state in the interfacial state in road area and beak area, measured 5 port devices channel region of auxiliary and beak area is target devices
The interfacial state of channel region and beak area.
3. a kind of 5 port devices of the test method for landscape insulation bar double-pole-type transistor interfacial state, comprising: P type substrate
(1), the P type substrate (1) is equipped with buries oxide layer (2), is equipped with N-type drift region (3) on buries oxide layer (2), drifts about in N-type
The area PXing Ti (4) and N-type buffer area (14) are equipped in area (3), are equipped with anode P in the inside of N-type buffer area (14)+Area (15),
Cathode P is equipped in the area PXing Ti (4)+Area (5) and cathode N+Area (6) and the top for being in the area PXing Ti (4) side by side, in N-type drift region
(3) surface is equipped with gate oxide (9) and field oxide (12), and the one of one end of gate oxide (9) and field oxide (12)
End offsets, and the other end of the gate oxide (9) is to cathode N+Area (6) extends and terminates in cathode N+The boundary in area (6), the field
The other end of oxide layer (12) is to anode P+Area (15) extends and terminates in the anode P+The boundary in area (15), in gate oxide (9)
Surface be equipped with the upper surface that polysilicon gate (10) and the polysilicon gate (10) extend to field oxide (12), field oxide
(12) right upper has polysilicon (13), in field oxide (12), cathode P+Area (5), cathode N+Area (6), polysilicon gate
(10), anode P+The surface in area (15) is equipped with passivation layer (11), in anode P+Area (15) and the surface of polysilicon (13) are connected with gold
Categoryization anode (16), in cathode N+The surface in area (6) is connected with metallization cathode (8), in cathode P+The surface in area (5) is connected with
Body area metal contacts (7), is connected with gate electrode (19) in polycrystalline silicon gate surface, which is characterized in that further include a charge pump electricity
Son provides area (17) and a charge pump special test electrode (18), and the charge pump electric provides area (17) and anode P+Area
(15) it is in the top of N-type buffer area (14) side by side, and the charge pump electric provides area (17) and charge pump special test electricity
Pole (18) is connected, cathode N+Area (6) and charge pump electric provide area (17) and are shorted, in cathode N+Area (6) and charge pump electric provide
Area is connected between (17) for providing the power supply of reverse bias voltage.
4. 5 port devices according to claim 3, which is characterized in that it is 1 that the charge pump electric, which provides area's (17) width,
μm -3 μm, and doping concentration is higher than the doping concentration of N-type buffer area (14).
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