CN106311625B - Semiconductor element classification method - Google Patents
Semiconductor element classification method Download PDFInfo
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- CN106311625B CN106311625B CN201510336366.0A CN201510336366A CN106311625B CN 106311625 B CN106311625 B CN 106311625B CN 201510336366 A CN201510336366 A CN 201510336366A CN 106311625 B CN106311625 B CN 106311625B
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Abstract
The present invention discloses a kind of semiconductor element classification method, includes: defining multiple semiconductor elements on a bogey is multiple specification areas；A selected operation is provided, selecting one of multiple specification area specification area is one first sorting area；One sorting operation is provided, the one or more semiconductor elements for first sorting area being attached on the bogey are taken out；And an overturning operation is provided, take out the one or more semiconductor elements for being attached to another specification area of multiple specification area on the bogey.
Description
Technical field
The present invention relates to the classification methods of semiconductor element, more particularly, to a kind of classification side of semiconductor light-emitting elements
Method.
Background technique
In semiconductor rear section manufacture craft, a cutting is that the chip of multiple semiconductor elements is surveyed in passing point
(Probing) it after specification classification, can partly be led via sorting equipment (Sorter) or turnover device (die flipper) by multiple
Volume elements part is according to different size classifying and selecting and packs, and is sent to different client or inventory storehouse.
When being picked using sorting device progress semiconductor element, although can be according to every semiconductor element different size
(bin) it carries out classification to pick, but its equipment manufacturing cost is expensive, maintenance cost is high, and is once only capable of single and picks, and picks speed
Slowly, not enough there is economic benefit；If carrying out classification choosing using tipping arrangement, since rule different from identification cannot be distinguished in tipping arrangement
The semiconductor element of lattice is only capable of doing a wide range of semiconductor element with approximate specification and chooses, can not will according to different size
The semiconductor element of dispersion is successively chosen single sorting of progress and is taken.
Summary of the invention
To solve the above problems, the present invention discloses a kind of semiconductor element classification method, include: defining on a bogey
Multiple semiconductor elements be multiple specification areas；A selected operation is provided, selecting a specification area therein is a sorting
Region；One sorting operation is provided, the semiconductor element for the sorting area being attached on the bogey is taken out；And provide one
Operation is overturn, the semiconductor element for another specification area being attached on the bogey is taken out.
A kind of semiconductor element classification method includes: providing a selected operation, selectes more than one first on a bogey
A semiconductor element is a sorting area；One sorting operation is provided, first off-sorting station being attached on the bogey is taken out
One or more semiconductor elements in domain；And an overturning operation is provided, take out more than one second be attached on the bogey
A semiconductor element.
Detailed description of the invention
Figure 1A is the schematic diagram of the semiconductor element classification method of the embodiment of the present invention；
Figure 1B is sorting device schematic diagram used in the embodiment of the present invention；
Fig. 1 C is tipping arrangement schematic diagram used in the embodiment of the present invention；
Fig. 2A is the multiple semiconductor element photoelectric characteristic distribution maps of the present invention；
Fig. 2 B is the multiple semiconductor element photoelectric characteristic distribution schematic diagrams of the present invention；
Fig. 2 C be the embodiment of the present invention classification process and selection after arrange schematic diagram；
Fig. 2 D be the embodiment of the present invention classification process and selection after arrange schematic diagram.
Symbol description
10 chips
10a semiconductor element
12 first adhesion coatings
12 ' second adhesion coatings
15 first carrying platforms
16 second carrying platforms
17 computer systems
18 pick device
100 sorting devices
20 substrates
22 first bogeys
23 second bogeys
24 third bogeys
25 first carrying platforms
26 second carrying platforms
27 air bags
27a cushion
28 heaters
29 pressurizers
Defect Bin failure area
200 attaching apparatus
1 first specification area of Bin
2 second specification area of Bin
3 third specification area of Bin
The 4th specification area of Bin 4
The 5th specification area of Bin 5
The 6th specification area of Bin 6
1 first separator bar of Line
2 second separator bar of Line
3 third separator bar of Line
Specific embodiment
Figure 1A is the semiconductor element classification method of first embodiment of the invention.If Figure 1A is shown, a kind of semiconductor element
Part classification method includes: defining multiple semiconductor elements on a bogey includes multiple specification areas；Select multiple classification
One of region is a sorting area, and the another of multiple specification areas is an overturning region；By a sorting operation, selection is attached to
The semiconductor element of sorting area on bogey；And by an overturning operation, selection is attached to turning on bogey
Turn the semiconductor element in region.
Semiconductor element is the electric circuitry packages that specific function is completed using the specific electrical properties of semiconductor material, packet
Containing light emitting diode or transistor, the semiconductor element of the present embodiment refers to light emitting diode, includes a substrate, the first electric conductivity
Semiconductor layer, shine lamination, the second conductive semiconductor layer, via MOCVD or MBE extensional mode in formation half on a chip
Conductor lamination forms semiconductor structure after photomask develops and defines the position platform (mesa), then via etching flat-bed format, then
Electrode is formed with plated film or routing mode, finally forms more semiconductor elements by cutting.Multiple semiconductor elements after cutting
The advanced professional etiquette lattice classification of part, the specification classification of the present embodiment are to survey operation first with to define multiple classification areas according to photoelectric characteristic
Domain；Then selecting one or more specification areas again is sorting area.In one embodiment, semiconductor element is because of extension or element system
It causes its photoelectric characteristic to be less dispersed in epitaxial chip as technique, or damages the semiconductor element of failure, it is also possible to
It is the semiconductor element that number is less in different size, the region where these semiconductor elements is chosen to be sorting area.
Then, the semiconductor element that an at least sorting operation chooses sorting area is provided, at this time in semiconductor remaining on bogey
The range of element is to overturn region.Finally, choosing by least one overturning operation and being attached to overturning region on bogey
Semiconductor element.In one embodiment, overturning region can be that photoelectric characteristic is more uniform and the semiconductor element of concentration, number are more
Semiconductor element.Cooperate overturning operation by sorting operation, is considered with reaching the optimal cost of classification and efficiency.Semiconductor element
Defining classification is carried out comprising the difference of foundation customer demand specification or default specification photoelectric characteristic range in the defining classification region of part,
Photoelectric characteristic includes brightness, and emission wavelength operates voltage, operation electric current or element power.
Figure 1B is sorting device 100 used in sorting operation in first embodiment.Sorting device as shown in Figure 1B
100, in the first embodiment, sorting device 100 picks dress comprising one first carrying platform 15, one second carrying platform 16, one
Set 18 and a control system 17.Picking device 18 includes a mechanical arm, and the chip 10 after cutting includes multiple semiconductor elements
10a is attached on an adhesion coating 12, and is placed on the first carrying platform 15, picks device 18 for the semiconductor element of sorting area
Part 10a is transferred to the second carrying platform 16 from the first carrying platform 15, and one second be attached on the second carrying platform 16 is viscous
Layer 12 ', wherein the first adhesion coating 12 and the second adhesion coating 12 ' can be a blue film.Control system 17 is the first carrying of electrical connection
Platform 15, the second carrying platform 16 and device 18 is picked, can classify according to the specification of semiconductor element 10a, control and pick device
18, the multiple semiconductor element 10a of sorting area are transferred to the second carrying platform 16 from the first carrying platform 15, wherein second holds
Carrying platform 16 may include multiple carrying platforms and multiple second adhesion coatings, can be by different off-sorting stations when there is multiple sorting areas
The semiconductor element 10a in domain is transferred on different carrying platforms.
Fig. 1 C is that tipping arrangement 200 used in operation is overturn in first embodiment.As shown in Figure 1 C, tipping arrangement 200
Include a substrate 20；One heater 28 is located in substrate；One first carrying platform 25 is located on heater；An and pressurizer 29
Above substrate 20, wherein pressurizer 29 is also located in air bag comprising an air bag 27 and a cushion 27a.Overturn operation
The first carrying platform 25 on be provided with the first adhesion coating 12, (adhere and carry sorting operation it is complete after remaining multiple semiconductors
Element 10a, that is, overturn the semiconductor element 10a in region.One second adhesion coating 12 ' is set on the second carrying platform 26,
Multiple semiconductor element 10as of the bonding plane of second adhesion coating 12 ' towards the first adhesion coating 12 and overturning region, then via pressurization
The pressure of air bag 27 of device 29 closely pastes the second adhesion coating 12 ' and semiconductor element 10a, finally adds again via heater 28
Heat, so that second adhesion coating 12 ' and multiple semiconductor element 10a patch cementation is fixed.Then to reduce semiconductor element 10a and first
The method that power is attached between adhesion coating 12, reduces between specification area position semiconductor element 10a and the first adhesion coating 12 to be removed
Attach power.Method includes to be coated with to go peptizing agent (not shown), example on the first adhesion coating 12 of specification area position to be removed
Such as acetone, when acetone infiltrates into the attaching face of first adhesion coating 12 and multiple semiconductor element 10a, multiple semiconductor elements
The attaching power of 10a and the first adhesion coating 12 weakens, then with automatic film tearing equipment (not shown) or is torn by hand the first adhesion coating 12
The second adhesion coating 12 ' is stayed in multiple semiconductor element 10a of the second adhesion coating 12 ', the region to be sorted of applied with acetone, is not coated with
The remaining multiple semiconductor element 10a of the specification area of cloth acetone are then still pasted on the first adhesion coating 12 after tearing, complete
At a subseries, if there are multiple overturning regions, implement repeatedly for several times, until all rollovers region is all attached to another adhesion
After layer, that is, complete whole overturning operations.It reduces semiconductor element and interlayer of adhering attaches the method for power in addition to coating above-mentioned
Remove photoresist solvent method, can also pass through the methods of irradiation UV light removal adhesion coating viscosity.To irradiate in the method for UV light, the adhesion
The UV indigo plant film that viscosity can reduce after the irradiation of UV light, which can be selected, in layer implements.The advantages of overturning operation is once choose large area
The semiconductor element of specification area, more single sorting operation of rate are fast.The semiconductor element bad for the photoelectric characteristic uniformity
Classification is completed in part, such as blue-ray LED, the overturning operation that can arrange in pairs or groups via sorting operation.
In the first embodiment, specification sorting operations also can allow semiconductor element photoelectric characteristic image identification instrument, use
To recognize the photoelectric characteristic specification of each semiconductor element 10a.In one embodiment, photoelectric characteristic image identification instrument also may include one
Coordinate position function is defined, after the semiconductor element for recognizing multiple and different or identical photoelectric characteristic specification, while analyzing half
The coordinate position of conductor element difference photoelectric characteristic specification, and then define specification area.Wafer-like row as shown in Figure 2 A
Multiple semiconductor elements of column are in the photoelectric characteristic distribution map on a bogey.Multiple semiconductor elements warp of wafer-like arrangement
After the specification sorting operations of photoelectric characteristic, multiple semiconductor elements are defined as multiple specification areas.Specification sorting operations, packet
Containing the sorting device for using photoelectric characteristic test equipment or other light emitting diode photoelectric characteristic image identification instrument, to generate as schemed
The photoelectric characteristic distribution map that 2A is presented.The photoelectric characteristic image identification instrument disclosed in the present embodiment, not divided by color area
Together, different photoelectric characteristics are represented, are defined outside multiple specification areas, while can also show multiple semiconductors according to X-axis and Y axis coordinate
The position of element.In the present embodiment, multiple specification areas as shown in Figure 2 A, this sentences different black and white contrasts and indicates, generation
The LED area of table different capacity, and be defined as: Defect Bin, 1 Bin, Bin 2, Bin 3, Bin more than 4
A specification area.In the present embodiment, Defect Bin is LED failure area, and Bin 1 is 175~180mW, Bin 2
For 181~185mW, Bin 3 be 185~190mW, Bin 4 is 190~195mW.Other than being defined with different capacity, still
Can wavelength basis, brightness, operation the ranges such as voltage or electric current define.
After completing definition, a selected operation is provided, selectes one or more specification area, such as: arbitrarily selected Bin
1, Bin 2, Bin 4 and Defect Bin are as sorting area and Bin 3 as overturning region.It aforementioned sorting area and turns over
Turn the selected reference using actual photoelectric characteristic distribution map as selected location in region.
In one embodiment, after completing definition, a selected operation, selected semiconductor element most classification areas are provided
Domain is overturning region, and the less specification area of semiconductor element granule number is sorting area, for reaching preferred sorting operation
With the cost and efficiency of overturning operation.For convenience of clear explanation, with Fig. 2 B as the schematic diagram of Fig. 2A.As shown in Figure 2 B, include
Defect Bin, 1 Bin, Bin 2, Bin3 and Bin 4 multiple specification areas, wherein Bin 1 is the most classification of number
Region, therefore it is chosen to be overturning region；Bin 2, Bin 3, Bin 4 and Defect Bin are chosen to be sorting area.
In one embodiment, after completing definition, a selected operation is provided, multiple sorting areas is selected and makes multiple overturnings
Region is not adjacent to each other, and multiple semiconductor elements of sorting area are then first picked out with sorting operation, so that multiple Flip Zones
Domain is not adjacent to each other, then carries out overturning operation respectively for individual overturning regions, can not be recognized with solving tradition overturning operation
The defect on interregional boundary.It can refer to and select non-adjacent Bin 1 and Bin 3 shown in Fig. 2 B as overturning region, remaining Bin
2, Bin 4 and DefectBin is sorting area.Bin 2, Bin 4 and Defect Bin first respectively via sorting operation by these
After the semiconductor element of specification area is chosen, Bin 1 and Bin 3 can be distinguished because of the space that sorting area leaves via estimation mode
Know the boundary of Bin 1 and Bin 3 out, then Bin 1 and Bin 3 is chosen into arrangement to different bearer device respectively to overturn operation
On.
In another embodiment, the boundary of each specification area is defined with Line 1, Line 2 and 3 separator bar of Line
It.With reference to shown in Fig. 2 B, selecting 1~Bin of Bin 4 is overturning region, is selected adjacent positioned at 3 separator bar of Line1~Line
Multiple semiconductor elements are that sorting area leaves space between multiple overturning regions, can make each overturning after completing sorting operation
It is interregional not adjacent to each other.
Fig. 2 C be one embodiment of the invention classification process and selection after arrange schematic diagram.In the present embodiment,
As shown in Figure 2 C, multiple semiconductor elements of wafer-like arrangement are carried on the first bogey 22, and first step is according to front reality
Method described in example is applied, 1~6 specification area of Bin is defined as.Then the specification area Bin of most semiconductor elements is selected
1 is used as overturning region and other specification areas Bin 2~6 for sorting area, and the data that will be chosen to be sorting area input
Sorting device, such as: 176~180mW, 181~185mW, 186~190mW, 191~195mW, 196~200mW and 201~
The brightness data of the Bin such as 205mW 2~6.Multiple semiconductor elements on first bogey 22 are put into sorting and set by second step
Standby, sorting device carries out multiple sorting operations according to being previously entered sorting area data.Third step is made via multiple sortings
After industry, the semiconductor element of sorting area Bin 2~6 is chosen via sorting operation onto multiple second bogeys 23 respectively,
The semiconductor element that remaining specification area Bin 1 namely overturns region then stays on the first bogey 22.Four steps
The semiconductor element for overturning region Bin 1 is put into tipping arrangement and carries out overturning operation.After 5th step is via overturning operation, turn over
The semiconductor element for turning region Bin 1 is reversed selection to third bogey 24 from the first bogey 22.Flip Zone
The semiconductor element of domain Bin 1 is arranged on third bogey 24 according to original overturning the irregular of region, sorting area Bin
2~6 semiconductor element when sorting operation according to rectangular sequential on the second bogey 23, by multiple semiconductor elements
It send together with third bogey 24 to storehouse and stores or deliver to customer.In another embodiment, overturning region Bin 1 is through overturning
After operation, the spread geometry on third bogey 24 can be irregular or distribution shape；Sorting area Bin 2~6 is through dividing
After picking operation, the spread geometry on the second bogey 23 can be rectangular or round.
Fig. 2 D be one embodiment of the invention classification process and selection after arrange schematic diagram.In the present embodiment,
As shown in Figure 2 D, multiple semiconductor elements of wafer-like arrangement first are carried on the first bogey 22, according to preceding embodiment
The method is defined as 1~3 specification area of Bin.Then specification area Bin 1, Bin 2 are selected, Bin 3 is three and turns over
Turn region, and positioned at Line 1, Line 2 and 3 separator bar of Line adjacent multiple semiconductor elements is three sorting areas
Bin 4, Bin 5 and Bin 6, and sorting area data are inputted in sorting device.Semiconductor element is put by second step
One sorting device carries out sorting operation.After third step is via multiple sorting operations, it is located at Line 1, Line 2 and Line
Sorting area Bin 4, Bin 5 and the Bin6 of the adjacent multiple semiconductor elements of 3 separator bars are respectively via sorting operation batch
Squarely is arranged on selection to multiple second bogeys 23, also there are remaining multiple Flip Zones on the first bogey 22 at this time
Domain Bin 1, Bin 2 and Bin 3.Remaining multiple overturning region Bin 1, Bin 2 and Bin 3 are put into one by four steps
Tipping arrangement is sequentially overturn operation three times, and batch, which is posted, to be attached on multiple third bogeys 24.5th step is via turning over
After transferring to industry, multiple overturning region Bin 1, Bin 2 and 3 semiconductor element of Bin are arranged in bogey according to original respectively
Irregular transposition on 22 is stored or is delivered to customer on bogey 24, finally sending respectively to storehouse.In another implementation
In example, after overturning operation, multiple overturning region Bin 1, Bin 2 and 3 semiconductor element of Bin are in the row on bogey
Column shape can be irregular or distribution shape；Line 1, Line 2 and the adjacent multiple semiconductor elements of 3 separator bar of Line
It in the spread geometry on bogey can be rectangular or round after sorting area Bin4, Bin 5 and the sorted operation of Bin 6.
Each embodiment cited by the present invention is only to illustrate the present invention, is not used to limit the scope of the present invention.It is any
People's any modification apparent easy to know made for the present invention or change are without departure from spirit and scope of the invention.
Claims (13)
1. a kind of semiconductor element classification method, includes:
Defining multiple semiconductor elements on a bogey is multiple specification areas；
A selected operation is provided, selecting one of multiple specification area specification area is one first sorting area；
One sorting operation is provided, the one or more semiconductor elements for first sorting area being attached on the bogey are taken out
Part；And
One overturning operation is provided, take out be attached to one of another specification area of multiple specification area on the bogey or
Multiple semiconductor elements.
2. semiconductor element classification method as described in claim 1, wherein the selected operation also includes selected one first overturning
Region, wherein the first overturning region includes another specification area in the overturning operation.
3. semiconductor element classification method as described in claim 1, wherein this definition mode includes according to multiple semiconductor
The photoelectric characteristic of element is classified.
4. semiconductor element classification method as claimed in claim 3, also comprising providing a photoelectric characteristic image identification instrument, identification
The photoelectric characteristic of multiple semiconductor element.
5. semiconductor element classification method as claimed in claim 3, wherein the photoelectric characteristic includes brightness, emission wavelength, behaviour
Make voltage, electric current or power.
6. semiconductor element classification method as claimed in claim 2, wherein the selected operation includes to select multiple sorting areas
Comprising first sorting area, and selecting multiple overturning regions includes the first overturning region, so that multiple overturning region
It is not adjacent to each other.
7. the step of semiconductor element classification method as claimed in claim 6, wherein this selectes multiple sorting areas, is comprising fixed
The boundary in any two multiple overturning regions of justice is a separator bar, and selecting the adjacent multiple semiconductor elements of the separator bar is that this is more
One of a sorting area.
8. semiconductor element classification method as claimed in claim 2, wherein selecting the specification area in the first overturning region
Include most multiple semiconductor elements.
9. semiconductor element classification method as described in claim 1, wherein the sorting operation includes to use a sorting device will
One or more semiconductor elements of first sorting area, which are posted, to be attached on one second bogey, and wherein this is posted attached side
Method includes heating, pressurization or irradiation.
10. semiconductor element classification method as claimed in claim 2, wherein the overturning operation includes to use a tipping arrangement will
One or more semiconductor elements in the first overturning region, which are posted, to be attached on a third bogey.
11. semiconductor element classification method as claimed in claim 9, wherein one or more semiconductors after the sorting operation
Element includes rectangular or round in the spread geometry on second bogey.
12. semiconductor element classification method as claimed in claim 10, wherein the post-job one or more of the overturning is partly led
Volume elements part includes irregular or distribution shape in the spread geometry on the third bogey.
13. a kind of semiconductor element classification method, includes:
One bogey is provided, includes more than one first a semiconductor elements and more than one second a semiconductor elements on the bogey
Part；
A selected operation is provided, selecting more than first a semiconductor element on the bogey is a sorting area；
One sorting operation is provided, the one or more semiconductor elements for the sorting area being attached on the bogey are taken out；
And
One overturning operation is provided, more than the second a semiconductor element being attached on the bogey is taken out.
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| CN201510336366.0A CN106311625B (en) | 2015-06-17 | 2015-06-17 | Semiconductor element classification method |
| CN201910063112.4A CN110038811B (en) | 2015-06-17 | 2015-06-17 | Semiconductor element classification method |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107321639A (en) * | 2017-05-27 | 2017-11-07 | 华灿光电（浙江）有限公司 | A kind of screening technique of light-emitting diode chip for backlight unit |
| CN107639043B (en) * | 2017-09-26 | 2020-06-09 | 武汉华星光电技术有限公司 | Panel classification moves and carries device |
| JP2019066399A (en) * | 2017-10-04 | 2019-04-25 | 三菱電機株式会社 | Semiconductor device classification system and semiconductor device |
| CN109279312B (en) * | 2018-11-27 | 2024-02-20 | 深圳市宇道机电技术有限公司 | Automatic film tearing equipment |
| CN114669496A (en) * | 2022-04-24 | 2022-06-28 | 江西兆驰半导体有限公司 | LED chip sorting method |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101210888A (en) * | 2006-12-29 | 2008-07-02 | 斯尔瑞恩公司 | Wafer inspection machine and method |
| CN101234383A (en) * | 2007-02-01 | 2008-08-06 | Qmc株式会社 | The sorting apparatus for semiconductor chip |
| CN101327483A (en) * | 2007-06-20 | 2008-12-24 | 京元电子股份有限公司 | Device and method for classifying chips |
| CN101987322A (en) * | 2009-08-07 | 2011-03-23 | 晶元光电股份有限公司 | Chip classification device and chip classification method |
| CN202028558U (en) * | 2011-01-26 | 2011-11-09 | 梭特科技股份有限公司 | Parallel automatic classifying picking mechanism |
| CN102790001A (en) * | 2011-05-18 | 2012-11-21 | 夏普株式会社 | Chip sorting device and chip sorting method |
| CN103143507A (en) * | 2013-02-27 | 2013-06-12 | 武汉电信器件有限公司 | Screening method of photodiode chips |
| TWI417967B (en) * | 2009-11-02 | 2013-12-01 | Chroma Ate Inc | A method for marking a grain bearing tray, a sorting machine and a characteristic mark |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6507800B1 (en) * | 2000-03-13 | 2003-01-14 | Promos Technologies, Inc. | Method for testing semiconductor wafers |
| JP4038356B2 (en) * | 2001-04-10 | 2008-01-23 | 株式会社日立製作所 | Defect data analysis method and apparatus, and review system |
| JP4931710B2 (en) * | 2007-06-29 | 2012-05-16 | 株式会社リコー | Non-defective chip classification method on wafer, chip quality determination method using the same, chip classification program, chip quality determination program, marking mechanism, and semiconductor device manufacturing method |
| US7983859B2 (en) * | 2007-09-26 | 2011-07-19 | Kabushiki Kaisha Toshiba | System and method for analyzing defects on a wafer |
| TWI389244B (en) * | 2008-10-17 | 2013-03-11 | Wecon Automation Co Ltd | Model Picker Method |
| TWI488250B (en) * | 2009-07-23 | 2015-06-11 | Epistar Corp | Chip sorting apparatus |
| JP2011187836A (en) * | 2010-03-10 | 2011-09-22 | Renesas Electronics Corp | Control method of semiconductor manufacturing apparatus and control system |
| US9202763B2 (en) * | 2013-01-16 | 2015-12-01 | Kabushiki Kaisha Toshiba | Defect pattern evaluation method, defect pattern evaluation apparatus, and recording media |
-
2015
- 2015-06-17 CN CN201510336366.0A patent/CN106311625B/en active Active
- 2015-06-17 CN CN201910063112.4A patent/CN110038811B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101210888A (en) * | 2006-12-29 | 2008-07-02 | 斯尔瑞恩公司 | Wafer inspection machine and method |
| CN101234383A (en) * | 2007-02-01 | 2008-08-06 | Qmc株式会社 | The sorting apparatus for semiconductor chip |
| CN101327483A (en) * | 2007-06-20 | 2008-12-24 | 京元电子股份有限公司 | Device and method for classifying chips |
| CN101987322A (en) * | 2009-08-07 | 2011-03-23 | 晶元光电股份有限公司 | Chip classification device and chip classification method |
| TWI417967B (en) * | 2009-11-02 | 2013-12-01 | Chroma Ate Inc | A method for marking a grain bearing tray, a sorting machine and a characteristic mark |
| CN202028558U (en) * | 2011-01-26 | 2011-11-09 | 梭特科技股份有限公司 | Parallel automatic classifying picking mechanism |
| CN102790001A (en) * | 2011-05-18 | 2012-11-21 | 夏普株式会社 | Chip sorting device and chip sorting method |
| CN103143507A (en) * | 2013-02-27 | 2013-06-12 | 武汉电信器件有限公司 | Screening method of photodiode chips |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110038811A (en) | 2019-07-23 |
| CN106311625A (en) | 2017-01-11 |
| CN110038811B (en) | 2021-10-26 |
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