CN106298689A - 封装结构 - Google Patents
封装结构 Download PDFInfo
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- CN106298689A CN106298689A CN201510282494.1A CN201510282494A CN106298689A CN 106298689 A CN106298689 A CN 106298689A CN 201510282494 A CN201510282494 A CN 201510282494A CN 106298689 A CN106298689 A CN 106298689A
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- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
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Classifications
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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Abstract
本公开关于一种封装结构,包含:基板,其中基板的第一侧面上设置至少一电子器件;壳体,设置于第一侧面上而覆盖第一侧面,且具有容置空间,容置空间容置电子器件;至少一柱体,柱体由壳体的内侧顶面朝容置空间的方向所延伸;以及至少一弹性体,位于基板及柱体之间,用以接收柱体所传来的压力,并将压力传递至基板上;其中弹性体的弹性模量小于1000Mpa。本公开的封装结构,可均匀柱体提供的压力,避免损害封装结构的内部元件,提高基板空间利用率以及降低成本。
Description
技术领域
本发明有关于一种封装结构,尤指一种具有弹性体,以凭借弹性体接收柱体所传来的压力,并将压力传递至基板上的封装结构。
背景技术
近年来随着科技的进步,各类电子产品逐渐朝向高密度、高性能以及轻、薄、短、小的趋势发展,因此电子产品的内部电路也朝模块化发展,以使许多功能整合在一电路模块中。以常见的电路模块例如功率模块(power module)为例,其包括例如直流-直流转换器(DC to DCconverter)、直流-交流转换器(DC to AC converter)或交流-直流转换器(AC to DC converter)等,且通常将有源器件及无源器件等电子器件整合为功率模块,进而将功率模块安装于系统电路板上。
请参阅图1,其为传统功率模块的封装结构的结构示意图。如图1所示,传统功率模块的封装结构1主要结构为于一基板10的一第一侧面100上设置有源器件(未图示)、无源器件(未图示)及用来对外连接的端子11(Pin),其中有源器件、无源器件及端子11利用焊锡(solder)焊接在基板10上,此外,有源器件、无源器件及端子11之间可利用引线键合(wire bond)技术而彼此以一键合线连接,借此形成功率模块,接着,于基板10的第一侧面100上覆盖一壳体12,壳体12完全包覆有源器件、无源器件,而壳体上12具有至少一孔洞,用以供对应的端子11穿设而使端子11外露于壳体12,借此功率模块便完成封装而构成封装结构1,且封装结构1可凭借外露于壳体的端子而插设于印刷电路板上。
另外,壳体12更具有为刚性结构的至少一柱体121,是设置于壳体12上并朝基板10的第一侧面100所延伸,其用以当壳体12覆盖基板10的第一侧面100时,与第一侧面100相接触抵顶而施加压力于第一侧面100上,使基板10在特殊外力的影响下,例如施加于封装结构1的一锁固力而使封装结构1以锁固方式与其它部件组接等,基板10仍可维持平坦结构而不会有部分区域例如中间区域,因外力影响而发生朝壳体12的方向凹陷的情况,如此一来,当封装结构1与其它部件组接时,例如设置一散热元件于基板10相对于第一侧面100的一第二侧面101上,以加强封装结构1的散热效率时,基板10便可凭借柱体121所施加的压力而与散热元件紧密接触,以保持良好的散热效率。
虽然凭借柱体121直接施加压力于基板10的第一侧面100上确实可使基板10维持平坦结构,然而因柱体121实际上为较硬的刚性结构,故当柱体121与基板10相接触抵顶时,可能导致基板10损坏。此外,为了确保柱体121在壳体12覆盖基板10的第一侧面100上时可确实与第一侧面100相接触抵顶,故柱体100的尺寸必需精准要求,换言之,即柱体121的加工精密度较高,如此一来,将使得封装结构1的制成不易。
再者,虽然当壳体10上具有多个柱体121时,便可凭借多个柱体121而更均匀地施加压力于基板10上,然而由于多个柱体121实际上将占据基板10上较多空间,导致基板10上的空间利用率不佳,进而局限电子器件的元件密度,虽然有部分传统的封装结构为了提升基板的空间利用率来改善电子器件的元件密度,将柱体改为与基板上的电子器件(例如有源器件及/或无源器件)的顶面相抵顶而施加压力,或是将柱体改为与设置在电子器件的顶面并与电子器件的电极连接的键合线相抵顶而施加压力,使柱体以间接方式施加压力于基板上,然而由于柱体为较硬的刚性结构,又电子器件及键合线的结构皆较为脆弱,故柱体与电子器件或与键合线之间的接触抵顶将可能导致电子器件或键合线损坏,使得封装结构内的功率模块无法正常运作。
因此,如何发展一种可改善上述现有技术缺陷的封装结构,实为相关技术领域者目前所迫切需要解决的问题。
发明内容
本发明的主目的为提供一种封装结构,其具有弹性体,该弹性体位于柱体及基板之间,且接收柱体所传来的压力,并将压力传递至基板上,以解决传统封装结构因柱体直接施加压力于基板上、电子器件上或键合线上,导致基板、电子器件或键合线易损坏,以及柱体的加工精密度较高而制成不易等缺陷。
为达上述目的,本发明的一实施方式为提供一种封装结构,包含:一基板,其中基板的第一侧面上设置至少一电子器件;一壳体,设置于第一侧面上而覆盖第一侧面,且具有容置空间,容置空间容置电子器件;至少一柱体,柱体由壳体的一内侧顶面朝容置空间的方向所延伸;以及至少一弹性体,位于基板及柱体之间,用以接收柱体所传来的压力,并将压力传递至基板上;其中弹性体的弹性模量小于1000Mpa。
根据本发明一实施方式,该弹性体的弹性模量10Mpa以下。
根据本发明一实施方式,该柱体组接于该壳体的该内侧面上。
根据本发明一实施方式,该柱体与该壳体一体成形。
根据本发明一实施方式,该弹性体的一顶面与该柱体接触而抵顶,该弹性体的一底面与该基板的该第一侧面上接触而抵顶。
根据本发明一实施方式,该封装结构更具有至少一端子,该端子的一第一端设置于该基板的该第一侧面上,该端子的一第二端穿设该壳体并部分外露于该壳体。
根据本发明一实施方式,该弹性体的一顶面与该柱体接触而抵顶,该弹性体的一底面与该第一端接触而抵顶。
根据本发明一实施方式,该电子器件由一有源器件或一无源器件所构成。
根据本发明一实施方式,当该电子器件为该有源器件时,该弹性体的一顶面与该柱体接触而抵顶,该弹性体的一底面与该有源器件的一顶面接触而抵顶。
根据本发明一实施方式,该弹性体的该底面与该有源器件的该顶面相接触的面积小于该有源器件的该顶面的面积。
根据本发明一实施方式,该弹性体的该底面与该有源器件的该顶面相接触的面积大于或等于一平方毫米,小于或等于四十五平方毫米。
根据本发明一实施方式,该电子器件的一电极与一键合线的部分线段接触,且该电子器件的一顶面上具有一键合区,该键合区为该电极与该键合线接触的区域。
根据本发明一实施方式,该弹性体的一顶面与该柱体接触而抵顶,该弹性体的一底面与该键合区上的该键合线接触而抵顶。
根据本发明一实施方式,依据该弹性体的该底面所接触的材料不同选用不同弹性模量的该弹性体。
根据本发明一实施方式,该弹性体的水平截面形状为圆形、椭圆、四边形、梯形、六边形或不规则形状。
根据本发明一实施方式,该弹性体的垂直截面形状为球形、四边形、可供该柱体定位设置的顶面凹陷形状或不规则形状。
根据本发明一实施方式,该弹性体包含设置于相对上方的一第一弹性部件及设置于相对下方的一第二弹性部件,且该第一弹性部件的弹性模量不同于该第二弹性部件的弹性模量。
根据本发明一实施方式,该弹性体的形成方式是于该封装结构内植入一弹性材料或预制成型。
根据本发明一实施方式,该弹性体的形成方式为喷雾形成或旋涂形成而构成一膜状弹性体。
根据本发明一实施方式,该弹性体先设置于该基板上或先设置于柱体上。
根据本发明一实施方式,该基板的该第一侧面上具有至少一定位孔,该定位孔容置该弹性体,并供该柱体设置而对该柱体进行定位,该柱体接触抵顶该弹性体,使该弹性体变形而填充在该柱体和该定位孔之间的一间隙内。
根据本发明一实施方式,该基板具有构成该第一侧面的一第一导电层,且该第一导电层具有至少一绝缘沟槽,该绝缘沟槽将该第一导电层分隔成多个彼此独立而相互绝缘的导电图形,而该弹性体设置于该绝缘沟槽内并与该柱体相接触而抵顶,且该弹性体由绝缘材质所构成。
根据本发明一实施方式,该柱体为导电材质所构成。
根据本发明一实施方式,该弹性体具有导电特性,且该弹性体的电阻率小于1欧姆·米。
根据本发明一实施方式,该弹性体具有导热特性,且该弹性体的导热系数大于0.5W/m·K。
相比于现有技术,本发明所提供实施例在于,提供一种封装结构,其具有弹性体,且将弹性体设置于柱体及柱体欲施加压力于基板上的位置之间,使柱体所提供的压力凭借弹性体传送至基板上,如此一来,便可凭借弹性体的弹性特性而减少柱体因加工精密度误差所带来的压力不均匀性,使柱体的加工精密度要求降低而封装结构的制成也较为简单,且因本发明的封装结构的柱体凭借弹性体而间接地施加压力于基板上、键合线上、电子器件上或端子上,故可避免柱体在施加压力的过程中造成基板、键合线、电子器件或端子损坏。另外,由于本发明的封装结构的柱体凭借弹性体便可施加压力于键合线上、电子器件上或端子上,故本发明的封装结构可提升基板上的空间利用率,进而改善电子器件于基板上的元件密度。
附图说明
图1为传统功率模块的封装结构的结构示意图。
图2为本发明第一实施例的封装结构的结构示意图。
图3为图1所示的封装结构的弹性体的各种可能实施方式的水平截面形状示意图。
图4为图1所示的封装结构的弹性体的各种可能实施方式的垂直截面形状示意图。
图5为本发明第二实施例的封装结构的部分结构示意图。
图6A为本发明第三实施例的封装结构的部分结构示意图。
图6B为图6A所示的封装结构设置弹性体时的部分结构示意图。
图6C为图6B所示的封装结构在柱体接触抵顶弹性体时的部分结构示意图。
图7为本发明第四实施例的封装结构的部分结构示意图。
图8为本发明第五实施例的封装结构的部分结构示意图。
具体实施方式
体现本发明特征与优点的一些典型实施例将在后段的说明中详细叙述。应理解的是本发明能够在不同的方式上具有各种的变化,其皆不脱离本发明的范围,且其中的说明及图示在本质上是当作说明之用,而非架构于限制本发明。
请参阅图2,其为本发明第一实施例的封装结构的结构示意图。如图2所示,本实施例的封装结构2具有一基板3、一壳体4、至少一柱体5及至少一弹性体6。基板3具有一第一侧面30及一第二侧面31,其中第一侧面30上可设置至少一电子器件7。壳体4设置于第一侧面30上而覆盖第一侧面30,且具有一容置空间40,用以容置电子器件7。
柱体5的第一端设置于壳体4的一内侧面41上,柱体5的第二端则朝基板3的第一侧面30的方向延伸。弹性体6的弹性模量实质上可为但不限于小于1000Mpa,且弹性体6位于基板3及柱体5之间,其可接收由柱体5所传来的压力,并以直接或间接方式将压力传递至基板3上。
另外,如图2所示,基板3的一侧可覆盖有第一导电层36,基板3的另一侧则覆盖有第二导电层37,其中第一导电层36部份构成基板3的第一侧面30,第二导电层37部份构成基板3的第二侧面31,且第一导电层36及第二导电层37可分别为但不限于由铜所构成。
再者,基板3可为直接覆铜(Direct Bonding Copper;DBC)基板,但不以此为限,也可为直接覆铝(Direct Bonding Aluminum;DBA)基板、低温共烧陶瓷(Low-Temperature Co-fired Ceramic;LTCC)基板、直接电镀铜(Direct Plated Copper;DPC)基板、金属绝缘(Insulated Metal Substrate;IMS)基板、或印刷电路板(PrintedCircuit Board;PCB)等。此外,基板3的第二侧面31上可设置一散热元件80,例如散热鳍片,以凭借散热元件80加强封装结构2的散热效率。另外,基板3的第二侧面31及散热元件80之间可设置一导热物质81,例如导热硅脂(thermal grease)等,以提高基板3和散热元件80之间的热传导效率。更甚者,封装结构2的壳体4可具有至少一锁固孔42,用以供一螺丝82经由壳体4的一外侧面43穿设锁固孔42,并部分突出壳体4的内侧面41,使螺丝82可部分锁固于散热元件80上,借此封装结构2便可利用螺丝82而固设于散热元件80上,此时螺丝82的锁固力实际上构成柱体5提供给弹性体6的压力。
于本实施例中,电子器件7可为有源器件,例如功率半导体芯片等,或为无源器件,例如电阻等,并利用焊锡(未图示)而焊接在第一侧面30上。此外,电子器件7的一电极71(当电子器件7例如为双极型晶体管时,电极71可为基极、发射极或集电极)可与一键合线83的部分线段接触,且电子器件7的顶面70上可具有一键合区S,该键合区S为电子器件7的电极71与键合线83接触的区域,而每一电子器件7的电极71可凭借键合区S上的键合线83而与其它电子器件7的电极71导接。
另外,基板3的第一侧面30上更具有至少一端子32,其中端子32的一第一端320可以例如焊接的方式固设于第一侧面30上,端子32的一第二端321则穿设壳体4上的一孔洞而位于封装结构2的外部,使封装结构2可利用端子32的第二端321而插设于印刷电路板上。当然,键合线83的部分线段也可与基板3上的端子32或其他导接线等电连接。
于一些实施例中,柱体5可与壳体4为相互独立的元件,而柱体5的第一端可以组接或粘胶等方式固设于壳体4的内侧面41上,但不以此为限,于其它实施例中,柱体5也可与壳体4一体成形。
此外,弹性体6的个数实际上对应于柱体5的个数。再者,弹性体6位于柱体5及基板3之间,例如设置于柱体5及基板3的第一侧面30之间、设置于柱体5及端子32的第一端320之间、设置于柱体5及位于键合区S上的键合线83之间及/或设置于柱体5及电子器件7的顶面70之间。当弹性体6设置于柱体5及基板3的第一侧面30之间时,例如图2所示的第一弹性体61,第一弹性体61的一顶面与柱体5相接触而抵顶,第一弹性体61的一底面与第一侧面30相接触而抵顶,此时第一弹性体61将柱体5所传来的压力直接传送至第一侧面30上。当弹性体6设置于柱体5及端子32的第一端320之间时,例如图2所示的第二弹性体62,第二弹性体62的一顶面与柱体5相接触而抵顶,第二弹性体62的一底面与端子32的第一端320相接触而抵顶,此时第二弹性体62将柱体5所传来的压力间接地经由端子32传送至第一侧面30上。当弹性体6设置于柱体5及位于键合区S上的键合线83之间时,例如图2所示的第三弹性体63,第三弹性体63的一顶面与柱体5相接触而抵顶,第三弹性体63的一底面与键合区S上的键合线83相接触而抵顶,此时第三弹性体63将柱体5所传来的压力间接地经由键合线83及电子器件7传送至第一侧面30上。当弹性体6设置于柱体5及电子器件7的顶面70之间时,例如图2所示的第四弹性体64,第四弹性体64的一顶面与柱体5相接触而抵顶,第四弹性体64的一底面与电子器件7的顶面70相接触而抵顶,此时第四弹性体64将柱体5所传来的压力间接地经由电子器件7传送至第一侧面30上。更甚者,于其它实施例中,基板3的侧面30、电子器件7的顶面70、键合线83的表面及/或端子32的第一端320可具有一涂层(例如涂覆的环氧树脂保护层),以保护基板3、电子器件7、键合线83及端子32,故弹性体6也对应地设置于柱体5及基板3的侧面30上的涂层之间、柱体5及电子器件7的顶面70上的涂层之间、设置于柱体5及位于键合区S上的键合线83的涂层之间及/或设置于柱体5及端子32的第一端320上的涂层之间。
由上可知,本发明的封装结构2实际上设置弹性体6于柱体5及柱体5欲施加压力于基板3上的位置之间,使柱体5所提供的压力凭借弹性体6传送至基板3上,如此一来,凭借弹性体6的弹性特性,可减少柱体5因加工精密度误差所带来的压力不均匀性,进而使柱体5的加工精密度要求降低而使封装结构2的制成也较为简单,更甚者,由于本发明的封装结构2的柱体5凭借弹性体5而间接地施加压力于基板3上、键合区S的键合线83上、电子器件7的顶面70上或端子32上,故可避免柱体5在施加压力的过程中造成基板3、键合线83、电子器件7或端子32损坏。另外,由于本发明的封装结构2的柱体5可凭借弹性体5而施加压力于键合线83上、电子器件7上或端子32上,基板3的空间利用率提高,进而改善电子器件7于基板3上的元件密度。
于一些实施例中,弹性体6的形成方式可为先于封装结构2内植入一弹性材料或是预制成型,也可为喷雾形成或旋涂形成而构成一膜状弹性体。另外,弹性体6可先设置于基板3的第一侧面30上,再与柱体5相接触抵顶,或先设置于柱体5上,再与基板3的第一侧面30相接触抵顶。再者,弹性体6的构成材料可为但不限于橡胶、硅胶、有机聚合物或碳纳米材料等。于一些实施例中,弹性体6的弹性模量可设置为10Mpa以下。
又当弹性体6设置于柱体5及电子器件7的顶面70之间,而电子器件7为有源器件时,例如图2所示的第四弹性体64,为了确保柱体5的压力可经由第四弹性体64而均匀地施加于电子器件7的顶面70,同时为了避让有源器件上方的键合区S,并避免损伤有源器件的边缘区域,故第四弹性体64的底面与电子器件7的顶面70相接触的面积实际上可小于顶面70的面积,更甚者,第四弹性体64的底面与电子器件7的顶面70相接触的面积以大于或等于一平方毫米,小于或等于四十五平方毫米为佳。
另外,更可依弹性体6的底面所接触的材料不同而选用不同弹性模量的弹性体6,例如图2所示,由于第一弹性体61的底面、第二弹性体62的底面、第三弹性体63的底面及第四弹性体64的底面分别接触不同材料,故第一弹性体61的弹性模量、第二弹性体62的弹性模量、第三弹性体63的弹性模量及第四弹性体64的弹性模量各不相同。
请参阅图3,其为图1所示的封装结构的弹性体的各种可能实施方式的水平截面形状示意图。如图3所示,本发明的弹性体6的水平截面形状可为是圆形(图3所示的(A)方式)、椭圆(图3所示的(B)方式)、四边形(图3所示的(C)方式)、梯形(图3所示的(D)方式)、六边形(图3所示的(E)方式)或各种不规则形状(图3所示的(F)集合方式)。
请参阅图4,其为图1所示的封装结构的弹性体的各种可能实施方式的垂直截面形状示意图。如图4所示,本发明的弹性体6的垂直截面形状可为,但不限于,球形(图4所示的(A)集合方式)、四边形(图4所示的(B)集合方式)或可供柱体5定位设置的顶面凹陷形状(图4所示的(C)方式),但弹性体6的垂直截面形状并不以此为限,也可为各种不规则形状。另外,每一弹性体6的高度可相同于其它弹性体6的高度,但不以此为限,每一弹性体6可依设置区域的不同而有不同的高度。
以下将再进一步说明本发明的封装结构的各种可能变化形式,且下列图示中与图2相同的标号代表结构与功能相似,而不再赘述。请参阅图5,其为本发明第二实施例的封装结构的部分结构示意图。如图5所示,于一些实施例中,由于弹性体6的顶面及底面实际上分别接触不同的材料,故为了使弹性体6提供较佳的弹性效果,弹性体6可包含设置于相对上方且构成顶面的一第一弹性部件65及设置于相对下方且构成底面的一第二弹性部件66,但不限于此,其中第一弹性部件65的弹性模量不同于第二弹性部件66的弹性模量。另外,由图3所示可知,多个柱体5的多个第二端也可接触抵顶同一个弹性体6。
请参阅图6A、图6B、图6C,其中图6A为本发明第三实施例的封装结构的部分结构示意图,图6B为图6A所示的封装结构设置于弹性体时的部分结构示意图,图6C为图6B所示的封装结构在柱体接触抵顶弹性体时的部分结构示意图。如图6A、图6B、图6C所示,于一些实施例中,基板3的第一侧面30更可具有一定位孔33(如图6A),其可利用蚀刻方式形成,该定位孔33容置弹性体6(如图6B),且可容置部份柱体5而对柱体5进行定位(如图6C),当柱体5部分设置于定位孔33时,弹性体5与柱体5及定位孔33相接触,弹性体5变形而填充在柱体5和定位孔33之间的一间隙内。
请参阅图7,其为本发明第四实施例的封装结构的部分结构示意图。如图所示,于一些实施例中,基板3的第一导电层30上更利用蚀刻方式而形成一绝缘沟槽34,绝缘沟槽34将该第一导电层分隔成多个彼此独立而相互绝缘的导电图形35,每一导电图形35可与对应的电子器件的导接区(本图未图示)导接。另外,弹性体6则可设置于绝缘沟槽34内,且为了避免多个导电图形35因与设置于绝缘沟槽34内的弹性体6相接触而导接,弹性体6则可由绝缘材质构成,柱体5则部分设置于绝缘沟槽34内,并与弹性体6相接触而抵顶,而由于本实施例的弹性体6设置于绝缘沟槽34内,而非设置于基板3的第一侧面30上,故弹性体6并不会影响基板3的第一侧面30上的线路元件布局,是以可以减小封装结构2的尺寸。
另外,于一些实施例中,柱体5可由塑胶等绝缘材料所构成,但不以此为限。请参阅图8,其为本发明第五实施例的封装结构的部分结构示意图。如图8所示,于其它实施例中,弹性体6可具有导电特性,例如弹性体6的电阻率可为,但不限于,小于1欧姆·米,而对应于弹性体6具有导电特性,本实施例的封装结构更可具有由导电材质所构成的至少一电路端子,例如图8所示的三个电路端子90,电路端子90设置于基板3的第一侧面30的上方,且邻近于壳体(本图未图示)的内侧顶面,且电路端子90可部分穿设于壳体而与位于封装结构外的其它外部电路电连接,此外,电路端子90更包含具有导电特性的柱体900,导电特性的柱体900可取代例如图2所示的柱体5,柱体900朝容置空间及基板3的第一侧面30所延伸,故当弹性体6的底面与电子器件7的电极71、基板3的第一侧面30、端子32的第一端320及/或键合区S上的键合线83接触而抵顶,且弹性体6的顶面与对应的柱体900相接触而抵顶时,电路端子90便可凭借柱体900及弹性体6而与电子器件7的电极71、基板3、端子32及/或键合区S上的导接线电连接,借此本实施例的封装结构不但可利用柱体900及弹性体6而实现基板的机械固定,同时也直接凭借具导电特性的柱体900及弹性体6而实现了封装结构的内部与外部电路连接,进而可减少焊接电路端子的工艺,提高封装效率。另外上述实施例中,多个电路端子90之间更可利用一绝缘层91来彼此隔离绝缘。
又于其它实施例中,弹性体6可具有导热特性,例如弹性体6的导热系数可为但不限于大于0.5W/m·K,如此一来,封装结构2的电子器件7所产生的热能不但可向下而经由基板3传导至散热元件80,以凭借散热元件80进行散热,也可凭借弹性体6而向上传导,以凭借柱体5及壳体4进行散热。
综上所述,本发明提供一种封装结构,其具有弹性体,且将弹性体设置于柱体及柱体欲施加压力于基板上的位置之间,使柱体所提供的压力凭借弹性体传送至基板上,如此一来,便可凭借弹性体的弹性特性而减少柱体因加工精密度误差所带来的压力不均匀性,使柱体的加工精密度要求降低而封装结构的制成也较为简单,且因本发明的封装结构的柱体凭借弹性体而间接地施加压力于基板上、键合线上、电子器件上或端子上,故可避免柱体在施加压力的过程中造成基板、键合线、电子器件或端子损坏。另外,由于本发明的封装结构的柱体凭借弹性体便可施加压力于较容易损坏的键合线上、电子器件上或端子上,故本发明的封装结构可提升基板上的空间利用率,进而改善电子器件于基板上的元件密度。
本发明得由熟习此技术的人士任施匠思而为诸般修饰,然皆不脱如附权利要求书所欲保护者。
Claims (25)
1.一种封装结构,其特征在于,包含:
一基板,其中该基板的一第一侧面上设置至少一电子器件;
一壳体,设置于该第一侧面上而覆盖该第一侧面,且具有一容置空间,该容置空间容置该电子器件;
至少一柱体,该柱体由该壳体的一内侧顶面朝该容置空间的方向所延伸;以及
至少一弹性体,位于该基板及该柱体之间,用以接收该柱体所传来的一压力,并将该压力传递至该基板上;
其中该弹性体的弹性模量小于1000Mpa。
2.如权利要求1所述的封装结构,其特征在于,该弹性体的弹性模量为10Mpa以下。
3.如权利要求1所述的封装结构,其特征在于,该柱体组接于该壳体的该内侧面上。
4.如权利要求1所述的封装结构,其特征在于,该柱体与该壳体一体成形。
5.如权利要求1所述的封装结构,其特征在于,该弹性体的一顶面与该柱体接触而抵顶,该弹性体的一底面与该基板的该第一侧面上接触而抵顶。
6.如权利要求1所述的封装结构,其特征在于,该封装结构更具有至少一端子,该端子的一第一端设置于该基板的该第一侧面上,该端子的一第二端穿设于该壳体并部分外露于该壳体。
7.如权利要求6所述的封装结构,其特征在于,该弹性体的一顶面与该柱体接触而抵顶,该弹性体的一底面与该第一端接触而抵顶。
8.如权利要求1所述的封装结构,其特征在于,该电子器件由一有源器件或一无源器件所构成。
9.如权利要求8所述的封装结构,其特征在于,当该电子器件为该有源器件时,该弹性体的一顶面与该柱体接触而抵顶,该弹性体的一底面与该有源器件的一顶面接触而抵顶。
10.如权利要求9所述的封装结构,其特征在于,该弹性体的该底面与该有源器件的该顶面相接触的面积小于该有源器件的该顶面的面积。
11.如权利要求10所述的封装结构,其特征在于,该弹性体的该底面与该有源器件的该顶面相接触的面积大于或等于一平方毫米,小于或等于四十五平方毫米。
12.如权利要求1所述的封装结构,其特征在于,该电子器件的一电极与一键合线的部分线段接触,且该电子器件的一顶面上具有一键合区,该键合区为该电极与该键合线接触的区域。
13.如权利要求12所述的封装结构,其特征在于,该弹性体的一顶面与该柱体接触而抵顶,该弹性体的一底面与该键合区上的该键合线接触而抵顶。
14.如权利要求5、7、9或13所述的封装结构,其特征在于,依据该弹性体的该底面所接触的材料不同选用不同弹性模量的该弹性体。
15.如权利要求1所述的封装结构,其特征在于,该弹性体的水平截面形状为圆形、椭圆、四边形、梯形、六边形或不规则形状。
16.如权利要求1所述的封装结构,其特征在于,该弹性体的垂直截面形状为球形、四边形、可供该柱体定位设置的顶面凹陷形状或不规则形状。
17.如权利要求1所述的封装结构,其特征在于,该弹性体包含设置于相对上方的一第一弹性部件及设置于相对下方的一第二弹性部件,且该第一弹性部件的弹性模量不同于该第二弹性部件的弹性模量。
18.如权利要求1所述的封装结构,其特征在于,该弹性体的形成方式是于该封装结构内植入一弹性材料或预制成型。
19.如权利要求1所述的封装结构,其特征在于,该弹性体的形成方式为喷雾形成或旋涂形成而构成一膜状弹性体。
20.如权利要求1所述的封装结构,其特征在于,该弹性体先设置于该基板上或先设置于柱体上。
21.如权利要求1所述的封装结构,其特征在于,该基板的该第一侧面上具有至少一定位孔,该定位孔容置该弹性体,并对该柱体进行定位,该柱体接触抵顶该弹性体,使该弹性体变形而填充在该柱体和该定位孔之间的一间隙内。
22.如权利要求1所述的封装结构,其特征在于,该基板具有构成该第一侧面的一第一导电层,且该第一导电层具有至少一绝缘沟槽,该绝缘沟槽将该第一导电层分隔成多个彼此独立而相互绝缘的导电图形,而该弹性体设置于该绝缘沟槽内并与该柱体相接触而抵顶,且该弹性体由绝缘材质所构成。
23.如权利要求1所述的封装结构,其特征在于,该柱体为导电材质所构成。
24.如权利要求23所述的封装结构,其特征在于,该弹性体具有导电特性,且该弹性体的电阻率小于1欧姆·米。
25.如权利要求1所述的封装结构,其特征在于,该弹性体具有导热特性,且该弹性体的导热系数大于0.5W/m·K。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109326566A (zh) * | 2018-09-18 | 2019-02-12 | 黎庆有 | 一种半导体芯片封装结构及其封装方法 |
CN111599767A (zh) * | 2019-02-20 | 2020-08-28 | 台达电子工业股份有限公司 | 功率模块封装结构 |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
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JP6274196B2 (ja) * | 2015-12-16 | 2018-02-07 | 株式会社オートネットワーク技術研究所 | 電気接続箱 |
EP3340291A1 (en) * | 2016-12-23 | 2018-06-27 | Infineon Technologies AG | Method for procuding an electronic module assembly and electronic module assembly |
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EP3913665A1 (en) * | 2020-05-18 | 2021-11-24 | Infineon Technologies AG | A power semiconductor module and a method for producing a power semiconductor module |
EP3929973B1 (en) * | 2020-06-22 | 2022-10-26 | Infineon Technologies AG | A power semiconductor module and a method for producing a power semiconductor module |
US20240063080A1 (en) * | 2022-04-28 | 2024-02-22 | Hitachi Energy Switzerland Ag | Semiconductor power module and method for manufacturing a semiconductor power module |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60119759A (ja) * | 1983-11-30 | 1985-06-27 | Mitsubishi Electric Corp | 半導体装置 |
JPH03236264A (ja) * | 1990-02-13 | 1991-10-22 | Fujitsu Ltd | 半導体装置 |
JPH04242088A (ja) * | 1991-01-16 | 1992-08-28 | Nec Corp | Icソケット |
US20020027283A1 (en) * | 1998-05-15 | 2002-03-07 | Kabushiki Kaisha Toshiba | Hermetically sealed semiconductor power module and large scale module comprising the same |
WO2003034467A2 (de) * | 2001-10-10 | 2003-04-24 | Europäische Gesellschaft Für Leistungshalbleiter Mbh | Leistungshalbleitermodul |
US6870258B1 (en) * | 2003-06-16 | 2005-03-22 | Advanced Micro Devices | Fixture suitable for use in coupling a lid to a substrate and method |
US20060150751A1 (en) * | 2003-06-10 | 2006-07-13 | Europaische Gesellschaft Fur Leistungshalbleiter Mbh | Power semiconductor module |
CN101071809A (zh) * | 2006-05-09 | 2007-11-14 | 塞米克朗电子有限及两合公司 | 功率半导体模块 |
CN101459164A (zh) * | 2007-10-18 | 2009-06-17 | 英飞凌科技股份公司 | 功率半导体模块 |
JP2010245096A (ja) * | 2009-04-01 | 2010-10-28 | Mitsubishi Electric Corp | 半導体装置 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6979899B2 (en) * | 2003-12-31 | 2005-12-27 | Texas Instruments Incorported | System and method for high performance heat sink for multiple chip devices |
US7268428B2 (en) * | 2005-07-19 | 2007-09-11 | International Business Machines Corporation | Thermal paste containment for semiconductor modules |
US7687920B2 (en) * | 2008-04-11 | 2010-03-30 | Stats Chippac Ltd. | Integrated circuit package-on-package system with central bond wires |
US8354747B1 (en) * | 2010-06-01 | 2013-01-15 | Amkor Technology, Inc | Conductive polymer lid for a sensor package and method therefor |
-
2015
- 2015-05-28 CN CN201510282494.1A patent/CN106298689B/zh active Active
- 2015-08-24 TW TW104127568A patent/TWI614849B/zh active
-
2016
- 2016-03-11 US US15/068,212 patent/US9633919B2/en active Active
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60119759A (ja) * | 1983-11-30 | 1985-06-27 | Mitsubishi Electric Corp | 半導体装置 |
JPH03236264A (ja) * | 1990-02-13 | 1991-10-22 | Fujitsu Ltd | 半導体装置 |
JPH04242088A (ja) * | 1991-01-16 | 1992-08-28 | Nec Corp | Icソケット |
US20020027283A1 (en) * | 1998-05-15 | 2002-03-07 | Kabushiki Kaisha Toshiba | Hermetically sealed semiconductor power module and large scale module comprising the same |
WO2003034467A2 (de) * | 2001-10-10 | 2003-04-24 | Europäische Gesellschaft Für Leistungshalbleiter Mbh | Leistungshalbleitermodul |
US20060150751A1 (en) * | 2003-06-10 | 2006-07-13 | Europaische Gesellschaft Fur Leistungshalbleiter Mbh | Power semiconductor module |
US6870258B1 (en) * | 2003-06-16 | 2005-03-22 | Advanced Micro Devices | Fixture suitable for use in coupling a lid to a substrate and method |
CN101071809A (zh) * | 2006-05-09 | 2007-11-14 | 塞米克朗电子有限及两合公司 | 功率半导体模块 |
CN101459164A (zh) * | 2007-10-18 | 2009-06-17 | 英飞凌科技股份公司 | 功率半导体模块 |
JP2010245096A (ja) * | 2009-04-01 | 2010-10-28 | Mitsubishi Electric Corp | 半導体装置 |
Cited By (3)
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---|---|---|---|---|
CN109326566A (zh) * | 2018-09-18 | 2019-02-12 | 黎庆有 | 一种半导体芯片封装结构及其封装方法 |
CN111599767A (zh) * | 2019-02-20 | 2020-08-28 | 台达电子工业股份有限公司 | 功率模块封装结构 |
CN111599767B (zh) * | 2019-02-20 | 2022-03-11 | 台达电子工业股份有限公司 | 功率模块封装结构 |
Also Published As
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US9633919B2 (en) | 2017-04-25 |
US20160351460A1 (en) | 2016-12-01 |
TWI614849B (zh) | 2018-02-11 |
TW201642404A (zh) | 2016-12-01 |
CN106298689B (zh) | 2018-10-09 |
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