CN106298534A - A kind of VDMOS device and preparation method thereof - Google Patents
A kind of VDMOS device and preparation method thereof Download PDFInfo
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- CN106298534A CN106298534A CN201510312718.9A CN201510312718A CN106298534A CN 106298534 A CN106298534 A CN 106298534A CN 201510312718 A CN201510312718 A CN 201510312718A CN 106298534 A CN106298534 A CN 106298534A
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- 238000002360 preparation method Methods 0.000 title abstract description 3
- 238000002347 injection Methods 0.000 claims abstract description 32
- 239000007924 injection Substances 0.000 claims abstract description 32
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 230000004913 activation Effects 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 41
- 238000004519 manufacturing process Methods 0.000 claims description 18
- 230000008569 process Effects 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 6
- 229910052785 arsenic Inorganic materials 0.000 claims description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical group [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 238000005457 optimization Methods 0.000 abstract 1
- 108091006146 Channels Proteins 0.000 description 14
- 230000008859 change Effects 0.000 description 5
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- 238000002513 implantation Methods 0.000 description 4
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- 238000012986 modification Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 2
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 2
- 210000000746 body region Anatomy 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 229910015900 BF3 Inorganic materials 0.000 description 1
- 208000033999 Device damage Diseases 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
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- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
- H01L21/3223—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering using cavities formed by hydrogen or noble gas ion implantation
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- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a kind of VDMOS device and preparation method thereof, including: on substrate, make epitaxial layer, gate oxide and polycrystalline grid successively；The described epitaxial layer being pointed between adjacent described polycrystalline grid carries out for the first time injecting formation and body district is lightly doped；Forming source region injection region described being lightly doped in body district, the element in described source region injection region has the thick atom attribute than great and easy activation；Carry out driving in, to form channel region for the first time according to the first Preset Time；Dielectric layer deposited also etches formation heavy doping body district and injects window, carry out third time be infused in described in body district in formation heavy doping body district is lightly doped；Carry out second time according to the second Preset Time to drive in, to increase the volume in described heavy doping body district and to guarantee the length of described channel region, in order to the problem solving while optimization EAS ability, other parameters of device to be impacted in prior art.
Description
Technical field
The present invention relates to semiconductor device processing technology field, particularly relate to a kind of VDMOS device and shape thereof
One-tenth method.
Background technology
Plane VDMOS device has a very important parameter to be exactly EAS (pulse avalanche breakdown energy),
The safety value of the transient overshoot voltage that avalanche breakdown energy calibration device can be tolerated, it depends on snowslide and hits
Wear the energy needing to dissipate.Under the applied environment that source electrode and drain electrode can produce bigger due to voltage spikes, it is necessary to
Consider the avalanche energy of device.
The snowslide of general device damages both of which, and cause thermal damage and parasitic triode conducting damage.Parasitic three
Pole pipe conducting damages and refers to that device itself exists a parasitic audion (epitaxial layer-body district-source region), works as device
When part turns off, when the reverse current between source and drain flows through body district, produce pressure drop, if this pressure drop is more than parasitic three
The cut-in voltage of pole pipe, then parasitic triode can be turned on by this reverse current because of the amplification of audion,
Causing out of control, now, grid voltage can not turn off VDMOS.
Prior art is by the overrich done in Shen Ti district or crosses deeply to reduce body district resistance, reaches to prevent parasitism
Triode ON, optimizes the purpose of EAS ability, but deep body offset is close to channel region, and do so can be right
Other parameters of device impact, such as, occur that wealthy threshold voltage (Vth) raises and drain-source breakdown voltage (BVDss)
The problems such as reduction.
Summary of the invention
The embodiment of the present invention provides the manufacture method of a kind of VDMOS device, excellent in order to solve in prior art
Change the problem while EAS ability, other parameters of device impacted.
For achieving the above object, following technical scheme is embodiments provided:
A kind of manufacture method of VDMOS device, including: on substrate, make epitaxial layer, gate oxidation successively
Layer and polycrystalline grid；The described epitaxial layer being pointed between adjacent described polycrystalline grid carries out injecting for the first time
Formation is lightly doped body district；Source region injection region is formed, in described source region injection region described being lightly doped in body district
Element has the thick atom attribute than great and easy activation；Carry out driving in for the first time according to the first Preset Time,
To form channel region；Dielectric layer deposited also etches formation heavy doping body district injection window, carries out third time and injects
Heavy doping body district is formed described being lightly doped in body district；Carry out second time according to the second Preset Time to drive in, with
Increase the volume in described heavy doping body district and guarantee the length of described channel region.
Wherein, described formation polycrystalline grid, particularly as follows: carry out after depositing one layer of polysilicon layer on gate oxide
Etching, cuts through described polysilicon layer and part gate oxide, forms spaced multiple polycrystalline grid.
Described form source region injection region, particularly as follows: inject it in described first time described being lightly doped in body district
After, in the described epitaxial layer between adjacent two described polycrystalline grids, carry out second time inject at the beginning of formation
Stock district；Or, after described first time injects, coating photoresist also etches formation source region injection window,
Carry out second time to inject formation and be separated into two-part source region.
Described dielectric layer deposited also etches formation heavy doping body district injection window, specifically includes: etching is given an account of
Matter layer and described initial source region, distinguish described initial source and be divided into two-part source region.
Further, if form N+ source region, injection element is arsenic；If form P+ source region, inject element
For boron difluoride.
It is preferred that described first Preset Time and described second Preset Time sum are equal to the gentliest mixing
Za Ti district injection process drive in the time.
It is preferred that described second Preset Time is equal to described first Preset Time.
Further, described carry out driving in for the first time according to the first Preset Time, including: when presetting according to first
Between and the first preset temperature, the described body district that is lightly doped is driven in；Described first Preset Time is 60～100
Minute；Described first preset temperature 1100～1200 degrees Celsius.
Wherein, described carry out second time according to the second Preset Time and drive in, including: according to the second Preset Time and
Second preset temperature, drives in described heavy doping Shen Ti district；Described second Preset Time is 60～100 points
Clock；Described second preset temperature is 1100～1200 degrees Celsius.
Manufacture method based on above-mentioned VDMOS device, the embodiment of the present invention also provides for a kind of VDMOS device
Part, described VDMOS device is by the system of the VDMOS device as described in any one of claim 1～9
Obtain as method.
The solution have the advantages that: one side twice injection of employing and the mode driven in have made and be lightly doped
Body district and heavy doping body district, because second time drives in the volume increasing heavy doping body district, and then increase heavy doping
Body district is at the proportion in whole body district, thus reduces the resistivity in body district so that body district resistance reduces；Another
Aspect ensure that the length of device channel region by driving in the control of time to twice, thus is reducing body district electricity
Other electrical parameter is not impacted while resistance.
Accompanying drawing explanation
For the technical scheme being illustrated more clearly that in the embodiment of the present invention, institute in embodiment being described below
The accompanying drawing used is needed to briefly introduce, it should be apparent that, the accompanying drawing in describing below is only the present invention's
Some embodiments, from the point of view of those of ordinary skill in the art, in the premise not paying creative work
Under, it is also possible to other accompanying drawing is obtained according to these accompanying drawings.
Fig. 1 is the VDMOS device manufacture method flow chart that the embodiment of the present invention provides；
Fig. 2 a to Fig. 2 g is that each step of forming method of the VDMOS device that the embodiment of the present invention provides is corresponding
Cross-sectional view；
Fig. 3 a and Fig. 3 b is the another kind of manufacture method of the VDMOS device source region that the embodiment of the present invention provides.
Detailed description of the invention
In order to make the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing to this
Bright it is described in further detail, it is clear that described embodiment is only some embodiments of the present invention,
Rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art are not doing
Go out all other embodiments obtained under creative work premise, broadly fall into the scope of protection of the invention.
The type of quasiconductor is determined by majority carrier in quasiconductor, if majority carrier is hole, is then P
Type, heavily doped for P+ type, lightly doped for P-type；If majority carrier is electronics, then it is N-type,
Heavily doped for N+ type, lightly doped for N-type.
Fig. 1 is an embodiment flow chart of the manufacture method of VDMOS device of the present invention, the present embodiment
Method includes:
Step S101: make epitaxial layer, gate oxide and polycrystalline grid on substrate successively；
Step S102: the described epitaxial layer being pointed between adjacent described polycrystalline grid carries out injecting for the first time
Formation is lightly doped body district；
Step S103: form source region injection region, the unit in described source region injection region described being lightly doped in body district
Element has the thick atom attribute than great and easy activation；
Step S104: carry out driving in, to form channel region for the first time according to the first Preset Time；
Step S105: dielectric layer deposited also etches formation heavy doping body district injection window, carries out third time and injects
Heavy doping body district is formed described being lightly doped in body district；
Step S106: carry out second time according to the second Preset Time and drive in, to increase described heavy doping body district
Volume also guarantees the length of described channel region.
Wherein, described formation polycrystalline grid, particularly as follows: it is laggard to deposit one layer of polysilicon layer on gate oxide
Row etching, cuts through described polysilicon layer and part gate oxide, forms spaced multiple polycrystalline grid.
On the one hand the effect of part gate oxide is because source region is injected to thick atom As or BF2, it is necessary to by oxygen
Change layer and etch away a part, reduce the stop that source region is injected ion；On the other hand epitaxial layer table can be protected
Face, reduces the damage in injection process brought epi-layer surface.
Described form source region injection region have the two kinds of forming methods, a kind of method to be described being lightly doped in body district:
After described first time injects, enter in the described epitaxial layer between adjacent two described polycrystalline grids
Row second time is injected and is formed initial source region, then is divided into two parts by cutting through initial source region, forms source
District；Another kind of method is: after described first time injects, and coating photoresist also etches formation source region injection
Window, carries out second time and injects formation and be separated into two-part source region.The mode that source region is formed has multiple,
Second method in the present embodiment, its source region forming process is relatively easy, it is not necessary to carries out photoetching and determines source region
Inject window, reduce technical process and process costs.
On the one hand in the present embodiment, use twice injection and the mode that drives in make and body district and weight are lightly doped
Doped body region, because second time drives in the volume increasing heavy doping body district, and then increases heavy doping body district whole
The proportion in individual district, thus reduce the resistivity in body district so that body district resistance reduces；On the other hand pass through
The control driving in the time to twice ensure that the length of device channel region, thus while reducing body district resistance
Other electrical parameter is not impacted.Prior art only drives in when formation is lightly doped body district,
It is to avoid the impact of channel width is not driven in when forming heavy doping body district.In the present embodiment the most right
Body district and heavy doping body district are lightly doped all drive in, by control drive in for twice the time realize reduce body district
Resistance also guarantees channel length.Drive in concrete setting of time for twice to carry out according to concrete scene.Implement
Example guaranteeing, channel length is also depending on concrete application scenarios.
In order to be better understood from the present invention, provide below in conjunction with the another embodiment with reference to Fig. 2 a to Fig. 2 g
The forming method of a kind of VDMOS device, Fig. 2 a to Fig. 2 g shows the VDMOS that the present embodiment is provided
The cross-sectional view that each step of forming method of device is corresponding.
Concrete, illustrating as a example by n-type channel, Ji Ti district is p-type semiconductor, and source region is N-shaped
Quasiconductor, the most merely illustrative, this invents the embodiment of equally applicable P-type channel.
As shown in Figure 2 a, first provide substrate, substrate makes epitaxial layer, gate oxide successively, at grid
Perform etching after depositing one layer of polysilicon layer in oxide layer, cut through described polysilicon layer and part gate oxide,
Forming spaced multiple polycrystalline grid, wherein thickness of grid oxide layer is, visual organ
Depending on part cut-in voltage scope, it is preferablyWherein polycrystalline gate from , it is preferablyOn epitaxial layer, etching stays the purpose of part gate oxide to be one
Aspect is because source region is injected to thick atom As or BF2, it is necessary to oxide layer etches away a part, reduces
Source region is injected the stop of ion；On the other hand can protect epi-layer surface, reduce in injection process external
Prolong the damage that layer surface is brought.
As shown in Figure 2 b, the described epitaxial layer being pointed between adjacent described polycrystalline grid carries out noting for the first time
Enter to be formed P-body district；Source region injection region, the unit in described source region injection region is formed described being lightly doped in body district
Element has the thick atom attribute than great and easy activation；If n-type channel, it is arsenic that usual source region injects element,
Because the atomic number of arsenic element 33, it is the slowest that element relative atomic mass drives in the most greatly that process moves, ability
Ensureing to form the raceway groove determining width when that second time driving in, if P-type channel, usual source region injects two
Boron fluoride.Generally source region Implantation Energy between 80KeV～150KeV, preferably 120KeV, injectant
Amount usually 1E15/cm2～8E15/cm2, preferably 6E15/cm2.Generally element is injected in P-body district is boron,
Implantation Energy is generally between 50KeV～150KeV, and preferably 80KeV, implantation dosage is usually
1E13/cm2～8E13/cm2Individual, preferably 4E13/cm2Individual.
As shown in Figure 2 c, according to the first Preset Time and the first preset temperature, the described body district that is lightly doped is carried out
Driving in, to form channel region, described first Preset Time is 60～100 minutes, preferably 70 minutes；Institute
State the first preset temperature 1100～1200 degrees Celsius, preferably 1150 degrees Celsius, drive in (driving) technique
Purpose is to activate the ion adulterated, and usual injection process is to use the high temperature anneal to complete.
As shown in Figure 2 d, deposit one layer of dielectric layer and etch described dielectric layer and initial source region, by described initially
Source region is separated into two-part source region, forms heavy doping body district and injects window.
As shown in Figure 2 e, counterweight doped body region is injected in window carries out being infused in described P-body district for the third time and is formed
P+ body district, being usually injected into element is boron, and Implantation Energy is 80KeV～150KeV, preferably 120KeV, agent
Amount usually 1E15/cm2-5E15/cm2, preferably 2E15/cm2。
As shown in figure 2f, according to the second Preset Time and the second preset temperature, described heavy doping Shen Ti district is entered
Row drives in, to increase the volume in described heavy doping body district and to guarantee the length of described channel region, described second pre-
If the time is 60～100 minutes, preferably 70 minutes；Described second preset temperature is 1100～1200 to take the photograph
Family name's degree, preferably 1150 degrees Celsius.Owing to Shen Ti district have passed through the process that drives in of high temperature, and then increase heavily doped
Za Ti district is at the proportion in whole body district, thus reduces the resistivity in body district, according to resistance formula: R=ρ * L/S,
Because L/S does not changes, show that body district resistance reduces, simultaneously the first Preset Time and described second Preset Time
Sum is lightly doped the Preset Time that body district drives in (i.e. only carries out in prior art body district is lightly doped equal to conventional
Drive in drives in the time), it is ensured that channel region is identical with the channel width of the device that traditional handicraft generates, wherein
Second Preset Time can be equal to described first Preset Time, because so time is easily controllable and then permissible
Drive in degree twice of control volume district, finally ensure that the length of final raceway groove.
As shown in Figure 2 g, deposit layer of metal layer on surface again, and then form source class metal, such VDMOS
One structure cell of device just as it can be seen, VDMOS device be through said method step make and
Becoming, final VDMOS device is made up of several such cellulars.
In order to further illustrate the another kind of manufacture method of the source region introduced in method flow diagram, example below
The cross-sectional view that another kind of source region manufacture method is corresponding is provided in conjunction with Fig. 3 a, Fig. 3 b.
As shown in Figure 3 a, etched by development after surface applies a layer photoetching glue, form the injection window of source region
Mouthful.
As shown in Figure 3 b, carrying out for the second time, injecting formation is separated into two-part source region.
The foregoing is only presently preferred embodiments of the present invention, be not intended to limit protection scope of the present invention.
All any modification, equivalent substitution and improvement etc. made within the spirit and principles in the present invention, are all contained in
Within protection scope of the present invention.
Although preferred embodiments of the present invention have been described, but those skilled in the art once know base
This creativeness concept, then can make other change and amendment to these embodiments.So, appended right is wanted
Ask and be intended to be construed to include preferred embodiment and fall into all changes and the amendment of the scope of the invention.
Obviously, those skilled in the art can carry out various change and modification without deviating from this to the present invention
Bright spirit and scope.So, if the present invention these amendment and modification belong to the claims in the present invention and
Within the scope of its equivalent technologies, then the present invention is also intended to comprise these change and modification.
Claims (10)
1. the manufacture method of a VDMOS device, it is characterised in that including:
Substrate makes epitaxial layer, gate oxide and polycrystalline grid successively；
The described epitaxial layer being pointed between adjacent described polycrystalline grid carries out injecting formation for the first time and is lightly doped
Body district；
Forming source region injection region described being lightly doped in body district, the element in described source region injection region has the most former
Son is than the attribute of great and easy activation；
Carry out driving in, to form channel region for the first time according to the first Preset Time；
Dielectric layer deposited also etches formation heavy doping body district and injects window, carries out third time and is infused in and described gently mixes
Heavy doping body district is formed in Za Ti district；
Carry out second time according to the second Preset Time to drive in, to increase the volume in described heavy doping body district and to guarantee
The length of described channel region.
The manufacture method of VDMOS device the most according to claim 1, it is characterised in that described
Form polycrystalline grid, particularly as follows:
Perform etching after gate oxide deposits one layer of polysilicon layer, cut through described polysilicon layer and part grid
Oxide layer, forms spaced multiple polycrystalline grid.
The manufacture method of VDMOS device the most according to claim 1, it is characterised in that described
Described being lightly doped in body district forms source region injection region, particularly as follows:
After described first time injects, at the described epitaxial layer between adjacent two described polycrystalline grids
Inside carry out second time and inject the initial source region of formation；Or,
After described first time injects, coating photoresist also etches formation source region injection window, carries out second
Secondary injection formation is separated into two-part source region.
The manufacture method of VDMOS device the most according to claim 3, it is characterised in that described shallow lake
Long-pending dielectric layer also etches formation heavy doping body district injection window, specifically includes:
Etch described dielectric layer and described initial source region, described initial source is distinguished and is divided into two-part source region.
5. according to the manufacture method of the VDMOS device described in any one of Claims 1-4, its feature
Being, if form N+ source region, injection element is arsenic；If form P+ source region, injection element is bifluoride
Boron.
The manufacture method of VDMOS device the most according to claim 5, it is characterised in that described
One Preset Time and described second Preset Time sum are equal to the driving of body district injection process is the most once lightly doped
The angle of incidence.
The manufacture method of VDMOS device the most according to claim 5, it is characterised in that described
Two Preset Times are equal to described first Preset Time.
The manufacture method of VDMOS device the most according to claim 5, it is characterised in that described
Carry out driving in for the first time according to the first Preset Time, including:
According to the first Preset Time and the first preset temperature, the described body district that is lightly doped is driven in；
Described first Preset Time is 60～100 minutes；Described first preset temperature 1100～1200 degrees Celsius.
The manufacture method of VDMOS device the most according to claim 5, it is characterised in that described
Carry out second time according to the second Preset Time to drive in, including:
According to the second Preset Time and the second preset temperature, described heavy doping Shen Ti district is driven in；Described
Second Preset Time is 60～100 minutes；Described second preset temperature is 1100～1200 degrees Celsius.
10. a VDMOS device, it is characterised in that described VDMOS device is by such as claim
The manufacture method of the VDMOS device described in 1～9 any one obtains.
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| CN201510312718.9A CN106298534A (en) | 2015-06-09 | 2015-06-09 | A kind of VDMOS device and preparation method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110176395A (en) * | 2019-06-13 | 2019-08-27 | 深圳市锐骏半导体股份有限公司 | A kind of VDMOS device production method reducing floating error |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5268586A (en) * | 1992-02-25 | 1993-12-07 | North American Philips Corporation | Vertical power MOS device with increased ruggedness and method of fabrication |
| US5521409A (en) * | 1990-12-21 | 1996-05-28 | Siliconix Incorporated | Structure of power mosfets, including termination structures |
| CN1428872A (en) * | 2001-12-24 | 2003-07-09 | 华瑞股份有限公司 | Power metal oxide semiconductcor field effect transistor device and its manufacture method |
-
2015
- 2015-06-09 CN CN201510312718.9A patent/CN106298534A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5521409A (en) * | 1990-12-21 | 1996-05-28 | Siliconix Incorporated | Structure of power mosfets, including termination structures |
| US5268586A (en) * | 1992-02-25 | 1993-12-07 | North American Philips Corporation | Vertical power MOS device with increased ruggedness and method of fabrication |
| CN1428872A (en) * | 2001-12-24 | 2003-07-09 | 华瑞股份有限公司 | Power metal oxide semiconductcor field effect transistor device and its manufacture method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110176395A (en) * | 2019-06-13 | 2019-08-27 | 深圳市锐骏半导体股份有限公司 | A kind of VDMOS device production method reducing floating error |
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Application publication date: 20170104 |