CN1428872A - Power metal oxide semiconductcor field effect transistor device and its manufacture method - Google Patents
Power metal oxide semiconductcor field effect transistor device and its manufacture method Download PDFInfo
- Publication number
- CN1428872A CN1428872A CN 01144661 CN01144661A CN1428872A CN 1428872 A CN1428872 A CN 1428872A CN 01144661 CN01144661 CN 01144661 CN 01144661 A CN01144661 A CN 01144661A CN 1428872 A CN1428872 A CN 1428872A
- Authority
- CN
- China
- Prior art keywords
- trap
- alloy
- type
- planted
- epitaxial layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The present invention relates to a power metal oxide semiconductor field effect transistor device and its production method. Said device successively has the drain on the N(+) silicon base, N(-) barrier crystal layer formed on the N(+) silicon base, N(+) type trap source contact zone formed in P(-) trap on the N(-) barrier crystal layer and source contact zone of the P(+) type dopant trap arranged after etching and gate electrode on which the multicrystal silicon is deposited over the channel between N(-) barrier crystal layer and N(+) type source contact zone. Said source contact zone is being in the boundary surface place between the N(-) barrier crystal layer and P(-) trap in which the P(+) dopant is ion-implanted after the P(-) trap is etched, and the above-mentioned source contact zone of N(+) type trap and the source contact zone of the P(+) type trap are not on same voltage.
Description
Technical field
The present invention relates to a kind of power MOSFET (metal-oxide-semiconductor field effect transistor metal oxide semiconductcor field effect transistor) device and manufacture method thereof that has the generation that reduces reverse leakage current sudden turn of events phenomenon and improve anti-snowslide collapse electric current (avalanche breakdown current) ability, and be particularly related to a kind of planar technique formula power MOSFET device and manufacture method thereof.
Background technology
Fig. 1 (a) has shown the manufacturing step of the power MOSFET device of common planar technique to Fig. 1 (h).Wherein Fig. 1 (a) has shown that growth field oxide 3 is at N
-Step on the epitaxial layer (EPI) 2, this N
-Epitaxial layer is formed on N
+On the substrate 1.Fig. 1 (b) has shown this field oxide 3 of etching and has carried out the formation step of gate 4.Fig. 1 (c) shows the step of polysilicon layer 5 depositions.Fig. 1 (d) show to carry out that the polysilicon layer light shield covers and polysilicon layer etching and form the polysilicon gate pole, and cloth is planted P
-Alloy and drive in this P
-Alloy and form P
+Trap 6 promptly forms P
-The step of channel region 6.Fig. 1 (e) demonstration applies P
+The light shield of alloy covers and cloth is planted P
+Alloy and form P
+The step of trap 7.Fig. 1 (f) demonstration applies N
+The light shield of alloy covers and cloth is planted N
+Alloy 8 and form the step of source contact area.Fig. 1 (g) shows the step of deposition BPSG (boron phosphorus silicate glass) 9.Fig. 1 (h) demonstration is used source contact metallization 10 and is handled the step of wafer rear contact as drain contact 11.
In the above-mentioned power MOSFET device made by common manufacturing step, when this device for closing (OFF) reverse leakage current at P
-Trap, i.e. P
-When flowing in the channel region 6, because N
+And P
+Trap 8 and 9 current potential identical (because of source potential identical), and because of this trap P
-Be little doped region, so this reverse leakage fails to be convened for lack of a quorum from N
- Epitaxial layer 2 flows through P
-Trap 6 and P
+Trap 7 is to source electrode (8,10) and will be at P
-Trap 6 and P
+The region generating voltage drop of trap 7, when this pressure drop during greater than 0.6 to 0.7 volt, can make the PN parasitic diode in this device open conducting (ON), produce a large amount of reverse leakage currents and the phenomenon of the reverse leakage current sudden turn of events takes place, and owing to this a large amount of electric current generally all concentrates on this P
-Trap 6 and N
-The corner at the interface of epitaxial layer 2, so this temperature at the interface is easy to increase and this device is damaged, so this device is not high on the ability of anti-snowslide collapse electric current yet.
In addition, rectilinear in recent years power transistor (Vertical Power MOSFET) device is applied on the power Switching power circuit of automatic electric machine in large quantities, and the most serious failure mode of this application is that inductive switching (Inductive Switching) can cause a large amount of avalanche currents down and cause device to produce wasting snowslide collapse electric current.In recent years, disclose the favourable P that is used in the 4774198th, 5057884,4587713, No. 5268586 at for example United States Patent (USP)
-Add a heavily doped P in the well region
+The district is to reduce P
-The probability of the parasitic BJT in the trap (bipolarity junction transistor) conducting, and then protect this device not destroyed by excessive avalanche current and reach the anti-avalanche current ability that promotes, to shown in Figure 6, its V-I characteristic will be described below as Fig. 3.
Therefore; be necessary to design a kind of power MOSFET device that minimizing reverse leakage current sudden turn of events phenomenon improves anti-snowslide collapse current capacity that has; the quality and the reliability of this device are improved significantly, and then protect the variation of this device under all kinds of moment power supply shakiness on the circuit application.
Summary of the invention
The object of the present invention is to provide a kind of power MOSFET device and manufacture method thereof that the sudden turn of events of minimizing reverse leakage current improves anti-snowslide collapse current capacity that have.
For achieving the above object, the invention provides a kind of power MOSFET device, it has N in order
+The drain of silicon substrate is formed on this N
+N on the silicon substrate
-Epitaxial layer is formed on this N
-The P of epitaxial layer top
-Trap is at this P
-The N that forms in the trap
+And the P that cloth is planted after the etching
+The source contact area of type alloy trap, and at this N
-Epitaxial layer and N
+The passage top deposits the gate electrode of polysilicon between the type source contact area, and wherein, described source contact area is for being etched to P earlier
-Implanting ions P again in the trap
+Finish after the alloy and be positioned at this N
-Epitaxial layer and this P
-Between trap at the interface, and this N
+The source contact area of type trap and this P
+The source contact area of type plunger is not on same voltage, can increase the anti-snowslide collapse current capacity of power MOSFET device thus.
The present invention also provides a kind of manufacture method of power MOSFET device, comprises the following steps:
1. at N
+The N that grows up of heap of stone on the silicon substrate brilliantly
-Epitaxial layer;
2. grow up field oxide at this N
-On the epitaxial layer;
3. this field oxide of etching and form gate;
4. deposit spathic silicon layer;
5. the light shield of carrying out this polysilicon layer covers and the etching of polysilicon layer and form the polysilicon layer gate pole, and cloth is planted P
-Alloy and drive in this P
-Alloy and form P
-Trap;
6. apply N
+The light shield of alloy covers and cloth is planted N
+Alloy and form source contact area;
7. make photoresistance, define the etching of source etch district after, cloth is planted P
+Alloy and form P
+Well region is then removed photoresistance;
8. deposit BPSG; And
9. making the metallization of source electrode contact point and handling the wafer rear contact is the drain contact;
Wherein, cloth is planted P
+Alloy is in this N
+Type source area and form P
+The step of well region is this N of downward etching
+The degree of depth that source area is 1 micron to 1.2 millimeters (adjusting according to different pressure-resistant apparatus) is to this P
-In the trap, from this P
-The etching region part cloth of trap is planted P
+Alloy makes this P
+The alloy trap is positioned at this P
-Trap and this N
-Between epitaxial layer at the interface.
According to power MOSFET apparatus features of the present invention, when it was opened, electron stream flowed from source electrode, through N
+Doped layer and P
-The inversion layer channel region is to N
-Epitaxial layer and drain.And when closing, reverse leakage current from drain through N
-Epitaxial layer directly flows through P
+Trap is to source electrode, because this P
+Type doped layer trap belongs to heavily doped layer, and resistance is minimum, so be difficult at source electrode and N
+Produce voltage drop between epitaxial layer and make PN parasitic diode conducting in this device, produce a large amount of reverse leakage currents and the phenomenon of the reverse leakage current sudden turn of events takes place, and improved the ability that electric current is collapsed in the anti-snowslide of this device.Moreover though in the prior art, cloth is planted this heavily doped P
+Trap is difficult for deeply to P
-Trap and N
-Between epitaxial layer at the interface, but manufacturing method according to the invention, wherein cloth is planted P
+Alloy is in this N
+Type source area and form P
+The step of type trap is downward this N of etching
+The degree of depth that source area is 1 micron to 1.2 millimeters is in this P
-Among the trap, from this P
-The source area part cloth of trap is planted P
+Alloy makes this P
+The type trap is positioned at this P
-Trap and this N
-Between epitaxial layer at the interface.
Description of drawings
Foregoing of the present invention will be elaborated in conjunction with following accompanying drawing with other purpose, characteristic and advantage, and wherein similar elements is represented with same-sign:
Fig. 1 (a) is the manufacturing step of the power MOSFET device of common planar technique to Fig. 1 (h);
Fig. 2 (a) to Fig. 2 (j) be the manufacturing step of power MOSFET device of the present invention;
Fig. 3 to Fig. 6 shows the structure skeleton diagram of No. the 4774198th, 5057884,4587713,5268586, United States Patent (USP) respectively;
Fig. 7 (a) and Fig. 7 (b) show common test circuit skeleton diagram and the V-I performance plot of measuring the anti-avalanche current ability of power MOSFET device respectively;
Fig. 8 shows the V-I performance plot of the anti-avalanche current of typical prior art MOSFET device (through the simulation drawing of No. the 4774198th, reference United States Patent (USP)), though wherein this device is planted P at source electrode cloth
+Alloy, but not etching of source electrode;
Fig. 9 shows the V-I performance plot of the anti-avalanche current of power MOSFET device according to the present invention, and wherein source electrode is that etching and cloth are planted P
+Alloy.
Embodiment
Fig. 2 (a) has shown the manufacturing step of power MOSFET device of the present invention to Fig. 2 (j).Wherein, Fig. 2 (a) has shown the N that grows up of heap of stone on N substrate 11 brilliantly
- Epitaxial layer 12 reaches at this N
- Growth field oxide 13 on the epitaxial layer 12.In Fig. 2 (b), show to apply this field oxide 13 of light shield etching and form gate 14 and be used as dielectric medium.Fig. 2 (c) shows that deposit spathic silicon layer 15 is on this gate 14.The light shield that Fig. 2 (d) show to carry out this polysilicon layer 15 covers and the etching of polysilicon layer 15 and form the polysilicon gate pole, and cloth is planted P
-Alloy and drive in this P
-Alloy and form P
-Trap 16.In Fig. 2 (e), show to apply N
+The light shield of alloy covers and cloth is planted N
+Alloy and form source area 18.In Fig. 2 (f), downward this N of etching
+The degree of depth that source area is 1 micron to 1.2 millimeters (this degree of depth will be adjusted to some extent by different pressure-resistant apparatus, be 30 volts of withstand voltage MOSFET devices herein) is to this P
-Among the trap 16.Then, shown in Fig. 2 (g), from this P
-This source area part cloth of trap 16 is planted P
+Alloy makes this P
+Type alloy trap 17 is positioned at this P
-Trap 16 and this N
-12 of epitaxial layers form heavy doping P at the interface
+Type trap 17, photoresistance is removed in the back shown in Fig. 2 (h).Then, deposit BPSG19 shown in Fig. 2 (i), then making the contact metallization 20 of source area and handle the wafer rear contact shown in Fig. 2 (j) is the drain contact, and forms passivation layer 21 and finish according to power MOSFET device of the present invention on this metal.As mentioned above, this power MOSFET device has N in order
+The drain of silicon substrate 11 is formed at this N
+N on the silicon substrate 11
- Epitaxial layer 12 is formed at this N
-The P of epitaxial layer 12 tops
-Trap 16 is at this P
-The N that forms on the trap 16
+And P
+ Type alloy trap 18 and 17 source contact area, and at this N
- Epitaxial layer 12 and N
+The passage top deposits the gate electrode of polysilicon, wherein this P between the type source contact area 18
+The source contact area of type alloy trap 17 is positioned at this N
- Epitaxial layer 12 and this P
-16 of traps at the interface, and this N
+The source contact area of type trap 18 and this P
+The source contact area of trap is not on same voltage.
When device of the present invention was closed (OFF), reverse leakage failed to be convened for lack of a quorum from N
-Epitaxial layer 12 P that directly flows through
+Alloy trap 17 is to source electrode 20, because this P
+Type alloy trap 17 belongs to heavily doped layer, and resistance is minimum, so be difficult at source electrode 20 and N
-12 of epitaxial layers produce voltage drop and make PN parasitic diode conducting (ON) in this device, produce a large amount of reverse leakage currents and the phenomenon of the reverse leakage current sudden turn of events takes place, and improved the ability that electric current is collapsed in the anti-snowslide of this device.
Manufacturing method according to the invention, wherein cloth is planted P
+Alloy is in this N
+ Type source area 18 and form P
+The step of type trap 17 is these N of downward etching
+Source area one proper depth is in this P
-Among the trap 16, from this P
-The etching region part of trap 16 comes cloth to plant P
+Alloy makes this P
+Type alloy trap 17 is positioned at this P
-Trap 16 and this N
-12 of epitaxial layers at the interface, the cloth that is difficult for that can solve prior art is like this planted heavily doped layer to the shortcoming of depths more.
Fig. 7 (a) and Fig. 7 (b) are respectively common test circuit and the V-I performance plot of measuring the anti-avalanche current ability of power MOSFET device, the wherein I in Fig. 7 (b)
ASMore Gao Ze represents the anti-avalanche current ability of this MOSFET better.Fig. 8 has shown the V-I performance plot of the anti-avalanche current of typical prior art (for example No. the 4774198th, United States Patent (USP)) MOSFET device, though wherein this device is planted P at source electrode cloth
+Alloy, but not etching of source electrode.Fig. 9 shows the V-I performance plot of the anti-avalanche current of power MOSFET device according to the present invention, and wherein source electrode is that etching and cloth are planted P
+Alloy, this two performance plot are all with MEDICI software simulation made.Can find out clearly that by comparing two figure the anti-avalanche current ability of MOSFET device of the present invention can increase substantially significantly.
Though above-mentioned explanation is described with plane formula N channel power MOSFET device, the present invention is also applicable to plane formula P channel power MOSFET device, wherein only needs P changed into N and change N into P to get final product.In addition, the present invention is equally applicable to aqueduct type power MOSFET device or IGBT (insulation gate pole bipolar transistor).The present invention is not limited to above-mentioned explanation, but can allow all modifications and variation, and wherein different manufacture methods causes identical with the method for apparatus of the present invention structure with the implanting ions technology, and the person is within the scope of the invention.
Claims (2)
1. power metal oxide semiconductcor field effect transistor device, it has N in order
+The drain of silicon substrate is formed on this N
+N on the silicon substrate
-Epitaxial layer is formed on this N
-The P of epitaxial layer top
-Trap is at this P
-The N that forms in the trap
+And the P that cloth is planted after the etching
+The source contact area of type alloy trap, and at this N
-Epitaxial layer and N
+The passage top deposits the gate electrode of polysilicon between the type source contact area, it is characterized in that:
Described source contact area is for being etched to P earlier
-Implanting ions P again in the trap
+Finish after the alloy and be positioned at this N
-Epitaxial layer and this P
-Between trap at the interface, and this N
+The source contact area of type trap and this P
+The source contact area of type plunger is not on same voltage, can increase the anti-snowslide collapse current capacity of power MOSFET device thus.
2. the manufacture method of a power metal oxide semiconductcor field effect transistor device comprises the following steps:
1. at N
+The N that grows up of heap of stone on the silicon substrate brilliantly
-Epitaxial layer;
2. grow up field oxide at this N
-On the epitaxial layer;
3. this field oxide of etching and form gate;
4. deposit spathic silicon layer;
5. the light shield of carrying out this polysilicon layer covers and the etching of polysilicon layer and form the polysilicon layer gate pole, and cloth is planted P
-Alloy and drive in this P
-Alloy and form P
-Trap;
6. apply N
+The light shield of alloy covers and cloth is planted N
+Alloy and form source contact area;
7. make photoresistance, define the etching of source etch district after, cloth is planted P
+Alloy and form P
+Well region is then removed photoresistance;
8. deposit boron phosphorus silicate glass; And
9. making the metallization of source electrode contact point and handling the wafer rear contact is the drain contact; Wherein, cloth is planted P
+Alloy is in this N
+Type source area and form P
+The step of well region is this N of downward etching
+Source area to proper depth in this P
-In the trap, from this P
-This source area part cloth of trap is planted P
+Alloy makes this P
+Type alloy trap is positioned at this P
-Trap and this N
-Between epitaxial layer at the interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01144661 CN1217418C (en) | 2001-12-24 | 2001-12-24 | Power metal oxide semiconductcor field effect transistor device and its manufacture method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01144661 CN1217418C (en) | 2001-12-24 | 2001-12-24 | Power metal oxide semiconductcor field effect transistor device and its manufacture method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1428872A true CN1428872A (en) | 2003-07-09 |
| CN1217418C CN1217418C (en) | 2005-08-31 |
Family
ID=4677744
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 01144661 Expired - Fee Related CN1217418C (en) | 2001-12-24 | 2001-12-24 | Power metal oxide semiconductcor field effect transistor device and its manufacture method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1217418C (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008117826A (en) * | 2006-11-01 | 2008-05-22 | Toshiba Corp | Power semiconductor element |
| CN101640197B (en) * | 2008-07-30 | 2011-02-02 | 尼克森微电子股份有限公司 | Semiconductor structure and method for manufacturing same |
| CN102184958A (en) * | 2011-04-22 | 2011-09-14 | 上海宏力半导体制造有限公司 | Vertical double-diffusion MOS (Metal-Oxide Semiconductor) tube and manufacturing method thereof |
| CN106298534A (en) * | 2015-06-09 | 2017-01-04 | 北大方正集团有限公司 | A kind of VDMOS device and preparation method thereof |
-
2001
- 2001-12-24 CN CN 01144661 patent/CN1217418C/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008117826A (en) * | 2006-11-01 | 2008-05-22 | Toshiba Corp | Power semiconductor element |
| CN101640197B (en) * | 2008-07-30 | 2011-02-02 | 尼克森微电子股份有限公司 | Semiconductor structure and method for manufacturing same |
| CN102184958A (en) * | 2011-04-22 | 2011-09-14 | 上海宏力半导体制造有限公司 | Vertical double-diffusion MOS (Metal-Oxide Semiconductor) tube and manufacturing method thereof |
| CN102184958B (en) * | 2011-04-22 | 2015-10-21 | 上海华虹宏力半导体制造有限公司 | Vertical double diffused MOSFET and manufacture method thereof |
| CN106298534A (en) * | 2015-06-09 | 2017-01-04 | 北大方正集团有限公司 | A kind of VDMOS device and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1217418C (en) | 2005-08-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109037208B (en) | Improve the two-way false grid deep trap electrostatic protection device and preparation method thereof of failure voltage | |
| CN108389891B (en) | A kind of double grid grid-control silicon controlled rectifier (SCR) Electro-static Driven Comb device and preparation method thereof | |
| CN101107718A (en) | Power metal oxide semiconductor assembly | |
| CN1825552A (en) | Method of implementation compensating dopant region and semiconductor device structure | |
| US9048308B2 (en) | Regenerative building block and diode bridge rectifier and methods | |
| CN113035701B (en) | Grid resistance adjustable super junction power device and manufacturing method thereof | |
| CN102254828A (en) | Method for making semiconductor device with super junction structure and rapid reverse recovery characteristic | |
| CN108807506A (en) | The deep trouth super-junction MOSFET device and its processing technology of with groove grid structure | |
| CN103094359A (en) | High voltage Schottky diode and manufacturing method thereof | |
| CN101764150B (en) | Silicon-on-insulator lateral insulated gate bipolar transistor and process manufacturing method | |
| CN109037071A (en) | A kind of preparation method of shield grid power device | |
| CN1675777A (en) | Self-aligned vertical gate semiconductor device | |
| CN110459540A (en) | The semiconductor device and its manufacturing method of integrated MOSFET and diode | |
| CN1217418C (en) | Power metal oxide semiconductcor field effect transistor device and its manufacture method | |
| CN106158927A (en) | A kind of super-junction semiconductor device optimizing switching characteristic and manufacture method | |
| US20030151092A1 (en) | Power mosfet device with reduced snap-back and being capable of increasing avalanche-breakdown current endurance, and method of manafacturing the same | |
| CN110676305A (en) | Vertical channel device with low gate charge characteristics and method of manufacture | |
| CN1591800A (en) | Method for mfg. improed structure high-voltage elements | |
| CN101556967B (en) | Power semiconductor and manufacturing method thereof | |
| CN103441149B (en) | Groove power device and preparation method thereof | |
| CN102881595B (en) | A kind of manufacture method of super-junction high-voltage power device | |
| CN115332330A (en) | IGBT device with reverse conduction characteristic and preparation method thereof | |
| CN1538508A (en) | Silicon carbide groove type gold oxygen half electric crystal | |
| CN207265059U (en) | Semiconductor devices | |
| CN108364945A (en) | A kind of double grid grid-control Electro-static Driven Comb device and preparation method thereof improving maintenance voltage |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |