CN1538508A - Silicon carbide groove type gold oxygen half electric crystal - Google Patents
Silicon carbide groove type gold oxygen half electric crystal Download PDFInfo
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Abstract
The invention discloses structure of ditch groove type MOS crystal possessing accumulation layer channel base on silicon carbide substrate. The structure includes ditch groove grid electrode, P- substrate layer, n+ doping zone, P+ doping zone formed in epitoxy or ion implanting, contact of source electrode of n+ doping zone and P+ doping zone, and drain electrode formed on silicon carbide substrate. Accumulation layer channel is located between ditch groove grid electrode and P- substrate layer. The substrate layer and source layer possess same electric potential. The invention also discloses the method for forming the structure.
Description
Technical field
The present invention relates to the related semiconductor processing procedure, particularly a kind of with carborundum as the plough groove type of semiconductor substrate gold oxygen half electric crystal structure and forming method thereof.
Background technology
Wear the electric crystal of voltage power greater than 1000 ambuscades in the market, many is that the Silicon IGBT (Insulated Gate Bipolar Transistor) of substrate plays the leading role in the Silicon Wafer.Yet the IGBT element is owing to be the two-carrier element, when closing element, desire will run into problem how to eliminate minority carrier (MinorityCarriers) lifetime (lifetime), if can not add to shorten into lifetime inhibitor (Lifetime Killer) lifetime of minority carrier from processing procedure, then the IGBT element must bear at power that the shut-in time consumed in system.
Relatively, be that the golden oxygen half electric crystal (MOSFET) that substrate is made is single carrier element with carborundum, can make the element quick closedown and reduce extra power consumption.This is because carbofrax material is owing to have the wide excellent materials that can be regarded as the future development power component with coefficient (3.26eV), high critical breakdown electric field intensity (3MV/cm) and high thermal conductivity coefficient (4.9W/cm-K).The power component that carborundum is made can easily reach 1000 ambuscades and wear the above demand of voltage, as long as make operating voltage even can reach the high pressure of 5KV by adjusting built crystal layer thickness.Therefore replace silicon IGBT with silicon carbide power element MOSFET and gradually become trend.According to theoretical calculation, under the same breakdown voltage condition, with carborundum the R of the power component made of ground
ON, SPThe resistance value of linear zone (when electric crystal is opened) only is 1/200 to 1/400 of silicon power component.
For making element is (the Normal Off) that closes under normal condition, and traditional carbonization silicon trench formula gold oxygen half electric crystal is taked inversion layer passage (Inversion Channel) more.For example, No. the 5506421st, the United States Patent (USP) that Palmour obtained, title are " Power Mosfet in Silicon Carbide ".Please refer to the cross sectional representation shown in Figure 1A.The diagram drain area comprises silicon carbide substrate 10 and mixes with n type impurity and drift layer 12.Then a p type doping impurity epitaxial layer 14 on the drift layer 12.27 of grooves are formed among the p type doping impurity epitaxial layer 14, and groove 27 bottoms are then goed deep in the drift layer 12.31 of gate pole oxidation layers are formed at channel bottom, sidewall and extend to the upper surface of p type impurity doping epitaxial layer 14.30 of gate contacts are formed on the gate pole oxidation layer 31.In addition, source electrode contact 22 more is formed at the n type impurity doped region n+18 of groove 27 both sides except forming p type impurity doping epitaxial layer 14, so that the source electrode contact remains on earthing potential.Show terminator 35 and oxide layer 36 formed thereon on the figure.The disadvantage of said structure is linear zone sheet resistor value R
ON, SPToo big.
In order to address this problem, adopting accumulation layer passage (Accumulation Channel) should be feasible method.The accumulation layer passage can allow passage that electronics flows by close the semiconductor of inversion layer passage and the interface zone of oxide layer (Interface Region) then move on to the mobility that electronics so can be improved in semiconductor inside (BulkRegion), and then the R of reduction element
ON, SP
Adopting accumulation layer passage (Accumulation Channel) to please refer to 6281521, one pieces of titles of United States Patent (USP) is " Silicon Carbide Horizontal Channel Buffered GateSemiconductor Devices ", is obtained by Singh.This patent is a kind of element of plane formula shown in Figure 1B.The greatest feature of this structure is not have gate pole oxidation layer, the substitute is with p type gate layer 16 and isolates gate contact 20 and the drift layer 12 that is formed on the silicon carbide substrate 10.And make can be in the channel region 15 generations one accumulation layer passage of drift layer 12 tops when being biased in gate and contacting 20 when applying.And when not applying when being biased in gate and contacting 20 passage extruding (Pinch Off) between p+ basal area (p+base Region) 14 and gate layer 16.For reaching the purpose of closing under the normal condition (promptly under the zero gate bias voltage, no current flows to drain 24 by source electrode), the doping content of must be selected suitable drift layer 12, p+ basal area 14 and gate layer 16, also must selecting gap between suitable substance P+basal area 14 and the gate layer 16 simultaneously, just to reach channel region 15 be exhaustion region completely not having under the gate voltage.
Though can reaching, the patent of Singh reduces R
ON, SPPurpose, yet because gate belongs to plane formula but not plough groove type, therefore, the required area of unit element will be greater than aforementioned plough groove type gold oxygen half electric crystal structure.
Summary of the invention
In view of aforesaid problem, the present invention will provide the mobility of a kind of golden oxygen half electric crystal of plough groove type accumulation type passage in order to the raising electronics, and then reduce the R of element
ON, SP
The purpose of this invention is to provide a kind of manufacture method that can high voltage bearing power electric crystal, this electric crystal is a kind of plough groove type gold oxygen half electric crystal structure of silicon carbide substrate.
Another purpose of the present invention provides the high problem of plough groove type gold oxygen half electric crystal structure linear operation resistance value that solves traditional inversion layer passage with the plough groove type gold oxygen half electric crystal structure of accumulation layer passage.
The invention provides a kind of groove gold oxygen half electric crystal structure, comprise: a n type doping impurity epitaxial layer and the heavily doped silicon carbide substrate of a n type impurity, a n type conductive impurity heavily doped region and adjoin the p type conductive impurity heavily doped region that is formed in this epitaxial layer and extends to the upper surface of this epitaxial layer each other; The one groove gate that is formed in this epitaxial layer and adjoins mutually with n type conductive impurity heavily doped region; One be formed in this epitaxial layer and with the groove gate at a distance of gapped p-base district, this gap is in order to as the accumulation layer passage.Bottom, p-base district is roughly the same with gash depth, and adjoins each other with n type conductive impurity heavily doped region and D type conductive impurity heavily doped region simultaneously, makes source metal and p-base district keep same potential.
In addition, one separator is formed on the groove gate and cover part n type conductive impurity heavily doped region, and source metal is formed at the silicon carbide substrate upper surface, connect n type conductive impurity heavily doped regions all on the substrate and p type conductive impurity heavily doped region simultaneously, it is isolated by separator and groove gate.
Plough groove type gold oxygen half electric crystal of the present invention is with regard to structure, it is a kind of golden oxygen half electric crystal that belongs to the accumulation layer passage, for making element of the present invention not apply under the state of voltage at gate is closed condition, p-basalis and n drift layer doping impurity concentration are through suitable selection, in addition, thus also need standard accumulation layer passage to reach that the accumulation layer passage becomes exhaustion region under the reverse blas.According to structure of the present invention, puncture voltage can reach 2200V, and electric crystal is under the operating voltage of linear zone, and sheet resistor only has 11m Ω-cm
2With regard to this puncture voltage, approached the limit of theoretical value, so element of the present invention with compare than the electric crystal of traditional tool inversion layer passage, have more antagonism and reduce so that R because of electron mobility raises with the element operation temperature
ON, SPThe advantage of rising.
Description of drawings:
The preferred embodiments of the present invention will be aided with following accompanying drawing and do more detailed elaboration in the comment of back:
Figure 1A shows the plough groove type gold oxygen half electric crystal structure cross sectional representation of the traditional silicon carbide substrate with inversion layer passage.
Figure 1B shows the plane formula gold oxygen half electric crystal structure cross sectional representation of the traditional silicon carbide substrate with accumulation layer passage.
Fig. 2 A shows that foundation method of the present invention imposes implanting ions to form the schematic diagram in p-base district in epitaxial layer.
Fig. 2 B shows according to method of the present invention, and comprehensive implanting ions is to form the schematic diagram of n+ heavily doped region.
Fig. 2 C shows according to method of the present invention, with the schematic diagram of photoresistance or rigid cover curtain definition groove gate.
Fig. 2 D shows and removing photoresistance or rigid cover backstage, to form gate pole oxidation layer according to method of the present invention on trenched side-wall and bottom and substrate, and with the schematic diagram of compound crystal silicon layer backfill.
Fig. 2 E shows according to the schematic diagram behind the method definition groove gate of the present invention.
Fig. 2 F shows that foundation method of the present invention imposes the high-temperature thermal oxidation processing procedure, so that be exposed to the schematic diagram of the compound crystal silicon layer oxidation of irrigation canals and ditches upper surface.
Fig. 2 G shows according to method formation photoresistance pattern of the present invention, imposes implanting ions again, to form the cross sectional representation of p+ doped region.
Fig. 2 H shows that foundation method of the present invention forms separator and cover part n+ heavily doped region on the groove gate, form the cross sectional representation of source electrode contact metal layer and drain contact metal layer again.
Fig. 2 I shows the three-dimensional form schematic diagram that forms golden oxygen half electric crystal according to method of the present invention.
Fig. 3 shows element of the present invention electrical analog result figure with the mapping of drain voltage and current density under different gate voltage.
Fig. 4 shows element of the present invention when the gate bias voltage is zero, and drain imposes the electrical analog result figure of voltage with the test puncture voltage.
Fig. 5 shows under the puncture voltage of element of the present invention and the linear work resistance value element schematic diagram made from famous research institution all over the world relatively.
The description of symbols table of comparisons in the accompanying drawing
| 10 | 12 drift layers |
| The 14p+ | 15 |
| 16 gate layers | The 18n+ source area |
| The contact of 20 gates | The contact of 22 source electrodes |
| The contact of 24 drains | 27 grooves |
| The contact of 30 gates | 31 gate |
| 35 terminators, 36 | 100A silicon carbide substrate n+ doped |
| 100B n-epitaxial layer | The 105p- |
| 108 n+ doped | 110 rigid |
| 120 grooves | W accumulation |
| 130 gate | 140 |
| 150 polysilicon oxide layers | 102,165 |
| 170 p+ doped | 180 separators |
| The contact of 200 source metals | |
| 210 groove | 220 drain Metal Contact |
| 410 electronic impact degree of ionization are to the drain voltage curve | 420 with electric hole knock-on ion degree to the drain voltage curve |
| 430 converse electrical leakage flow curves |
Embodiment
Groove of the present invention gold oxygen half electric crystal manufacture method please refer to the cross sectional representation of Fig. 2 A to Fig. 2 I.
Please refer to Fig. 2 A, the semiconductor substrate of a silicon carbide material at first is provided, this semiconductor substrate comprises the n-epitaxial layer 100B of a n type impurity heavily doped n+ substrate 100A and n type doping impurity as drift layer (Drift Layer).Then on this epitaxial layer 100B, form one and have the photoresistance pattern 102 that defines p-base district 105 openings.Subsequently, serve as the cover curtain with photoresistance pattern 102, impose implanting ions for the first time, be implanted into p type conductive impurities, for example aluminium or BF in epitaxial layer 100
2+Etc. conductive impurities, to form p-base district 105.The degree of depth in p-base district 105 is about 0.8 μ m to 5.0 μ m.
Please refer to Fig. 2 B, and then after removing photoresistance pattern 102, impose implanting ions for the second time comprehensively, be implanted into n type conductive impurities in epitaxial layer 100B.N type conductive impurities can be a nitrogen ion for example, to form n+ doped layer (Fig. 2 C then is called doped region after reaching) 108, wherein the face that connects of n+ doped region 108 and this epitaxial layer 100B obviously is shallower than the face that connects of this p-base district 105 and epitaxial layer 100B, and its result is shown in Fig. 2 B.
Please refer to Fig. 2 C, go up in epitaxial layer 100B and form a metal level or oxide layer.Again with little shadow photoresistance and etching technique definition metal level or oxide layer 110, has the rigid cover curtain 110 of groove opening pattern with formation subsequently.With follow-up be etch mask with photoresistance and rigid cover curtain 110, or after photoresistance pattern (not shown) was removed, continuous was etch mask with rigid cover curtain 110, etching epitaxial layer 100B is with formation groove 120.The degree of depth of groove 120 degree of depth with p-base district 105 approximately is suitable.The both sides of this outer channel 120 and p-base district 105 be at a distance of the gap of width W, with as the accumulation layer passage.
Subsequently, please refer to Fig. 2 D.After removing rigid cover curtain 110, form bottom, sidewall and this epitaxial layer 100B surface of a gate pole oxidation layer 130 in groove 120 comprehensively.Gate pole oxidation layer 130 can be the oxide layer HTO of high temperature deposition or the thermal oxidation method oxide layer of growing up or the polysilicon layer gate pole oxidation layer 130 of thermal oxidation again of deposition skim earlier.For preferred embodiment, the thickness of gate pole oxidation layer is about 50nm to 200nm.
And then, deposit a polysilicon layer 140 more comprehensively, filling up this groove 120, and be formed on the semiconductor substrate.Polysilicon layer 140 can be used the Low Pressure Chemical Vapor Deposition (LPCVD) and the synchronous method deposition of Doped n-type conductive impurities, also can after the deposition in polysilicon layer again with POCL
3The diffusion impurity phosphorus atoms.
Subsequently, please refer to the cross sectional representation shown in Fig. 2 E, define polysilicon layer 140 to define polysilicon trench gate 140A with little shadow and etching technique.Generally speaking, polysilicon layer 140 width W 1 that protrude from the epitaxial layer 100 B upper surfaces can be a bit larger tham irrigation canals and ditches width W 2, can make easier the carrying out of contact procedure of polysilicon trench gate 140A like this.
After removing etch mask, carry out the thermal oxidation processing procedure subsequently, make the upper surface oxidation of polysilicon layer 140A, so that the exposed upper surface of irrigation canals and ditches gate 140A coats an oxide layer 150, certainly epitaxial layer 100B is in the thermal oxidation processing procedure, also can generate a thickness and groove gate 140A and go up oxide layer 150 thickness that the coat thin oxide layer of comparing, shown in Fig. 2 F.Note that this thermal oxidation fabrication steps is optionally.As irrigation canals and ditches gate 140A when to protrude from epitaxial layer 100B upper surface be not a lot, oxidization time just should not be too of a specified duration, perhaps can omit this step.
Please refer to the cross sectional representation shown in Fig. 2 G, then, form a photoresistance pattern 165 again, in order to the p+ doped region 170 in the definition double diffusion source electrode.Subsequently, promptly carry out implanting ions for the third time, implant p type impurity to form p+ doped region 170.P+ doped region 170 adjoins n+ doped region 108, and cloth to plant the degree of depth also identical.
Subsequently, please refer to the cross sectional representation shown in Fig. 2 H, behind the removal photoresistance pattern 165, deposit an oxide layer 180 more earlier with separator as source electrode and irrigation canals and ditches gate.For preferred embodiment, this layer separator 180 thickness are about 0.3-1.0 μ m, can select for example tetraethoxysilane (TEOS) for use.And then (please refer to the topography of Fig. 2 I with the scope of little shadow and etching technique definition separator 180 and the contact zone of groove gate again; Topographic Diagram).Please note that separator comes isolation trenches gate 140A to contact (aftermentioned) with source metal with 180, the source metal contact then must contact n+ doped region 108 and p+ doped region 170 simultaneously, so that comprise p-substrate 105 and on the codope district (n+ doped region 108 and p+ doped region 170) that adjoins mutually can keep identical current potential simultaneously, therefore, the pattern definition step of separator 180 need make n+ doped region 108 parts exposed.
Please refer to Fig. 2 H, subsequently, impose cycle of annealing earlier with activated impurity, for example 1400-1600 ℃ of annealing of carrying out 30 minutes to 2 hours afterwards, deposits a metal level with metal sputtering more comprehensively.At last, impose little shadow technology and etching technique with contact 200 of definition source metal and groove gate Metal Contact 210.At this moment, source metal contact 200 is what to be separated with groove gate Metal Contact 210.
Please refer to Fig. 2 I and show, according to the formed perspective view of method of the present invention.This figure is the embodiment of a reference, and the groove gate element among the figure can be honeycomb or long ditch shape is arranged or other modes are arranged.
Please refer to Fig. 2 H at last, remove all oxide layers of the semiconductor substrate back side earlier,, subsequently, impose metal sputtering more comprehensively and form a metal level 220 at the back side of semiconductor substrate, as the drain metal contact layer up to exposed n+ doped silicon carbide substrate 100A.Afterwards, heat treatment again is so that source metal 200 and drain metal level 220 and groove gate metal level 210 form low ohm contact layer.
According to the foregoing description, plough groove type gold oxygen half electric crystal structure of the present invention is to adopt the accumulation layer passage, and the passage that promptly is close under the groove gate is positioned at the n-drift layer or claims the n-epitaxial layer.Generally speaking, the element of accumulation layer passage is to belong to the normal element of opening (Normal-On) down, promptly when gate voltage is zero, still has electric current if there is voltage difference to exist between drain end and the source terminal.Though the present invention adopts the accumulation layer passage, but still wish that element is normal element of closing (Normal-Off) down, promptly when gate voltage was zero, passage was required to be cut-off state.Utilize carbofrax material itself to have the characteristic of wide bandgap.Be that the exhaustion region width that carborundum p-n connects face under the no-bias state can make element of the present invention be easy to reach this purpose than the big characteristic of exhaustion region that silicon p-n connects face.In addition, can be again by the concentration relationship in control P-substrate and n-drift zone and accumulation layer channel width to reach when gate voltage when being zero, the accumulation layer passage is in the state by vague and general fully (FullyDepleted).Therefore, for preferred embodiment, the concentration ratio of p-substrate and n-drift region is controlled at 10
15: 10
12To 10
18: 10
15And accumulation layer channel width W is about 0.1-0.8 μ m.
Therefore, processing procedure according to the embodiment of the invention, element of the present invention also is the element of closing under the normal condition, and work as gate voltage is timing, electronics in the accumulation layer passage can be subjected to electric field attracts and accumulate more and more many electronics, so when between drain end and the source terminal voltage difference being arranged, get final product conduction current.Because electronics is motion (belonging to majority carrier) in accumulation layer, therefore can not produce the problem that electronics causes mobility to descend because of collision scattering, under high electron mobility, reduced the resistance R when electric crystal is opened naturally
ON, SP
Fig. 3 to Fig. 5 shows the electrical analog result of the element of making according to the inventive method.Wherein simulation is carried out according to following condition.Gash depth and width are for being 2 μ m.And the concentration relationship of p-substrate and n-drift region is controlled at 10
18Cm
-3: 10
15Cm
-3Accumulation layer channel width w is about 0.3-0.5 μ m.When source voltage was 0 volt, gate voltage and drain voltage then changed respectively as shown in the figure.
Fig. 3 shows drain electric current one drain voltage (Id-Vd), when VG=VD=10V, and R
ON, SPBe 11m Ω-cm
2
Fig. 4 shows shielding (Blocking) the simulated behavior result according to element of the present invention, and display simulation is mapped to drain voltage curve 420 and at converse electrical leakage flow curve 430 to drain voltage curve 410 and with electric hole knock-on ion degree (Hole Impact Ionization Integral) with electronic impact degree of ionization (Electron Impact Ionization).The voltage that this moment, the groove gate applied is 0 volt.Show among the figure that the voltage that applies when gate is 0 volt, source voltage also is 0 volt, and degree of ionization just sharply increased when added drain voltage increased to 2100 volts, and when 2200V, degree of ionization is 1, and expression punctures, and drain puncture voltage this moment (breakdown voltage) reaches 2200V.Not excessive when having only drain voltage, severally flatly can't see leakage current, converse electrical leakage flow curve 430 develops in trunnion axis, only when puncture voltage 2200V, just sharply increases.
We do one to the element of the present invention and the carborundum gold oxygen half electric crystal element of various countries' exploitation at present relatively again.Show among the figure, though the element of being delivered not as good as KEPC according to the component breakdown voltage of manufacturing of the present invention (2200 volts of relative KEPC of the present invention 6000 volts), resistance R of the present invention
ON, SPMinimum.This means that element heating amount of the present invention is minimum, so electron mobility can not rise and descend with temperature, therefore can keep best speed performance.And in fact, with regard to the puncture voltage curve and the R of carborundum
ON, SPRelation, obviously with R
ON, SPEqual 10
-2Ω-cm
2, element of the present invention more approaches the puncture voltage limit that carborundum can reach.And in fact with regard to the application of majority, 2200 volts puncture voltage can be satisfied the demand.
Element of the present invention has following advantage:
(1) tool high-breakdown-voltage, and, therefore electron mobility is remained on certain level owing to be that accumulation layer passage so linear work resistance value are low.
(2) element making step of the present invention is simple, only needs seven road light shields to get final product.
(3) though element of the present invention is the accumulation layer passage, but still be normal element of closing (Normal-Off) down, therefore do not have the problem of leakage current.
More than described the preferred embodiments of the present invention, so it is not in order to limit the present invention.Those skilled in the art can not depart from the improvement and the variation of category of the present invention and spirit to embodiment disclosed herein.
Claims (10)
1, a kind of method that forms groove gold oxygen half electric crystal, this method comprises following steps at least:
Provide and comprise n type doping epitaxial layer and the heavily doped silicon carbide substrate of n type;
On this epitaxial layer, form one first photoresistance pattern, with definition p-substrate doped region;
Impose implanting ions for the first time, cloth is planted p type impurity in epitaxial layer, in order to form a plurality of p-base district;
Remove this first photoresistance pattern;
Impose implanting ions for the second time, cloth is planted n type impurity in this epitaxial layer comprehensively, and in order to form the n+ doped region, wherein the face that connects of n+ doped region and this epitaxial layer is shallower than the face that connects of this p-base district and epitaxial layer;
Define a groove with little shadow and etching technique in this epitaxial layer, this trenched side-wall and this p-base district are separated by with a gap, and this gap is the accumulation layer passage;
Form gate pole oxidation layer at this channel bottom, sidewall and this silicon carbide substrate all surface;
Deposition one polysilicon layer fills up this groove, and makes it to overflow this epitaxial layer comprehensively;
Define this polycrystalline layer of sand to define the groove gate with little shadow and etching technique;
Form the second photoresistance pattern on the surface of The above results, in order to definition p+ doped region position, this p+ doped region position is close to this n+ doped region to constitute two impurity doped regions, in order to the source electrode contact to be provided;
Impose implanting ions for the third time, in order in this epitaxial layer, to form this p+ doped region;
Remove this second photoresistance pattern;
On all surface, form dielectric layer;
Define this dielectric layer with little shadow and etching technique, in order on this groove gate remainder, to form a contact zone and the separator that exposes a groove polysilicon layer and the n+ doped region of cover part;
Impose ion activation heat treatment, so that the impurity activation that cloth is planted;
Upper surface in this epitaxial layer forms the first metal layer comprehensively;
Define this metal level with little shadow and etching technique, in order to definition source metal contact layer and groove gate metal level, this source metal contact layer is formed in this p+ district and this n+ district simultaneously, and this groove gate metal layer contacting is in the contact zone of polysilicon layer;
All oxide layers of removing this n type heavy doping silicon carbide substrate back side are up to exposed this n type heavy doping silicon carbide substrate surface; And
Form the first metal layer on this n type heavy doping silicon carbide substrate surface, this second metal level is the drain as this groove gold oxygen half electric crystal comprehensively.
2. method as claimed in claim 1 is included in before the formation separator step and behind the definition groove gate and imposes the thermal oxidation processing procedure so that the exposed upper surface of this irrigation canals and ditches gate coats first oxide layer.
3. method as claimed in claim 1, wherein above-mentioned gash depth is 0.8-5.0 μ m, and the gate oxide layer thickness is about 50-200nm, and above-mentioned separator is a tetraethoxysilane, and thickness is 0.3-1.0 μ m.
4. method as claimed in claim 1, wherein above-mentioned n type impurity are that nitrogen ion, p type impurity are aluminium ion or boron ion, and above-mentioned ion activation heat treatment temperature is 1400-1600 ℃.
5. method as claimed in claim 1 is included in and imposes heat treatment so that this source metal, drain metal and groove gate metal form the low ohmic contact layer of resistance after the drain Metal Contact defines.
6. groove gold oxygen half electric crystal structure comprises at least:
One silicon carbide substrate, this silicon carbide substrate comprise heavily doped substrate of n type and n type doping impurity epitaxial layer formed thereon;
One is formed in this epitaxial layer and extends to the n type conductive impurity heavily doped region of the upper surface of this epitaxial layer;
One is formed at the groove gate in this epitaxial layer, and this groove gate comprises a gate pole oxidation layer and a compound crystal gate layer, and wherein this compound crystal gate layer protrudes from the upper surface of this epitaxial layer;
One is doped with P-type conduction impurity, and be formed at p-basalis in this epitaxial layer, the sidewall of this p-basalis and this groove gate is separated by with a width, is used to construction one accumulation layer channel region in the sidewall of this groove gate and the epitaxial layer between this p one basalis;
One is formed on this groove gate and the separator of cover part n type conductive impurity heavily doped region;
One is formed in this epitaxial layer, and extends to the p type conductive impurity heavily doped region of the upper surface of this epitaxial layer, and this p type conductive impurity heavily doped region adjoins mutually with this n type conductive impurity heavily doped region and this p-basalis;
One is formed at the source metal contact layer on this n type conductive impurity heavily doped region and this p type conductive impurity heavily doped region simultaneously;
One is formed at the drain metal contact layer at the back side of this silicon carbide substrate.
7. groove gold oxygen half electric crystal structure as claimed in claim 6, the bottom of wherein above-mentioned p-basalis is identical with the bottom degree of depth of this groove gate, and the gate oxide layer thickness is 50-200nm, and separator is a teos layer.
8. groove gold oxygen half electric crystal structure as claimed in claim 6, wherein on the order of magnitude, high 2 to 3 orders of magnitude of n type conductive impurity concentration in this silicon carbide substrate of p type conductive impurity concentration ratio of above-mentioned p-basalis, this accumulation layer channel region width is this groove gate when making alive not, even drain area applies bias voltage, this accumulation layer channel region still is complete exhaustion region.
9. groove gold oxygen half electric crystal structure as claimed in claim 6, wherein above-mentioned source metal contact layer comprises on the separator that is formed at this groove gate, but does not comprise the end of this groove gate, and this end is in order to definition gate contact zone.
10. groove gold oxygen half electric crystal structure as claimed in claim 6, wherein above-mentioned compound crystal gate layer and this gate oxide layer segment are covered on this n type conductive impurity heavily doped region, so that this groove gate protrudes from the width of part of epitaxial layer upper surface greater than the part in this groove.
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| US11804545B2 (en) | 2008-12-25 | 2023-10-31 | Rohm Co., Ltd. | Semiconductor device |
| CN102610643A (en) * | 2011-12-20 | 2012-07-25 | 成都芯源系统有限公司 | Trench MOSFET device |
| CN102610643B (en) * | 2011-12-20 | 2015-01-28 | 成都芯源系统有限公司 | Trench MOSFET device |
| CN105070748A (en) * | 2015-08-31 | 2015-11-18 | 株洲南车时代电气股份有限公司 | Manufacturing method of IGBT grid electrode |
| CN105070748B (en) * | 2015-08-31 | 2019-01-29 | 株洲南车时代电气股份有限公司 | A kind of production method of IGBT grid |
| CN106783568A (en) * | 2016-12-27 | 2017-05-31 | 株洲中车时代电气股份有限公司 | A kind of power device grid curb wall preparation method |
| TWI835394B (en) * | 2022-11-08 | 2024-03-11 | 財團法人工業技術研究院 | Semiconductor device |
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