CN106298530B - A kind of production method and DMOS device of the device active region DMOS - Google Patents
A kind of production method and DMOS device of the device active region DMOS Download PDFInfo
- Publication number
- CN106298530B CN106298530B CN201510295736.0A CN201510295736A CN106298530B CN 106298530 B CN106298530 B CN 106298530B CN 201510295736 A CN201510295736 A CN 201510295736A CN 106298530 B CN106298530 B CN 106298530B
- Authority
- CN
- China
- Prior art keywords
- area
- layer
- grid
- groove
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 56
- 239000002184 metal Substances 0.000 claims abstract description 56
- 238000000407 epitaxy Methods 0.000 claims abstract description 51
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 44
- 229920005591 polysilicon Polymers 0.000 claims abstract description 44
- 238000005530 etching Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 6
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 6
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 239000010936 titanium Substances 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 10
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- 239000010941 cobalt Substances 0.000 claims description 5
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 11
- 238000011084 recovery Methods 0.000 abstract description 10
- 230000005684 electric field Effects 0.000 abstract description 9
- 230000000903 blocking effect Effects 0.000 abstract description 5
- 238000003860 storage Methods 0.000 abstract description 3
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 229910000531 Co alloy Inorganic materials 0.000 description 2
- 229910000990 Ni alloy Inorganic materials 0.000 description 2
- 229910001260 Pt alloy Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910001069 Ti alloy Inorganic materials 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000001172 regenerating effect Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Manufacturing & Machinery (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The embodiment of the invention discloses the production method of the device active region double-diffused metal oxide semiconductor DMOS and DMOS devices.By forming the polysilicon layer of N-type epitaxy layer, gate oxide and doping in N-type substrate in the embodiment of the present invention, and form area of grid and groove；The area PXing Ti is formed in the N-type epitaxy layer, and N-type source region is formed in the area PXing Ti；Etching forms Schottky contact area；Deposited metal forms Schottky contact region in Schottky contact area, forms source electrode and drain electrode.Metal layer and N-type epitaxy layer is made to form Schottky contact region in the embodiment of the present invention.When DMOS device work in forward conduction, reduce the storage charge and reverse recovery charge in drift region；When DMOS device is in reverse blocking state, the electric field of Schottky contacts is reduced, improve Schottky contacts breakdown voltage and reduces leakage current, the breakdown voltage and electric leakage when DMOS device being made to meet application require.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to the production methods and DMOS device of a kind of device active region DMOS
Part.
Background technique
DMOS device is a kind of MOSFET that transistor area is formed using diffusion.MOSFET is widely applied power
Switching device, with the high and low loss of input impedance, switching speed it is fast, without second breakdown, safety operation area is wide, dynamic property
The advantages that good.
In the more existing power switch circuit for requiring reverse current to flow through active switching devices, MOSFET must be anti-
To conducting, for example, being used for the direct current of speed regulating motor driving to the inverter switching device power supply of exchange, and it to be used for Motor Control
, the DC converter with regenerative braking etc..
However, the service life of the drift region of the MOSFET element of traditional handicraft manufacture is long, and have in p-well region a large amount of anti-
To recovery charge, cause reverse recovery time longer.When power MOSFET is used to that reverse current is required to flow through active switch device
When device for power switching in the power switch circuit of part, since its Reverse recovery is very slow, it is easy to cause power device to fail,
The phenomenon that even damaging circuit.
To sum up, in frequency applications, using DMOS device made by the prior art since reverse recovery time is longer, table
Reveal lower switching speed, leads to various unfavorable conditions occur.
Summary of the invention
The embodiment of the present invention provides the production method and DMOS device of a kind of device active region DMOS, to solve using existing
There is DMOS device made by technology since reverse recovery time is longer, show lower switching speed, causes to occur various
The technical issues of unfavorable condition.
A kind of production method of device active region DMOS provided in an embodiment of the present invention, comprising:
N-type epitaxy layer, gate oxide and the polysilicon layer of doping are sequentially formed in N-type substrate；
The polysilicon layer and the gate oxide of the doping are etched, area of grid and groove are formed；The area of grid
The polysilicon layer of the doping between adjacent grooves and the gate oxide below the polysilicon layer of the doping；
Injecting p-type ion forms the area PXing Ti in the corresponding N-type epitaxy layer of the groove；
Injection N-type ion forms N-type source region in the area PXing Ti；
An area of grid between the groove is at least etched, Schottky contact area is formed；
The first metal layer is deposited, forms Schottky contact region in the Schottky contact area；
Form source electrode and drain electrode.
Preferably, the polysilicon layer and the gate oxide of the etching doping, form area of grid and groove, packet
It includes:
Form the multiple area of grid and multiple grooves being arranged alternately；
Two grooves adjacent in the multiple groove are included into one group, each groove only belongs to one group；
An area of grid between the groove is at least etched, Schottky contact area is formed, comprising:
The area of grid between every group of groove is etched, Schottky contact area is formed.
Preferably, the area of grid at least etched between the groove, forms before Schottky contact area, packet
It includes:
Dielectric layer deposited；
The area of grid at least etched between the groove forms Schottky contact area, comprising:
The dielectric layer is etched to the N-type epitaxy layer, forms source contact regions and Schottky contact area；
The first metal layer forms source electrode in the source contact regions.
Preferably, the deposit the first metal layer, after the Schottky contact area forms Schottky contact region, packet
It includes:
Second metal layer is deposited on the first metal layer；
In the N-type substrate backwards to the one outgrowth third metal layer of N-type epitaxy layer, drain electrode is formed.
Preferably, the polysilicon layer and the gate oxide of the etching doping, form groove, comprising:
Mask layer is deposited on the polysilicon layer of the doping；
Determine the region for needing to form the groove；
The mask layer of the recess region is performed etching, so that forming initial groove on mask layer；
The polysilicon layer and the gate oxide of the doping of the initial recess region are etched, groove is formed.
Preferably, described sequentially form N-type epitaxy layer, gate oxide and the polysilicon layer of doping, packet in N-type substrate
It includes:
Initial oxide layer is grown in the N-type epitaxy layer；
Remove the initial oxide layer of the active area region.
The embodiment of the present invention provides a kind of double-diffused metal oxide semiconductor DMOS device, including termination environment and active
Area, the active area include at least:
The N-type epitaxy layer being set in the N-type substrate is formed with the area PXing Ti in the N-type epitaxy layer and is located at described
N-type source region in the area PXing Ti；
The area of grid being set in the N-type epitaxy layer；Two adjacent area of grid constitute a grid group, at least
Schottky contact region is provided between two area of grid in one grid group；
The first metal layer that is set on the N-type epitaxy layer and the area of grid and it is set to the gate regions
Dielectric layer between domain and the first metal layer；The first metal layer forms source electrode in the N-type source region, and described first
Metal layer forms Schottky contact region in the Schottky contact area.
Preferably, being provided with Schottky contact region between two area of grid in each grid group.
Preferably, further include:
The second metal layer being set on the first metal layer；The N-type substrate is set to backwards to the N-type epitaxy layer
The third metal layer of side forms drain electrode.
Preferably, the first metal layer is the alloy of nickel, cobalt, titanium, platinum or any combination thereof.
By forming the polysilicon layer of N-type epitaxy layer, gate oxide and doping in N-type substrate in the embodiment of the present invention,
The polysilicon layer and the gate oxide of the doping are etched, area of grid and groove are formed, the area of grid is adjacent recessed
The polysilicon layer of the doping between slot and the gate oxide below the polysilicon layer of the doping；To the groove
Injecting p-type ion forms the area PXing Ti in the N-type epitaxy layer；To groove injection N-type ion in the area PXing Ti
Form N-type source region；An area of grid between the groove is at least etched, Schottky contact area is formed；Deposited metal,
The Schottky contact area forms Schottky contact region, forms source electrode and drain electrode.N is being injected to groove in the embodiment of the present invention
During type ion forms N-type source region, light shield is omitted, by the way of inject comprehensively, so as to lead in the next steps
At least one area of grid of etching is crossed, so that metal layer and N-type epitaxy layer form Schottky contact region.When the work of DMOS device exists
When forward conduction, Schottky contact region and diode region are shunted, and form majority carrier electric current, therefore reduce in drift region
Store charge and reverse recovery charge；When DMOS device is in reverse blocking state, Schottky contact region is by adjacent P
The electric field in the area Xing Ti is protected, and since the depletion layer in the adjacent area PXing Ti extends, the schottky junctions contacting surface area Xia N- is by pinch off, therefore
The electric field for reducing Schottky contacts improves Schottky contacts breakdown voltage and reduces leakage current, to make this structure
Breakdown voltage and electric leakage when DMOS device meets application require.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly introduced, it should be apparent that, drawings in the following description are only some embodiments of the invention, for this
For the those of ordinary skill in field, without any creative labor, it can also be obtained according to these attached drawings
His attached drawing.
Fig. 1 is process signal corresponding to a kind of production method of the device active region DMOS provided in an embodiment of the present invention
Figure；
Structural schematic diagram in Fig. 2-Fig. 8 device active region DMOS manufacturing process provided in an embodiment of the present invention.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with attached drawing to the present invention make into
It is described in detail to one step, it is clear that described embodiments are only a part of the embodiments of the present invention, rather than whole implementation
Example.Based on the embodiments of the present invention, obtained by those of ordinary skill in the art without making creative efforts
All other embodiment, shall fall within the protection scope of the present invention.
Fig. 1 is process signal corresponding to a kind of production method of the device active region DMOS provided in an embodiment of the present invention
Figure, this method comprises:
Step 101, N-type epitaxy layer, gate oxide and the polysilicon layer of doping are sequentially formed in N-type substrate；
Step 102, the polysilicon layer and the gate oxide of the doping are etched, area of grid and groove are formed；It is described
The polysilicon layer and the grid below the polysilicon layer of the doping of the doping of the area of grid between adjacent grooves
Oxide layer；
Step 103, injecting p-type ion forms the area PXing Ti in the corresponding N-type epitaxy layer of the groove；
Step 104, injection N-type ion forms N-type source region in the area PXing Ti；
Step 105, an area of grid between the groove is at least etched, Schottky contact area is formed；
Step 106, the first metal layer is deposited, forms Schottky contact region in the Schottky contact area；
Step 107, source electrode and drain electrode is formed.
DMOS device in the embodiment of the present invention includes active area and termination environment, in step 101, in N-type substrate successively
Form the polysilicon layer of N-type epitaxy layer, gate oxide and doping, comprising: grow initial oxide layer in the N-type epitaxy layer；
The initial oxide layer for removing the active area region retains the initial oxide layer of the terminal region.
Specifically, in a step 102, the polysilicon layer and the gate oxide of the doping are etched, groove, packet are formed
It includes: depositing mask layer on the polysilicon layer of the doping；Determine the region for needing to form the groove；To the recess region
Mask layer perform etching so that forming initial groove on mask layer；Etch the more of the doping of the initial recess region
Crystal silicon layer and the gate oxide form groove.
Preferably, in a step 102, by etching the polysilicon layer and the gate oxide of the doping, forming alternating
The multiple area of grid and multiple grooves being arranged；Two grooves adjacent in the multiple groove are included into one group, each groove
Only belong to one group；Correspondingly, in step 105, an area of grid between the groove is at least etched, Schottky contacts are formed
Region, comprising: etch the area of grid between every group of groove, form Schottky contact area.
In the embodiment of the present invention, before step 105, the area of grid at least etched between the groove, shape
Before Schottky contact area, further includes: one layer of dielectric layer of deposit；Correspondingly, in step 105, described at least to etch institute
It states an area of grid between groove, forms Schottky contact area, comprising: etch the dielectric layer to the N-type epitaxy layer,
Form source contact regions and Schottky contact area；Wherein, the first metal layer forms source electrode in the source contact regions.
Further, the first metal layer is deposited in step 106, forms Schottky contacts in the Schottky contact area
After area, further includes: deposit second metal layer on the first metal layer；In the N-type substrate backwards to the N-type epitaxy layer side
Third metal layer is deposited, drain electrode is formed.
By forming the polysilicon layer of N-type epitaxy layer, gate oxide and doping in N-type substrate in the embodiment of the present invention,
The polysilicon layer and the gate oxide of the doping are etched, area of grid and groove are formed, the area of grid is adjacent recessed
The polysilicon layer of the doping between slot and the gate oxide below the polysilicon layer of the doping；To the groove
Injecting p-type ion forms the area PXing Ti in the N-type epitaxy layer；To groove injection N-type ion in the area PXing Ti
Form N-type source region；An area of grid between the groove is at least etched, Schottky contact area is formed；Deposited metal,
The Schottky contact area forms Schottky contact region, forms source electrode and drain electrode.N is being injected to groove in the embodiment of the present invention
During type ion forms N-type source region, light shield is omitted, by the way of inject comprehensively, so as to lead in the next steps
At least one area of grid of etching is crossed, so that metal layer and N-type epitaxy layer form Schottky contact region.When the work of DMOS device exists
When forward conduction, Schottky contact region and diode region are shunted, and form majority carrier electric current, therefore reduce in drift region
Store charge and reverse recovery charge；When DMOS device is in reverse blocking state, Schottky contact region is by adjacent P
The electric field in the area Xing Ti is protected, and since the depletion layer in the adjacent area PXing Ti extends, the schottky junctions contacting surface area Xia N- is by pinch off, therefore
The electric field for reducing Schottky contacts improves Schottky contacts breakdown voltage and reduces leakage current, to make this structure
Breakdown voltage and electric leakage when DMOS device meets application require.
For a clearer understanding of the present invention, it is described in detail combined with specific embodiments below.
It should be noted that being only the processing mode between two adjacent grooves described in the embodiment.However, this hair
It is not limited in bright embodiment between two adjacent grooves and forms Schottky contact region, for example, it can be to non-conterminous
Two grooves are handled, to form one or more Schottky contact region between non-conterminous two grooves.
As shown in Fig. 2, forming N-type epitaxy layer 202 in N-type substrate 201；Initial oxidation is grown in N-type epitaxy layer 202
Layer 203.
DMOS device in the embodiment of the present invention includes that active area and termination environment are beaten after initial oxide layer 203 is grown
It is provided with source region, peels the initial oxide layer of active area off, retains the initial oxide layer of termination environment.The embodiment of the present invention is directed to active area
Production method improve, for ease of description, omitting terminal plot structure herein and in subsequent step.
As shown in figure 3, growing one layer of gate oxide 204 for playing insulating effect, gate oxide 204 in N-type epitaxy layer 202
Material can be silica, then on gate oxide 204 grow one layer be used as grid doping polysilicon layer 205.
As shown in figure 4, depositing mask layer on the polysilicon layer 205 of doping, the region for needing to form groove is determined, it is right
The mask layer of recess region performs etching, so that forming initial groove on mask layer, exposes the polysilicon layer of doping；To doping
Polysilicon layer and gate oxide perform etching, and are etched to N-type epitaxy layer 202, and remove the exposure mask on the polysilicon layer 205 of doping
Layer forms area of grid 2061, area of grid 2062, area of grid 2063 and groove 2071, groove 2072.
In the embodiment of the present invention, during forming groove, the polysilicon layer of doping can also be only etched to gate oxidation
Layer, to etch away the gate oxide of bottom portion of groove during subsequent etching dielectric layer.The embodiment of the present invention does not do this
Concrete restriction.
As shown in figure 5, to groove 2071,2072 injecting p-type ion of groove, and driven in, and then in N-type epitaxy layer
The area PXing Ti 209 is formed in 202, is injected N-type ion to groove 2071, groove 2072, and is carried out annealing process, and then in p-type body
N-type source region 210 is formed in area 209.Wherein, N-type source region 210 is N-type heavily doped region.
In the embodiment of the present invention, during injecting N-type ion formation N-type source region to groove 2071, groove 2072, save
Slightly light shield at least etches an area of grid by the way of inject comprehensively so as to pass through in the next steps, so that golden
Belong to layer and N-type epitaxy layer forms Schottky contact region.
As shown in fig. 6, dielectric layer deposited 211.
As shown in fig. 7, passing through certain media layer, the groove 2071 of 2072 region of chemical wet etching groove 2071 and groove
Area of grid between groove 2072 and the dielectric layer on the area of grid, formed Schottky contact area 212 with
And source contact region 213.
Optionally, if remaining with gate oxide during above-mentioned etching forms groove, then should pass through in this step
The certain media of 2072 region of gate oxide, groove 2071 and groove of 2072 bottom of chemical wet etching groove 2071 and groove
Area of grid between layer, groove 2071 and groove 2072 and the dielectric layer on the area of grid.
It should be noted that in this embodiment it is that then chemical wet etching forms Xiao Te by first depositing one layer of dielectric layer
Base contact area, however it's not limited to that for the embodiment of the present invention, for example, it is also possible to after forming N-type source region 210, just into
Row chemical wet etching removes the area of grid between groove 2071 and groove 2072, then deposits one layer of dielectric layer, and to the medium
Layer performs etching, and then forms Schottky contact area 212.Comparatively, in former embodiment, primary light need to only be carried out
Etching, just forms Schottky contact area, simple process has saved the cost of manufacture of device, and latter embodiment is then
Twi-lithography etching need to be carried out, it is complex.Therefore in the embodiment of the present invention, preferably first dielectric layer deposited, then chemical wet etching shape
At the embodiment of Schottky contact area.
As shown in figure 8, deposit the first metal layer 214 and second metal layer 215, the first metal layer 214 is in Schottky contacts
Region 212 forms Schottky contact region, forms source electrode in source contact region 213.In N-type substrate 201 backwards to N-type epitaxy layer
A 202 outgrowth third metal layer 216 forms drain electrode.
Preferably, the metal layer 214 in the embodiment of the present invention be nickel, cobalt, titanium, platinum or any combination thereof alloy so as to
It is enough to form Schottky diode in Schottky contact area, when the work of DMOS device is in forward conduction, Schottky contact region with
Diode region shunts, and forms majority carrier electric current, reduces the storage charge and reverse recovery charge in drift region；When
When DMOS device is in reverse blocking state, Schottky contact region is protected by the electric field in the adjacent area PXing Ti, due to adjacent p-type
The depletion layer in body area extends, and the area schottky junctions contacting surface Xia N- reduces the electric field of Schottky contacts by pinch off, improves
Schottky contacts breakdown voltage and reduce leakage current, thus breakdown voltage when the DMOS device of this structure being made to meet application and
Electric leakage requires.
The embodiment of the present invention provides a kind of double-diffused metal oxide semiconductor DMOS device, including termination environment and active
Area, wherein the active area includes at least:
The N-type epitaxy layer being set in the N-type substrate is formed with the area PXing Ti in the N-type epitaxy layer and is located at described
N-type source region in the area PXing Ti；
The area of grid being set in the N-type epitaxy layer；Two adjacent area of grid constitute a grid group, at least
Schottky contact region is provided between two area of grid in one grid group；
The first metal layer that is set on the N-type epitaxy layer and the area of grid and it is set to the gate regions
Dielectric layer between domain and the first metal layer；The first metal layer forms source electrode in the N-type source region, and described first
Metal layer forms Schottky contact region in the Schottky contact area.
Preferably, being provided with Schottky contact region between two area of grid in each grid group.
Preferably, further include:
The second metal layer being set on the first metal layer；The N-type substrate is set to backwards to the N-type epitaxy layer
The third metal layer of side forms drain electrode.
Preferably, the first metal layer is the alloy of nickel, cobalt, titanium, platinum or any combination thereof.
It can be seen from the above: by forming N-type epitaxy layer, gate oxidation in N-type substrate in the embodiment of the present invention
The polysilicon layer of layer and doping etches the polysilicon layer and the gate oxide of the doping, forms area of grid and groove, institute
State the polysilicon layer of the doping of the area of grid between adjacent grooves and below the polysilicon layer of the doping described in
Gate oxide；The area PXing Ti is formed in the N-type epitaxy layer to the groove injecting p-type ion；N-type is injected to the groove
Ion forms N-type source region in the area PXing Ti；An area of grid between the groove is at least etched, schottky junctions are formed
Touch region；Deposited metal forms Schottky contact region in the Schottky contact area, forms source electrode and drain electrode.The present invention
In embodiment during forming N-type source region to groove injection N-type ion, light shield is omitted, by the way of inject comprehensively, from
And it can be in the next steps by least etching an area of grid, so that metal layer and N-type epitaxy layer form schottky junctions
Touch area.When the work of DMOS device is in forward conduction, Schottky contact region and diode region are shunted, and form majority carrier electricity
Stream, therefore reduce the storage charge and reverse recovery charge in drift region；When DMOS device is in reverse blocking state
When, Schottky contact region is protected by the electric field in the adjacent area PXing Ti, since the depletion layer in the adjacent area PXing Ti extends, schottky junctions
The area contacting surface Xia N- reduces the electric field of Schottky contacts by pinch off, improves Schottky contacts breakdown voltage and reduction
Leakage current, so that the breakdown voltage and electric leakage when the DMOS device of this structure being made to meet application require.
Although preferred embodiments of the present invention have been described, it is created once a person skilled in the art knows basic
Property concept, then additional changes and modifications may be made to these embodiments.So it includes excellent that the following claims are intended to be interpreted as
It selects embodiment and falls into all change and modification of the scope of the invention.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (8)
1. a kind of production method of the device active region double-diffused metal oxide semiconductor DMOS characterized by comprising
N-type epitaxy layer is formed in N-type substrate, initial oxide layer is grown in the N-type epitaxy layer, and remove active area region
The initial oxide layer, retain terminal region gate oxide；The polysilicon layer of doping is grown on the gate oxide；
The polysilicon layer and the gate oxide of the doping are etched, area of grid and groove are formed；The area of grid is phase
The polysilicon layer of the doping between adjacent groove and the gate oxide below the polysilicon layer of the doping；
Injecting p-type ion forms the area PXing Ti in the corresponding N-type epitaxy layer of the groove；
Injection N-type ion forms N-type source region in the area PXing Ti；
Dielectric layer deposited in the groove and on the area of grid etches an area of grid between the groove, described
The dielectric layer in dielectric layer and the groove on area of grid forms Schottky contact area；
The first metal layer is deposited, forms Schottky contact region in the Schottky contact area；The first metal layer be nickel,
Cobalt, titanium, any one in platinum or any multinomial combined alloy；
Form source electrode and drain electrode.
2. the method as described in claim 1, which is characterized in that the polysilicon layer and the gate oxidation of the etching doping
Layer forms area of grid and groove, comprising:
Form the multiple area of grid and multiple grooves being arranged alternately；
Two grooves adjacent in the multiple groove are included into one group, each groove only belongs to one group；
An area of grid between the groove is at least etched, Schottky contact area is formed, comprising:
The area of grid between every group of groove is etched, Schottky contact area is formed.
3. method according to claim 1 or 2, which is characterized in that an area of grid, institute between the etching groove
State the dielectric layer in the dielectric layer and the groove on area of grid, comprising:
The dielectric layer is etched to the N-type epitaxy layer, forms source contact regions and Schottky contact area；
The first metal layer forms source electrode in the source contact regions.
4. the method as described in claim 1, which is characterized in that the deposit the first metal layer, in the Schottky contact region
Domain is formed after Schottky contact region, comprising:
Second metal layer is deposited on the first metal layer；
In the N-type substrate backwards to the one outgrowth third metal layer of N-type epitaxy layer, drain electrode is formed.
5. the method as described in claim 1, which is characterized in that the polysilicon layer and the gate oxidation of the etching doping
Layer forms groove, comprising:
Mask layer is deposited on the polysilicon layer of the doping；
Determine the region for needing to form the groove；
The mask layer of the recess region is performed etching, so that forming initial groove on mask layer；
The polysilicon layer and the gate oxide of the doping of the initial recess region are etched, groove is formed.
6. a kind of double-diffused metal oxide semiconductor DMOS device, including termination environment and active area, which is characterized in that described double
Diffused metal oxide emiconductor DMOS device passes through production method system described in any one of claims 1 to 5
It forms, the active area includes at least:
The N-type epitaxy layer being set in the N-type substrate is formed with the area PXing Ti in the N-type epitaxy layer and is located at the p-type
N-type source region in body area；
The area of grid being set in the N-type epitaxy layer；Two adjacent area of grid constitute a grid group, at least one
Schottky contact region is provided between two area of grid in grid group；
The first metal layer that is set on the N-type epitaxy layer and the area of grid and be set to the area of grid and
Dielectric layer between the first metal layer；The first metal layer is nickel, cobalt, titanium, any one in platinum or any multinomial
Combined alloy；The first metal layer forms source electrode in the N-type source region, and the first metal layer is in the schottky junctions
It touches region and forms Schottky contact region.
7. DMOS device as claimed in claim 6, which is characterized in that be respectively provided between two area of grid in each grid group
There is Schottky contact region.
8. DMOS device as claimed in claim 6, which is characterized in that further include:
The second metal layer being set on the first metal layer；The N-type substrate is set to backwards to the N-type epitaxy layer side
Third metal layer, formed drain electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510295736.0A CN106298530B (en) | 2015-06-02 | 2015-06-02 | A kind of production method and DMOS device of the device active region DMOS |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510295736.0A CN106298530B (en) | 2015-06-02 | 2015-06-02 | A kind of production method and DMOS device of the device active region DMOS |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106298530A CN106298530A (en) | 2017-01-04 |
| CN106298530B true CN106298530B (en) | 2019-08-30 |
Family
ID=57656527
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510295736.0A Active CN106298530B (en) | 2015-06-02 | 2015-06-02 | A kind of production method and DMOS device of the device active region DMOS |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106298530B (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7208785B2 (en) * | 2004-12-20 | 2007-04-24 | Silicon-Based Technology Corp. | Self-aligned Schottky-barrier clamped planar DMOS transistor structure and its manufacturing methods |
-
2015
- 2015-06-02 CN CN201510295736.0A patent/CN106298530B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN106298530A (en) | 2017-01-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110061050B (en) | Semiconductor device and insulated gate bipolar transistor with barrier region | |
| CN105074921B (en) | Semiconductor device | |
| US10475896B2 (en) | Silicon carbide MOSFET device and method for manufacturing the same | |
| CN103208531B (en) | Fast recovery diode (FRD) chip and manufacturing method for FRD chip | |
| CN106783851B (en) | SiCJFET device integrated with Schottky diode and manufacturing method thereof | |
| CN102723363B (en) | A kind of VDMOS device and preparation method thereof | |
| CN111403486B (en) | Groove type MOSFET structure and manufacturing method thereof | |
| CN107507861B (en) | Schottky contact injection enhanced SiC PNM-IGBT device and preparation method thereof | |
| KR20090031194A (en) | Semiconductor device | |
| US11342433B2 (en) | Silicon carbide devices, semiconductor devices and methods for forming silicon carbide devices and semiconductor devices | |
| CN109686781A (en) | A kind of superjunction devices production method of multiple extension | |
| CN105070663B (en) | Silicon carbide MOSFET channel self-alignment process implementation method | |
| CN102184945A (en) | Groove gate type MOSFET device | |
| CN103855206A (en) | Insulated gate bipolar transistor and manufacturing method thereof | |
| CN111129163A (en) | Schottky diode and preparation method thereof | |
| CN104409334A (en) | Method for preparing super junction device | |
| CN111509034A (en) | Field effect transistor with same gate source doping, cell structure and preparation method | |
| CN104253154A (en) | IGBT (insulated gate bipolar transistor) with inlaid diode and manufacturing method of IGBT | |
| CN104253042A (en) | Manufacturing method of IGBT (insulated gate bipolar transistor) | |
| CN106298530B (en) | A kind of production method and DMOS device of the device active region DMOS | |
| CN107342224B (en) | Manufacturing method of VDMOS device | |
| CN206672934U (en) | The SiCJFET devices of integrated schottky diode | |
| CN202917494U (en) | A field stop buffer layer and an IGBT device containing the field stop buffer layer | |
| CN107452623B (en) | Manufacturing method of fast recovery diode and fast recovery diode | |
| CN108258040A (en) | Igbt with wide band gap semiconducter substrate material and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220725 Address after: 518116 founder Microelectronics Industrial Park, No. 5, Baolong seventh Road, Baolong Industrial City, Longgang District, Shenzhen, Guangdong Province Patentee after: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. Address before: 100871, Beijing, Haidian District Cheng Fu Road 298, founder building, 5 floor Patentee before: PEKING UNIVERSITY FOUNDER GROUP Co.,Ltd. Patentee before: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. |