CN106209070A - A kind of phase discriminator based on sense amplifier D-flip flop - Google Patents
A kind of phase discriminator based on sense amplifier D-flip flop Download PDFInfo
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- CN106209070A CN106209070A CN201610627409.5A CN201610627409A CN106209070A CN 106209070 A CN106209070 A CN 106209070A CN 201610627409 A CN201610627409 A CN 201610627409A CN 106209070 A CN106209070 A CN 106209070A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
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Abstract
The invention discloses a kind of phase discriminator based on sense amplifier D-flip flop, it includes igniter module, reseting module, latch module and phase error output module, igniter module receive reference clock and feedback clock and export corresponding trigger output signal to reseting module, latch module and phase error output module；Reseting module exports reseting controling signal control trigger module resets according to reset signal and the trigger output signal of input；Latch module is according to trigger output signal output phase error direction signal；Phase error output module is according to trigger output signal and phase error direction signal output phase error initial signal and phase error termination signal, phase error signal is obtained according to described phase error initial signal and phase error termination signal, can effectively eliminate the dependence that trigger is set up the time, improve the timing performance of phase discriminator, two signals are used to represent phase error, it is possible to be effectively improved the accuracy of phase discriminator.
Description
Technical field
The present invention relates to phase discriminator technical field, particularly to a kind of phase discriminator based on sense amplifier D-flip flop.
Background technology
Phase discriminator (Phase Detector) be again phase comparator, it is possible to detects the phase error of input signal, defeated
Go out the circuit of the phase error signal that a magnitude of voltage represents.It is the important of phase-locked loop pll (Phase-locked Loop)
Ingredient, is used for extracting phase error signal.Existing phase discriminator can be divided into analogue phase detection device and digital phase discriminator two class,
Digital phase discriminator is made up of digital logic gate, and area low power consumption is low, is susceptible to PVT impact, has therefore obtained wider application.
As it is shown in figure 1, flop phase discriminator is a kind of common digital phase discriminator, reference clock and feedback clock are connected on
The clock end of two triggers, the input termination VDD of trigger.In the ideal situation, when reference rising edge clock is prior to feedback
When rising edge clock arrives trigger, the UP signal of trigger A output is high level, until feedback clock rising edge arrives, B touches
The output DN sending out device also becomes high level, UP and DN phase with " 1 ", trigger reset signal is effective, two trigger resets, UP
All become low level again with DN, vice versa.Therefore, when with reference to clock phase advanced feedback clock phase place, UP is phase error letter
Number, DN is reset signal；When lagging behind frequency divider output clock phase with reference to clock phase, DN output is phase error,
UP is reset signal.The output waveform of phase discriminator is as shown in Figure 2.
Existing digital phase discriminator all does improvement on this circuit base and realizes.This phase demodulation based on flop
It is very big that device is set up time effects by trigger, only when sequential be required to meet trigger set up the time time, phase discriminator could be defeated
Go out correct phase error, additionally, because trigger exists internal delay time, UP and DN always produces an of short duration pulse letter
Number, therefore the phase error length represented by UP and DN is always long than actual phase error length.
Thus prior art could be improved and improve.
Summary of the invention
In place of above-mentioned the deficiencies in the prior art, it is an object of the invention to provide a kind of tactile based on sense amplifier type
Send out the phase discriminator of device, it is possible to effectively eliminate the dependence that trigger is set up the time, improve the timing performance of phase discriminator, use two
Individual signal represents phase error, it is also possible to effectively improve the accuracy of phase discriminator.
In order to achieve the above object, this invention takes techniques below scheme:
A kind of phase discriminator based on sense amplifier D-flip flop, it include igniter module, reseting module, latch module and
Phase error output module, is received reference clock and feedback clock by igniter module and exports corresponding trigger output signal extremely
Reseting module, latch module and phase error output module；Reseting module is defeated according to reset signal and the described triggering of input
Go out signal output reseting controling signal control trigger module resets；Latch module exports phase according to described trigger output signal
Position direction of error signal is to phase error output module；Phase error output module misses according to described trigger output signal and phase place
Difference direction signal output phase error initial signal and phase error termination signal, according to described phase error initial signal and phase
Position error termination signal obtains phase error signal.
In described phase discriminator based on sense amplifier D-flip flop, described igniter module includes the first sensitive amplification
Type trigger and the second sense amplifier D-flip flop, described first sense amplifier D-flip flop is used for receiving reference clock
And export the first trigger output signal；Described second sense amplifier D-flip flop is used for receiving feedback clock and exporting second touching
Send out output signal.
In described phase discriminator based on sense amplifier D-flip flop, described first sense amplifier D-flip flop and
The circuit structure of two sense amplifier D-flip flops is identical, and described first sense amplifier D-flip flop includes CK end, D
End,End, Q end,End, Rst end andEnd, also includes charge amplifying unit and latch units；
Wherein, described charging amplifying unit includes the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the 5th MOS
Pipe, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor, the 9th metal-oxide-semiconductor, the tenth metal-oxide-semiconductor, the 11st metal-oxide-semiconductor, the 12nd metal-oxide-semiconductor,
13rd metal-oxide-semiconductor, the 14th metal-oxide-semiconductor, the 15th metal-oxide-semiconductor, the 16th metal-oxide-semiconductor, the first output node and the second output node；
The grid of described first metal-oxide-semiconductor connectsEnd, the drain electrode of the first metal-oxide-semiconductor connects the first output node, the first metal-oxide-semiconductor
Source electrode connects Vdd terminal；
The grid of described second metal-oxide-semiconductor connects Vss end, and the drain electrode of the second metal-oxide-semiconductor connects the first output node, the second metal-oxide-semiconductor
Source electrode connects Vdd terminal；
The grid of described 3rd metal-oxide-semiconductor connects Rst end, and the drain electrode of the 3rd metal-oxide-semiconductor connects the second output node, the 3rd metal-oxide-semiconductor
Source electrode connects Vdd terminal；
The grid of described 4th metal-oxide-semiconductor connects Vdd terminal, and the drain electrode of the 4th metal-oxide-semiconductor connects the second output node, the 4th metal-oxide-semiconductor
Source electrode connects Vdd terminal；
The grid of described 5th metal-oxide-semiconductor connects CK end, and the drain electrode of the 5th metal-oxide-semiconductor connects the first output node, the source of the 5th metal-oxide-semiconductor
Pole connects the first output node；
The grid of described 6th metal-oxide-semiconductor connects the second output node, and the drain electrode of the 6th metal-oxide-semiconductor connects the first output node, and the 6th
The source electrode of metal-oxide-semiconductor connects the first output node；
The grid of described 7th metal-oxide-semiconductor connects the first output node, and the drain electrode of the 7th metal-oxide-semiconductor connects the second output node, and the 7th
The source electrode of metal-oxide-semiconductor connects the second output node；
The grid of described 8th metal-oxide-semiconductor connects CK end, and the drain electrode of the 8th metal-oxide-semiconductor connects the second output node, the source of the 8th metal-oxide-semiconductor
Pole connects the second output node；
The grid of described 9th metal-oxide-semiconductor connects Vss end, and the drain electrode of the 9th metal-oxide-semiconductor connects the first output node, the 9th metal-oxide-semiconductor
Source ground；
The grid of described tenth metal-oxide-semiconductor connects the second output node, and the drain electrode of the tenth metal-oxide-semiconductor connects the first output node, and the tenth
The source electrode of metal-oxide-semiconductor connects drain electrode and the source electrode of the 14th metal-oxide-semiconductor of the 13rd metal-oxide-semiconductor；
The grid of described 11st metal-oxide-semiconductor connects the first output node, and the drain electrode of the 11st metal-oxide-semiconductor connects the second output node,
The source electrode of the 11st metal-oxide-semiconductor connects drain electrode and the drain electrode of the 14th metal-oxide-semiconductor of the 15th metal-oxide-semiconductor；
The grid of described 12nd metal-oxide-semiconductor connects Rst end, and the drain electrode of the 12nd metal-oxide-semiconductor connects the second output node, and the 12nd
The source ground of metal-oxide-semiconductor；
The grid of described 13rd metal-oxide-semiconductor connects D end, and the source electrode of the 13rd metal-oxide-semiconductor connects the drain electrode of the 16th metal-oxide-semiconductor；
The grid of described 14th metal-oxide-semiconductor connects Vdd terminal；
The grid of described 15th metal-oxide-semiconductor connectsEnd, the source electrode of the 15th metal-oxide-semiconductor connects the drain electrode of the 16th metal-oxide-semiconductor；
The grid of described 16th metal-oxide-semiconductor connects CK end, the source ground of the 16th metal-oxide-semiconductor；
Wherein, described latch units include the 17th metal-oxide-semiconductor, the 18th metal-oxide-semiconductor, the 19th metal-oxide-semiconductor, the 20th metal-oxide-semiconductor, second
11 metal-oxide-semiconductors, the 22nd metal-oxide-semiconductor, the 23rd metal-oxide-semiconductor, the 24th metal-oxide-semiconductor, the 25th metal-oxide-semiconductor, the 26th MOS
Pipe, the 27th metal-oxide-semiconductor, the 28th metal-oxide-semiconductor, the 29th metal-oxide-semiconductor and the 30th metal-oxide-semiconductor；
The grid of described 17th metal-oxide-semiconductor connects the first output node, and the drain electrode of the 17th metal-oxide-semiconductor connects Q end, the 17th MOS
The source electrode of pipe connects Vdd terminal；
The grid of described 18th metal-oxide-semiconductor connectsEnd, the drain electrode of the 18th metal-oxide-semiconductor connects Q end, the source electrode of the 18th metal-oxide-semiconductor
Connect Vdd terminal；
The grid of described 19th metal-oxide-semiconductor connects Q end, and the drain electrode of the 19th metal-oxide-semiconductor connectsEnd, the source electrode of the 19th metal-oxide-semiconductor
Connect Vdd terminal；
The grid of described 20th metal-oxide-semiconductor connects the second output node, and the drain electrode of the 20th metal-oxide-semiconductor connectsEnd, the 20th MOS
The source electrode of pipe connects Vdd terminal；
The grid of described 21st metal-oxide-semiconductor connects CK end, and the drain electrode of the 21st metal-oxide-semiconductor connects Q end, the 21st metal-oxide-semiconductor
Source electrode connect the 22nd metal-oxide-semiconductor drain electrode；
The grid of described 22nd metal-oxide-semiconductor connectsEnd, the source electrode of the 22nd metal-oxide-semiconductor connects the leakage of the 29th metal-oxide-semiconductor
Pole and the source electrode of the 26th metal-oxide-semiconductor；
The grid of described 23rd metal-oxide-semiconductor connects CK end, and the drain electrode of the 23rd metal-oxide-semiconductor connectsEnd, the 23rd metal-oxide-semiconductor
Source electrode connect the 24th metal-oxide-semiconductor drain electrode；
The grid of described 24th metal-oxide-semiconductor connects D end, the source electrode of the 24th metal-oxide-semiconductor connect the 30th metal-oxide-semiconductor drain electrode and
The source electrode of the 27th metal-oxide-semiconductor；
The grid of described 25th metal-oxide-semiconductor connects Rst end, and the drain electrode of the 25th metal-oxide-semiconductor connects Q end, the 25th metal-oxide-semiconductor
Source ground；
The grid of described 26th metal-oxide-semiconductor connectsEnd, the drain electrode of the 26th metal-oxide-semiconductor connects Q end；
The grid of described 27th metal-oxide-semiconductor connects Q end, and the drain electrode of the 27th metal-oxide-semiconductor connectsEnd；
The grid of described 28th metal-oxide-semiconductor connects Vss end, and the drain electrode of the 28th metal-oxide-semiconductor connectsEnd, the 28th MOS
The source ground of pipe；
The grid of described 29th metal-oxide-semiconductor connects the first output node, the source ground of the 29th metal-oxide-semiconductor；
The grid of described 30th metal-oxide-semiconductor connects the second output node, the source ground of the 30th metal-oxide-semiconductor.
In described phase discriminator based on sense amplifier D-flip flop, described reseting module includes the first NAND gate and
One and door, an input of described first NAND gate connects the Q end of the first sense amplifier D-flip flop, the first NAND gate
Another input connects the Q end of the second sense amplifier D-flip flop, the outfan of described first NAND gate connect first with
One input of door；First receives reset signal with another input of door, and described first is connected the with the outfan of door
One sense amplifier D-flip flop and the Rst end of the second sense amplifier D-flip flop.
In described phase discriminator based on sense amplifier D-flip flop, described latch module include the second NAND gate,
3rd NAND gate, the 4th NAND gate and the 5th NAND gate, an input of described second NAND gate connects the first sensitive amplification
The Q end of type trigger and phase error output module, another input of the second NAND gate connects the defeated of the 4th NAND gate
Going out end, the outfan of described second NAND gate connects an input and an input of the 3rd NAND gate of the 4th NAND gate
End；Another input of described 3rd NAND gate connects the outfan of the 5th NAND gate, and the outfan of the 3rd NAND gate connects
One input of the 5th NAND gate and phase error output module；Another input of described 4th NAND gate connects second
The Q end of sense amplifier D-flip flop, the outfan of the 4th NAND gate is also connected with another input of the 5th NAND gate；Described
The outfan of the 5th NAND gate is also connected with phase error output module.
In described phase discriminator based on sense amplifier D-flip flop, described phase error output module includes initial single
Unit and termination unit, described start element is for triggering according to phase error direction signal, the first trigger output signal and second
Output signal output phase error initial signal；Described termination unit for according to phase error direction signal, first trigger defeated
Go out signal and the second trigger output signal output phase error termination signal.
In described phase discriminator based on sense amplifier D-flip flop, described start element include the 6th NAND gate,
Seven NAND gate and the 8th NAND gate, an input of described 6th NAND gate connects the Q of the first sense amplifier D-flip flop
End, another input of the 6th NAND gate connects the outfan of the 3rd NAND gate, and the outfan of described 6th NAND gate connects
One input of the 8th NAND gate；One input of described 7th NAND gate connects the outfan of the 5th NAND gate, described
Another input of 7th NAND gate connects the Q end of the second sense amplifier D-flip flop, the output of described 7th NAND gate
End connects another input of the 8th NAND gate；The outfan output phase error initial signal of described 8th NAND gate；
Described termination unit includes the 9th NAND gate, the tenth NAND gate and the 11st NAND gate, of described 9th NAND gate
Input connects the outfan of the 5th NAND gate, and another outfan of the 9th NAND gate connects the first sense amplifier type to be triggered
The Q end of device, the outfan of described 9th NAND gate connects an input of the 11st NAND gate；The one of described tenth NAND gate
Individual input connects the outfan of the 3rd NAND gate, and another outfan of the tenth NAND gate connects the second sense amplifier type and touches
Sending out the Q end of device, the outfan of described tenth NAND gate connects another input of the 11st NAND gate；Described 11st with non-
The outfan output phase error termination signal of door.
In described phase discriminator based on sense amplifier D-flip flop, also include phase error more new module, for root
Trigger output signal output phase error more new signal according to igniter module output；Described phase error more new module includes
Two and door, described second is connected the Q end of the first sense amplifier D-flip flop with an input of door, second with another of door
Individual input connects the Q end of the second sense amplifier D-flip flop, described second and the outfan output phase error renewal of door
Signal.
In described phase discriminator based on sense amplifier D-flip flop, described first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd
Metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor, the 17th metal-oxide-semiconductor, the 18th MOS
Pipe, the 19th metal-oxide-semiconductor and the 20th metal-oxide-semiconductor are P-channel metal-oxide-semiconductor.
In described phase discriminator based on sense amplifier D-flip flop, described 9th metal-oxide-semiconductor, the tenth metal-oxide-semiconductor, the 11st
Metal-oxide-semiconductor, the 12nd metal-oxide-semiconductor, the 13rd metal-oxide-semiconductor, the 14th metal-oxide-semiconductor, the 15th metal-oxide-semiconductor, the 16th metal-oxide-semiconductor, the 21st MOS
Pipe, the 22nd metal-oxide-semiconductor, the 23rd metal-oxide-semiconductor, the 24th metal-oxide-semiconductor, the 25th metal-oxide-semiconductor, the 26th metal-oxide-semiconductor, second
17 metal-oxide-semiconductors, the 28th metal-oxide-semiconductor, the 29th metal-oxide-semiconductor and the 30th metal-oxide-semiconductor are N-channel MOS pipe.
Compared to prior art, the phase discriminator based on sense amplifier D-flip flop that the present invention provides includes trigger mould
Block, reseting module, latch module and phase error output module, received reference clock and feedback clock also by igniter module
Export corresponding trigger output signal to reseting module, latch module and phase error output module；Reseting module is according to defeated
The reset signal entered and described trigger output signal output reseting controling signal control trigger module resets；Latch module root
According to described trigger output signal output phase error direction signal to phase error output module；Phase error output module according to
Described trigger output signal and phase error direction signal output phase error initial signal and phase error termination signal, according to
Described phase error initial signal and phase error termination signal obtain phase error signal, it is possible to effectively eliminate and build trigger
Dependence between immediately, improves the timing performance of phase discriminator, uses two signals to represent phase error, it is also possible to effectively to improve
The accuracy of phase discriminator.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of flop phase discriminator in prior art.
Fig. 2 is the sequential chart of trigger phase discriminator output in prior art.
The circuit diagram of the phase discriminator based on sense amplifier D-flip flop that Fig. 3 provides for the present invention.
Fig. 4 a is the phase error figure of the mistake of phase discriminator based on traditional flip-flop output.
Fig. 4 b is the correct phase error figure of phase discriminator based on sense amplifier D-flip flop output.
In the phase discriminator based on sense amplifier D-flip flop that Fig. 5 a provides for the present invention, the first sense amplifier type touches
Send out the circuit diagram of the charging amplifying unit of device.
In the phase discriminator based on sense amplifier D-flip flop that Fig. 5 b provides for the present invention, the first sense amplifier type touches
Send out the circuit diagram of the latch units of device.
The sequential chart of phase discriminator based on the sense amplifier D-flip flop output that Fig. 6 provides for the present invention.
Detailed description of the invention
In view of in prior art phase discriminator to be set up time effects by trigger very big, and phase error length is inaccurate etc.
Shortcoming, it is an object of the invention to provide a kind of phase discriminator based on sense amplifier D-flip flop, it is possible to effectively eliminate touching
Send out device and set up the dependence of time, improve the timing performance of phase discriminator, use two signals to represent phase error, it is possibility to have
Effect improves the accuracy of phase discriminator.
For making the purpose of the present invention, technical scheme and effect clearer, clear and definite, develop simultaneously embodiment pair referring to the drawings
The present invention further describes.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not used to
Limit the present invention.
Refer to Fig. 3, the phase discriminator based on sense amplifier D-flip flop that the present invention provides include igniter module 10,
Reseting module 20, latch module 30 and phase error output module 40, received reference clock and feedback by igniter module 10
Clock also exports corresponding trigger output signal to reseting module 20, latch module 30 and phase error output module 40；Multiple
Position module 20 exports reseting controling signal control trigger module 10 according to reset signal and the described trigger output signal of input
Reset；Latch module 30 according to described trigger output signal output phase error direction signal to phase error output module
40；Phase error output module 40 is according to the initial letter of described trigger output signal and phase error direction signal output phase error
Number and phase error termination signal, according to described phase error initial signal and phase error termination signal obtain phase error letter
Number, specifically, represent phase by the length between the rising edge of phase error initial signal and phase error termination signal
Position error, is effectively increased the accuracy of phase discriminator.
Further, described igniter module 10 includes that the first sense amplifier D-flip flop SAFF1 and second sensitive is put
Big type trigger SAFF2, described first sense amplifier D-flip flop SAFF1 are used for receiving reference clock and exporting first touching
Send out output signal；Described second sense amplifier D-flip flop SAFF2 is used for receiving feedback clock and exporting the second triggering output
Signal.
When being embodied as, the first sense amplifier D-flip flop SAFF1's and the second sense amplifier D-flip flop SAFF2
Input D end is all connected to Vdd terminal, and the clock end CK of the first sense amplifier D-flip flop SAFF1 terminates reference clock in_
The clock end CK of Refclk, the second sense amplifier D-flip flop SAFF2 terminates feedback clock in_Divclk, and first sensitive puts
The outfan Q end of big type trigger SAFF1 exports the first trigger output signal UP, the second sense amplifier D-flip flop
The outfan Q end of SAFF2 exports the second trigger output signal DN, because phase discriminator is the highest to the performance requirement of trigger, it is desirable to
The time of setting up of trigger and retention time are the least.It is defeated to phase discriminator that Fig. 4 (a) and Fig. 4 (b) represents that the time set up by trigger
Go out the impact of phase error.When phase discriminator has just detected a phase error signal, and the rising edge of another clock is the most and then
During arrival, trigger only has the least time to complete reset and re-read data, when this time is less than trigger
When setting up the time, phase discriminator will the phase error of output error, as shown in Fig. 4 (a) dotted line frame, touch when this time meets
Sending out when setting up the time of device, phase discriminator could export correct phase error, as shown in Figure 4 (b).The most high performance trigger
Normal work to phase discriminator is extremely important, and conventional D flip flop circuit to set up the time the biggest, in order to improve phase discriminator
Timing performance and the reduction phase discriminator sensitivity to the time of setting up, the mirror based on sense amplifier D-flip flop that the present invention provides
Have employed high performance sense amplifier D-flip flop in phase device, have negative setting up the time, the retention time is little, and transmission delay is little
Etc. advantage, it is ensured that the accuracy of the phase error of phase discriminator output.
Specifically, in the phase discriminator based on sense amplifier D-flip flop that the present invention provides, described first sensitive amplification
The circuit structure of type trigger SAFF1 and the second sense amplifier D-flip flop SAFF2 is identical, and it is sensitive that this sentences first
Explain as a example by amplifier D-flip flop SAFF1, see also Fig. 5 (a) and Fig. 5 (b), described first sensitive amplification
Type trigger SAFF1 include CK end, D end,End, Q end,End, Rst end andEnd, also includes charge amplifying unit and lock
Memory cell, wherein charging amplifying unit is the first order circuit of the first sense amplifier D-flip flop SAFF1, and latch units is the
The second level circuit of one sense amplifier D-flip flop SAFF1.Described charging amplifying unit is used for precharging, and on clock
Rising along Gather and input signal when arriving, and the signal collected is delivered to second level circuit output, latch units uses nothing afterwards
Ratio logical design, transmission delay when minimizing trigger output high level to low level changes, also reduce trigger simultaneously
Power consumption.
Wherein, described charging amplifying unit includes the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, the 3rd metal-oxide-semiconductor M3, the 4th MOS
Pipe M4, the 5th metal-oxide-semiconductor M5, the 6th metal-oxide-semiconductor M6, the 7th metal-oxide-semiconductor M7, the 8th metal-oxide-semiconductor M8, the 9th metal-oxide-semiconductor M9, the tenth metal-oxide-semiconductor
M10, the 11st metal-oxide-semiconductor M11, the 12nd metal-oxide-semiconductor M12, the 13rd metal-oxide-semiconductor M13, the 14th metal-oxide-semiconductor M14, the 15th metal-oxide-semiconductor
M15, the 16th metal-oxide-semiconductor M16, the first output nodeWith the second output node.Wherein, described first metal-oxide-semiconductor M1, the 2nd MOS
Pipe M2, the 3rd metal-oxide-semiconductor M3, the 4th metal-oxide-semiconductor M4, the 5th metal-oxide-semiconductor M5, the 6th metal-oxide-semiconductor M6, the 7th metal-oxide-semiconductor M7, the 8th metal-oxide-semiconductor M8
For P-channel metal-oxide-semiconductor, described 9th metal-oxide-semiconductor M9, the tenth metal-oxide-semiconductor M10, the 11st metal-oxide-semiconductor M11, the 12nd metal-oxide-semiconductor M12, the tenth
Three metal-oxide-semiconductor M13, the 14th metal-oxide-semiconductor M14, the 15th metal-oxide-semiconductor M15, the 16th metal-oxide-semiconductor M16 are N-channel MOS pipe.
The grid of described first metal-oxide-semiconductor M1 connectsEnd, the drain electrode of the first metal-oxide-semiconductor M1 connects the first output node, the
The source electrode of one metal-oxide-semiconductor M1 connects Vdd terminal.
The grid of described second metal-oxide-semiconductor M2 connects Vss end, and the drain electrode of the second metal-oxide-semiconductor M2 connects the first output node, the
The source electrode of two metal-oxide-semiconductor M2 connects Vdd terminal.
The grid of described 3rd metal-oxide-semiconductor M3 connects Rst end, and the drain electrode of the 3rd metal-oxide-semiconductor M3 connects the second output node, the
The source electrode of three metal-oxide-semiconductor M3 connects Vdd terminal.
The grid of described 4th metal-oxide-semiconductor M4 connects Vdd terminal, and the drain electrode of the 4th metal-oxide-semiconductor M4 connects the second output node, the
The source electrode of four metal-oxide-semiconductor M4 connects Vdd terminal.
The grid of described 5th metal-oxide-semiconductor M5 connects CK end, and the drain electrode of the 5th metal-oxide-semiconductor M5 connects the first output node, the 5th
The source electrode of metal-oxide-semiconductor M5 connects the first output node。
The grid of described 6th metal-oxide-semiconductor M6 connects the second output node, the drain electrode of the 6th metal-oxide-semiconductor M6 connects the first output
Node, the source electrode of the 6th metal-oxide-semiconductor M6 connects the first output node。
The grid of described 7th metal-oxide-semiconductor M7 connects the first output node, the drain electrode of the 7th metal-oxide-semiconductor M7 connects the second output
Node, the source electrode of the 7th metal-oxide-semiconductor M7 connects the second output node。
The grid of described 8th metal-oxide-semiconductor M8 connects CK end, and the drain electrode of the 8th metal-oxide-semiconductor M8 connects the second output node, the 8th
The source electrode of metal-oxide-semiconductor M8 connects the second output node。
The grid of described 9th metal-oxide-semiconductor M9 connects Vss end, and the drain electrode of the 9th metal-oxide-semiconductor M9 connects the first output node, the
The source ground of nine metal-oxide-semiconductor M9.
The grid of described tenth metal-oxide-semiconductor M10 connects the second output node, it is defeated that the drain electrode of the tenth metal-oxide-semiconductor M10 connects first
Egress, the source electrode of the tenth metal-oxide-semiconductor M10 connects drain electrode and the source electrode of the 14th metal-oxide-semiconductor M14 of the 13rd metal-oxide-semiconductor M13.
The grid of described 11st metal-oxide-semiconductor M11 connects the first output node, the drain electrode of the 11st metal-oxide-semiconductor M11 connects the
Two output nodes, the source electrode of the 11st metal-oxide-semiconductor M11 connects drain electrode and the leakage of the 14th metal-oxide-semiconductor M14 of the 15th metal-oxide-semiconductor M15
Pole.
The grid of described 12nd metal-oxide-semiconductor M12 connects Rst end, and the drain electrode of the 12nd metal-oxide-semiconductor M12 connects the second output joint
Point, the source ground of the 12nd metal-oxide-semiconductor M12.
The grid of described 13rd metal-oxide-semiconductor M13 connects D end, and the source electrode of the 13rd metal-oxide-semiconductor M13 connects the 16th metal-oxide-semiconductor
The drain electrode of M16.
The grid of described 14th metal-oxide-semiconductor M14 connects Vdd terminal.
The grid of described 15th metal-oxide-semiconductor M15 connectsEnd, the source electrode of the 15th metal-oxide-semiconductor M15 connects the 16th metal-oxide-semiconductor
The drain electrode of M16.
The grid of described 16th metal-oxide-semiconductor M16 connects CK end, the source ground of the 16th metal-oxide-semiconductor M16.
When clock signal CK is low level (when the signal of CK end is low level), the first output nodeDefeated with second
EgressIt is charged to high level, output signalWithKeep constant (i.e.WithThe level signal of end keeps constant)；When
The when that the rising edge of clock signal CK arriving, the first output nodeWith the second output nodeAccording to input signalWith
Value start electric discharge, when input signal D be 1,When being 0 (signal of D end be high level,The signal of end is low level),
First output node signal=0, second output node signal=1, so that output signal=1、=0.Because at clock
First output node when signal CK is low levelWith the second output nodeIt is charged to high level in advance, if clock signal
CK rising edge arrives the first output nodeWith the second output nodeJust can start electric discharge, thus realize negative setting up the time,
Decrease phase discriminator and trigger is set up the dependence of time.
Further, described latch units includes the 17th metal-oxide-semiconductor M17, the 18th metal-oxide-semiconductor M18, the 19th metal-oxide-semiconductor
M19, the 20th metal-oxide-semiconductor M20, the 21st metal-oxide-semiconductor M21, the 22nd metal-oxide-semiconductor M22, the 23rd metal-oxide-semiconductor M23, the 20th
Four metal-oxide-semiconductor M24, the 25th metal-oxide-semiconductor M25, the 26th metal-oxide-semiconductor M26, the 27th metal-oxide-semiconductor M27, the 28th metal-oxide-semiconductor
M28, the 29th metal-oxide-semiconductor M29 and the 30th metal-oxide-semiconductor M30.Wherein, described 17th metal-oxide-semiconductor M17, the 18th metal-oxide-semiconductor M18,
19th metal-oxide-semiconductor M19 and the 20th metal-oxide-semiconductor M20 is P-channel metal-oxide-semiconductor, described 21st metal-oxide-semiconductor M21, the 22nd metal-oxide-semiconductor
M22, the 23rd metal-oxide-semiconductor M23, the 24th metal-oxide-semiconductor M24, the 25th metal-oxide-semiconductor M25, the 26th metal-oxide-semiconductor M26, second
17 metal-oxide-semiconductor M27, the 28th metal-oxide-semiconductor M28, the 29th metal-oxide-semiconductor M29 and the 30th metal-oxide-semiconductor M30 are N-channel MOS pipe.
The grid of described 17th metal-oxide-semiconductor M17 connects the first output node, the drain electrode of the 17th metal-oxide-semiconductor M17 connects Q
End, the source electrode of the 17th metal-oxide-semiconductor M17 connects Vdd terminal.
The grid of described 18th metal-oxide-semiconductor M18 connectsEnd, the drain electrode connection Q end of the 18th metal-oxide-semiconductor M18, the 18th
The source electrode of metal-oxide-semiconductor M18 connects Vdd terminal.
The grid of described 19th metal-oxide-semiconductor M19 connects Q end, and the drain electrode of the 19th metal-oxide-semiconductor M19 connectsEnd, the 19th
The source electrode of metal-oxide-semiconductor M19 connects Vdd terminal.
The grid of described 20th metal-oxide-semiconductor M20 connects the second output node, the drain electrode of the 20th metal-oxide-semiconductor M20 connects
End, the source electrode of the 20th metal-oxide-semiconductor M20 connects Vdd terminal.
The grid of described 21st metal-oxide-semiconductor M21 connects CK end, the drain electrode connection Q end of the 21st metal-oxide-semiconductor M21, and second
The source electrode of 11 metal-oxide-semiconductor M21 connects the drain electrode of the 22nd metal-oxide-semiconductor M22.
The grid of described 22nd metal-oxide-semiconductor M22 connectsEnd, the source electrode of the 22nd metal-oxide-semiconductor M22 connects the 29th
The drain electrode of metal-oxide-semiconductor M29 and the source electrode of the 26th metal-oxide-semiconductor M26.
The grid of described 23rd metal-oxide-semiconductor M23 connects CK end, and the drain electrode of the 23rd metal-oxide-semiconductor M23 connectsEnd, the
The source electrode of 23 metal-oxide-semiconductor M23 connects the drain electrode of the 24th metal-oxide-semiconductor M24.
The grid of described 24th metal-oxide-semiconductor M24 connects D end, and the source electrode of the 24th metal-oxide-semiconductor M24 connects the 30th MOS
The drain electrode of pipe M30 and the source electrode of the 27th metal-oxide-semiconductor M27.
The grid of described 25th metal-oxide-semiconductor M25 connects Rst end, and the drain electrode of the 25th metal-oxide-semiconductor M25 connects Q end, the
The source ground of 25 metal-oxide-semiconductor M25.
The grid of described 26th metal-oxide-semiconductor M26 connectsEnd, the drain electrode of the 26th metal-oxide-semiconductor M26 connects Q end.
The grid of described 27th metal-oxide-semiconductor M27 connects Q end, and the drain electrode of the 27th metal-oxide-semiconductor M27 connectsEnd.
The grid of described 28th metal-oxide-semiconductor M28 connects Vss end, and the drain electrode of the 28th metal-oxide-semiconductor M28 connectsEnd, the
The source ground of 28 metal-oxide-semiconductor M28.
The grid of described 29th metal-oxide-semiconductor M29 connects the first output node, the source electrode of the 29th metal-oxide-semiconductor M29 connects
Ground.
The grid of described 30th metal-oxide-semiconductor M30 connects the second output node, the source ground of the 30th metal-oxide-semiconductor M30.
The i.e. latch units of second level circuit of the first sense amplifier D-flip flop SAFF1 uses incomparable logical design, the
21 metal-oxide-semiconductor M21, the 22nd metal-oxide-semiconductor M22, the 23rd metal-oxide-semiconductor M23 and the 24th metal-oxide-semiconductor M24 are used for reducing tactile
Send out device output high level to low level change time transmission delay, also reduce the power consumption of trigger simultaneously.
Referring to Fig. 3, reset mould described in the phase discriminator based on sense amplifier D-flip flop that the present invention provides
Block 20 includes that the first NAND gate NAND1 and first connects first with door AND1, an input of described first NAND gate NAND1
The Q end of sense amplifier D-flip flop SAFF1, another input of the first NAND gate NAND1 connects the second sense amplifier
The Q end of D-flip flop SAFF2, the outfan of described first NAND gate NAND1 connects an input of first and door AND1；The
One receives reset signal with another input of door AND1, and described first is connected the first sensitive amplification with the outfan of door AND1
Type trigger SAFF1 and the Rst end of the second sense amplifier D-flip flop SAFF2, specifically, the first sense amplifier type touches
The outfan Q end sending out device SAFF1 exports the first trigger output signal UP, the output of the second sense amplifier D-flip flop SAFF2
End Q end exports signal that the second trigger output signal DN, UP signal and DN signal obtain after the first NAND gate NAND1 with multiple
Position signal in_Reset signal phase with, obtain reset control model reset, reset signal is input to the first sense amplifier type
Trigger SAFF1 and the second sense amplifier D-flip flop SAFF2 reset terminal Rst, control trigger resets.
UP signal and DN signal are through latch module 30 afterwards, obtain phase error direction signal out_Dir andSignal, wherein latch module 30 is cross-linked NAND gate latch, specifically, described latch module 30
Including the second NAND gate NAND2, the 3rd NAND gate NAND3, the 4th NAND gate NAND4 and the 5th NAND gate NAND5, described second
One input of NAND gate NAND2 connects Q end and the phase error output module of the first sense amplifier D-flip flop SAFF1
40, another input of the second NAND gate NAND2 connects the outfan of the 4th NAND gate NAND4, described second NAND gate
The outfan of NAND2 connects an input and an input of the 3rd NAND gate NAND3 of the 4th NAND gate NAND4；Institute
Another input stating the 3rd NAND gate NAND3 connects the outfan of the 5th NAND gate NAND5, the 3rd NAND gate NAND3
Outfan connects an input and the phase error output module 40 of the 5th NAND gate NAND5；Described 4th NAND gate NAND4
Another input connect the Q end of the second sense amplifier D-flip flop SAFF2, the outfan of the 4th NAND gate NAND4 is also
Connect another input of the 5th NAND gate NAND5；It is defeated that the outfan of described 5th NAND gate NAND5 is also connected with phase error
Go out module 40.Phase error direction signal out_Dir represents the direction of phase error, when with reference to the advanced feedback clock of clock phase
During phase place, out_Dir exports high level, and when lagging behind feedback clock phase place with reference to clock phase, out_Dir exports low electricity
Flat.
Meanwhile, described phase discriminator based on sense amplifier D-flip flop also includes phase error more new module 50, is used for
According to the trigger output signal output phase error more new signal of igniter module 10 output, each phase error detection is complete
Time, phase error more new module 50 exports an of short duration pulse signal out_Update, i.e. phase error more new signal, this
Pulse signal will be used for producing the synchronised clock of wave filter.Specifically, described phase error more new module 50 includes second and door
AND2, described second is connected the Q end of the first sense amplifier D-flip flop SAFF1 with an input of door AND2, second with
Another input of door AND2 connects the Q end of the second sense amplifier D-flip flop SAFF2, the described second defeated with door AND2
Go out to hold output phase error more new signal, i.e. UP signal and DN signal to obtain phase error after second with door AND2 and update letter
Number Out_Update.
Further, described phase error output module 40 includes start element 401 and terminates unit 402, described initial
Unit 401 is for according to phase error direction signal out_Dir, the first trigger output signal UP and the second trigger output signal DN
Output phase error initial signal out_Start；Described termination unit 402 for according to phase error direction signal out_Dir,
First trigger output signal UP and the second trigger output signal DN output phase error termination signal out_Stop, afterwards according to phase
Length between position error initial signal out_Start and the rising edge of phase error termination signal out_Stop represents that phase place is by mistake
Difference signal, contrast tradition phase discriminator only represents phase error by the pulse length of a signal, can be effectively improved phase error
Accuracy.
Described start element includes the 6th NAND gate NAND6, the 7th NAND gate NAND7 and the 8th NAND gate NAND8, described
One input of the 6th NAND gate NAND6 connects the Q end of the first sense amplifier D-flip flop SAFF1, the 6th NAND gate
Another input of NAND6 connects the outfan of the 3rd NAND gate NAND3, and the outfan of described 6th NAND gate NAND6 is even
Connect an input of the 8th NAND gate NAND8；One input of described 7th NAND gate NAND7 connects the 5th NAND gate
The outfan of NAND5, another input of described 7th NAND gate NAND7 connects the second sense amplifier D-flip flop
The Q end of SAFF2, the outfan of described 7th NAND gate NAND7 connects another input of the 8th NAND gate NAND8；Described
The outfan output phase error initial signal of the 8th NAND gate NAND8.One input of wherein said 6th NAND gate NAND6
End input UP signal, another input input out_Dir signal of the 6th NAND gate NAND6, obtain signal S1, institute with non-post
State an input input of the 7th NAND gate NAND7Signal, another input of the 7th NAND gate NAND7 is defeated
Enter DN signal, obtain signal S2, signal S1 and S2 with non-post and phase error initial signal out_Start have to be arrived.
Described termination unit includes the 9th NAND gate NAND9, the tenth NAND gate NAND10 and the 11st NAND gate NAND11,
One input of described 9th NAND gate NAND9 connects the outfan of the 5th NAND gate NAND5, the 9th NAND gate NAND9
Another outfan connects the Q end of the first sense amplifier D-flip flop SAFF1, the outfan of described 9th NAND gate NAND9
Connect an input of the 11st NAND gate NAND11；One input of described tenth NAND gate NAND10 connect the 3rd with
The outfan of not gate NAND3, another outfan of the tenth NAND gate NAND10 connects the second sense amplifier D-flip flop
The Q end of SAFF2, the outfan of described tenth NAND gate NAND10 connects another input of the 11st NAND gate NAND11；
The outfan output phase error termination signal of described 11st NAND gate NAND11.Wherein said 9th NAND gate NAND9
One input inputSignal, another input input UP signal of the 9th NAND gate NAND9, obtain with non-post
Signal S3, input input out_Dir signal of described tenth NAND gate NAND10, another of the tenth NAND gate NAND10
Individual input input DN signal, obtains signal S4, signal S3 and S4 with non-post and have to arrive phase error termination signal out_
Stop。
Below in conjunction with Fig. 3, Fig. 5 (a), Fig. 5 (b) and Fig. 6 phase demodulation based on sense amplifier D-flip flop to the present invention
The operation principle of device is described in detail:
Trigger reset at the beginning, UP and DN signal is all low level, when the rising edge of reference clock in_Refclk is prior to feedback
When the rising edge of clock in_Divclk arrives, UP exports high level, until in_Divclk rising edge arrives, DN output one is short
Temporary high level pulse signal, UP and DN signal with have to arrive logical zero, trigger reset, UP and DN also recovers logic O.Otherwise
When in_Refclk rising edge is slower than the arrival of in_Divclk rising edge, DN first exports high level, until in_Refclk rising edge
Arrive, trigger reset.UP and DN signal can obtain out_Dir signal, concrete logic through a NAND gate RS latch
Output rule is as follows: as " UP=1, DN=0 " " out_Dir=1 ", as " UP=0, DN=1 " " out_Dir=0 ", when " UP=0,
DN=0 " or time " UP=1, DN=1 ", " out_Dir " keeps constant.The logical expression of out_Start and out_Stop such as formula (1)
With formula (2) Suo Shi.
(1)
(2)
Because there is internal delay time, UP signal and DN signal in trigger always produces an of short duration pulse signal, therefore UP letter
Number and phase error length represented by DN signal always long than actual phase error length, therefore with out_Start and
Length between the rising edge of two signals of out_Stop represents phase error signal, can balance out trigger internal delay time
Impact, the measurement of phase error is the most accurate.
The highest to the performance requirement of trigger additionally, due to phase discriminator, it is desirable to the time of setting up of trigger and retention time are to the greatest extent
May be little, present invention employs the sense amplifier D-flip flop with the negative time of setting up, the retention time is little, transmission delay
Little, eliminate phase discriminator and trigger is set up the dependence of time, improve the timing performance of phase discriminator, owing to the most putting sensitive
Big type trigger is described in detail, and is not described further.
In sum, the phase discriminator based on sense amplifier D-flip flop that the present invention provides includes igniter module, answers
Position module, latch module and phase error output module, received reference clock and feedback clock by igniter module and export
Corresponding trigger output signal is to reseting module, latch module and phase error output module；Reseting module is according to input
Reset signal and described trigger output signal output reseting controling signal control trigger module resets；Latch module is according to institute
State trigger output signal output phase error direction signal to phase error output module；Phase error output module is according to described
Trigger output signal and phase error direction signal output phase error initial signal and phase error termination signal, according to described
Phase error initial signal and phase error termination signal obtain phase error signal, it is possible to when effectively trigger is set up by elimination
Between dependence, improve the timing performance of phase discriminator, use two signals to represent phase error, it is also possible to effectively to improve phase demodulation
The accuracy of device.
It is understood that for those of ordinary skills, can be according to technical scheme and send out
Bright design in addition equivalent or change, and all these change or replace the guarantor that all should belong to appended claims of the invention
Protect scope.
Claims (10)
1. a phase discriminator based on sense amplifier D-flip flop, it is characterised in that include igniter module, reseting module,
Latch module and phase error output module, received reference clock and feedback clock by igniter module and export corresponding touching
Send out and output signal to reseting module, latch module and phase error output module；Reseting module is according to the reset signal of input
Reseting controling signal control trigger module resets is exported with described trigger output signal；Latch module is defeated according to described triggering
Go out signal output phase error direction signal to phase error output module；Phase error output module triggers output according to described
Signal and phase error direction signal output phase error initial signal and phase error termination signal, according to described phase error
Initial signal and phase error termination signal obtain phase error signal.
Phase discriminator based on sense amplifier D-flip flop the most according to claim 1, it is characterised in that described trigger
Module includes the first sense amplifier D-flip flop and the second sense amplifier D-flip flop, and described first sense amplifier type touches
Send out device to be used for receiving reference clock and exporting the first trigger output signal；Described second sense amplifier D-flip flop is used for receiving
Feedback clock also exports the second trigger output signal.
Phase discriminator based on sense amplifier D-flip flop the most according to claim 2, it is characterised in that described first spirit
The circuit structure of quick amplifier D-flip flop and the second sense amplifier D-flip flop is identical, described first sense amplifier
D-flip flop include CK end, D end,End, Q end,End, Rst end andEnd, also includes charge amplifying unit and latch units；
Wherein, described charging amplifying unit includes the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the 5th MOS
Pipe, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor, the 9th metal-oxide-semiconductor, the tenth metal-oxide-semiconductor, the 11st metal-oxide-semiconductor, the 12nd metal-oxide-semiconductor,
13rd metal-oxide-semiconductor, the 14th metal-oxide-semiconductor, the 15th metal-oxide-semiconductor, the 16th metal-oxide-semiconductor, the first output node and the second output node；
The grid of described first metal-oxide-semiconductor connectsEnd, the drain electrode of the first metal-oxide-semiconductor connects the first output node, the first metal-oxide-semiconductor
Source electrode connects Vdd terminal；
The grid of described second metal-oxide-semiconductor connects Vss end, and the drain electrode of the second metal-oxide-semiconductor connects the first output node, the second metal-oxide-semiconductor
Source electrode connects Vdd terminal；
The grid of described 3rd metal-oxide-semiconductor connects Rst end, and the drain electrode of the 3rd metal-oxide-semiconductor connects the second output node, the 3rd metal-oxide-semiconductor
Source electrode connects Vdd terminal；
The grid of described 4th metal-oxide-semiconductor connects Vdd terminal, and the drain electrode of the 4th metal-oxide-semiconductor connects the second output node, the 4th metal-oxide-semiconductor
Source electrode connects Vdd terminal；
The grid of described 5th metal-oxide-semiconductor connects CK end, and the drain electrode of the 5th metal-oxide-semiconductor connects the first output node, the source of the 5th metal-oxide-semiconductor
Pole connects the first output node；
The grid of described 6th metal-oxide-semiconductor connects the second output node, and the drain electrode of the 6th metal-oxide-semiconductor connects the first output node, and the 6th
The source electrode of metal-oxide-semiconductor connects the first output node；
The grid of described 7th metal-oxide-semiconductor connects the first output node, and the drain electrode of the 7th metal-oxide-semiconductor connects the second output node, and the 7th
The source electrode of metal-oxide-semiconductor connects the second output node；
The grid of described 8th metal-oxide-semiconductor connects CK end, and the drain electrode of the 8th metal-oxide-semiconductor connects the second output node, the source of the 8th metal-oxide-semiconductor
Pole connects the second output node；
The grid of described 9th metal-oxide-semiconductor connects Vss end, and the drain electrode of the 9th metal-oxide-semiconductor connects the first output node, the 9th metal-oxide-semiconductor
Source ground；
The grid of described tenth metal-oxide-semiconductor connects the second output node, and the drain electrode of the tenth metal-oxide-semiconductor connects the first output node, and the tenth
The source electrode of metal-oxide-semiconductor connects drain electrode and the source electrode of the 14th metal-oxide-semiconductor of the 13rd metal-oxide-semiconductor；
The grid of described 11st metal-oxide-semiconductor connects the first output node, and the drain electrode of the 11st metal-oxide-semiconductor connects the second output node,
The source electrode of the 11st metal-oxide-semiconductor connects drain electrode and the drain electrode of the 14th metal-oxide-semiconductor of the 15th metal-oxide-semiconductor；
The grid of described 12nd metal-oxide-semiconductor connects Rst end, and the drain electrode of the 12nd metal-oxide-semiconductor connects the second output node, and the 12nd
The source ground of metal-oxide-semiconductor；
The grid of described 13rd metal-oxide-semiconductor connects D end, and the source electrode of the 13rd metal-oxide-semiconductor connects the drain electrode of the 16th metal-oxide-semiconductor；
The grid of described 14th metal-oxide-semiconductor connects Vdd terminal；
The grid of described 15th metal-oxide-semiconductor connectsEnd, the source electrode of the 15th metal-oxide-semiconductor connects the drain electrode of the 16th metal-oxide-semiconductor；
The grid of described 16th metal-oxide-semiconductor connects CK end, the source ground of the 16th metal-oxide-semiconductor；
Wherein, described latch units include the 17th metal-oxide-semiconductor, the 18th metal-oxide-semiconductor, the 19th metal-oxide-semiconductor, the 20th metal-oxide-semiconductor, second
11 metal-oxide-semiconductors, the 22nd metal-oxide-semiconductor, the 23rd metal-oxide-semiconductor, the 24th metal-oxide-semiconductor, the 25th metal-oxide-semiconductor, the 26th MOS
Pipe, the 27th metal-oxide-semiconductor, the 28th metal-oxide-semiconductor, the 29th metal-oxide-semiconductor and the 30th metal-oxide-semiconductor；
The grid of described 17th metal-oxide-semiconductor connects the first output node, and the drain electrode of the 17th metal-oxide-semiconductor connects Q end, the 17th MOS
The source electrode of pipe connects Vdd terminal；
The grid of described 18th metal-oxide-semiconductor connectsEnd, the drain electrode of the 18th metal-oxide-semiconductor connects Q end, and the source electrode of the 18th metal-oxide-semiconductor is even
Connect Vdd terminal；
The grid of described 19th metal-oxide-semiconductor connects Q end, and the drain electrode of the 19th metal-oxide-semiconductor connectsEnd, the source electrode of the 19th metal-oxide-semiconductor is even
Connect Vdd terminal；
The grid of described 20th metal-oxide-semiconductor connects the second output node, and the drain electrode of the 20th metal-oxide-semiconductor connectsEnd, the 20th MOS
The source electrode of pipe connects Vdd terminal；
The grid of described 21st metal-oxide-semiconductor connects CK end, and the drain electrode of the 21st metal-oxide-semiconductor connects Q end, the 21st metal-oxide-semiconductor
Source electrode connect the 22nd metal-oxide-semiconductor drain electrode；
The grid of described 22nd metal-oxide-semiconductor connectsEnd, the source electrode of the 22nd metal-oxide-semiconductor connects the drain electrode of the 29th metal-oxide-semiconductor
Source electrode with the 26th metal-oxide-semiconductor；
The grid of described 23rd metal-oxide-semiconductor connects CK end, and the drain electrode of the 23rd metal-oxide-semiconductor connectsEnd, the 23rd metal-oxide-semiconductor
Source electrode connect the 24th metal-oxide-semiconductor drain electrode；
The grid of described 24th metal-oxide-semiconductor connects D end, the source electrode of the 24th metal-oxide-semiconductor connect the 30th metal-oxide-semiconductor drain electrode and
The source electrode of the 27th metal-oxide-semiconductor；
The grid of described 25th metal-oxide-semiconductor connects Rst end, and the drain electrode of the 25th metal-oxide-semiconductor connects Q end, the 25th metal-oxide-semiconductor
Source ground；
The grid of described 26th metal-oxide-semiconductor connectsEnd, the drain electrode of the 26th metal-oxide-semiconductor connects Q end；
The grid of described 27th metal-oxide-semiconductor connects Q end, and the drain electrode of the 27th metal-oxide-semiconductor connectsEnd；
The grid of described 28th metal-oxide-semiconductor connects Vss end, and the drain electrode of the 28th metal-oxide-semiconductor connectsEnd, the 28th metal-oxide-semiconductor
Source ground；
The grid of described 29th metal-oxide-semiconductor connects the first output node, the source ground of the 29th metal-oxide-semiconductor；
The grid of described 30th metal-oxide-semiconductor connects the second output node, the source ground of the 30th metal-oxide-semiconductor.
Phase discriminator based on sense amplifier D-flip flop the most according to claim 3, it is characterised in that described reset mould
Block includes the first NAND gate and first and door, and an input of described first NAND gate connects the first sense amplifier type to be triggered
The Q end of device, another input of the first NAND gate connects the Q end of the second sense amplifier D-flip flop, and described first with non-
The outfan of door connects an input of first and door；First receives reset signal with another input of door, and described the
One is connected the first sense amplifier D-flip flop and the Rst end of the second sense amplifier D-flip flop with the outfan of door.
Phase discriminator based on sense amplifier D-flip flop the most according to claim 3, it is characterised in that described latch
Module includes the second NAND gate, the 3rd NAND gate, the 4th NAND gate and the 5th NAND gate, an input of described second NAND gate
End connects Q end and phase error output module, another input of the second NAND gate of the first sense amplifier D-flip flop
Connecting the outfan of the 4th NAND gate, the outfan of described second NAND gate connects an input and the 3rd of the 4th NAND gate
One input of NAND gate；Another input of described 3rd NAND gate connects the outfan of the 5th NAND gate, the 3rd with
The outfan of not gate connects an input and the phase error output module of the 5th NAND gate；Another of described 4th NAND gate
Individual input connects the Q end of the second sense amplifier D-flip flop, and the outfan of the 4th NAND gate is also connected with the 5th NAND gate
Another input；The outfan of described 5th NAND gate is also connected with phase error output module.
Phase discriminator based on sense amplifier D-flip flop the most according to claim 5, it is characterised in that described phase place is by mistake
Difference output module include start element and terminate unit, described start element for according to phase error direction signal, first touch
Send out output signal and the second trigger output signal output phase error initial signal；Described termination unit is for according to phase error
Direction signal, the first trigger output signal and the second trigger output signal output phase error termination signal.
Phase discriminator based on sense amplifier D-flip flop the most according to claim 6, it is characterised in that described initial list
Unit includes the 6th NAND gate, the 7th NAND gate and the 8th NAND gate, and an input of described 6th NAND gate connects the first spirit
The Q end of quick amplifier D-flip flop, the outfan of another input connection the 3rd NAND gate of the 6th NAND gate, the described 6th
The outfan of NAND gate connects an input of the 8th NAND gate；One input of described 7th NAND gate connect the 5th with
The outfan of not gate, another input of described 7th NAND gate connects the Q end of the second sense amplifier D-flip flop, described
The outfan of the 7th NAND gate connects another input of the 8th NAND gate；The outfan output phase place of described 8th NAND gate
Error initial signal；
Described termination unit includes the 9th NAND gate, the tenth NAND gate and the 11st NAND gate, of described 9th NAND gate
Input connects the outfan of the 5th NAND gate, and another outfan of the 9th NAND gate connects the first sense amplifier type to be triggered
The Q end of device, the outfan of described 9th NAND gate connects an input of the 11st NAND gate；The one of described tenth NAND gate
Individual input connects the outfan of the 3rd NAND gate, and another outfan of the tenth NAND gate connects the second sense amplifier type and touches
Sending out the Q end of device, the outfan of described tenth NAND gate connects another input of the 11st NAND gate；Described 11st with non-
The outfan output phase error termination signal of door.
Phase discriminator based on sense amplifier D-flip flop the most according to claim 3, it is characterised in that also include phase place
Error update module, for the trigger output signal output phase error more new signal according to igniter module output；Described phase
Position error update module includes second and door, and described second is connected the first sense amplifier D-flip flop with an input of door
Q end, second is connected the Q end of the second sense amplifier D-flip flop with another input of door, the described second defeated with door
Go out to hold output phase error more new signal.
Phase discriminator based on sense amplifier D-flip flop the most according to claim 3, it is characterised in that described first
Metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor,
17th metal-oxide-semiconductor, the 18th metal-oxide-semiconductor, the 19th metal-oxide-semiconductor and the 20th metal-oxide-semiconductor are P-channel metal-oxide-semiconductor.
Phase discriminator based on sense amplifier D-flip flop the most according to claim 3, it is characterised in that the described 9th
Metal-oxide-semiconductor, the tenth metal-oxide-semiconductor, the 11st metal-oxide-semiconductor, the 12nd metal-oxide-semiconductor, the 13rd metal-oxide-semiconductor, the 14th metal-oxide-semiconductor, the 15th metal-oxide-semiconductor,
16th metal-oxide-semiconductor, the 21st metal-oxide-semiconductor, the 22nd metal-oxide-semiconductor, the 23rd metal-oxide-semiconductor, the 24th metal-oxide-semiconductor, the 25th
Metal-oxide-semiconductor, the 26th metal-oxide-semiconductor, the 27th metal-oxide-semiconductor, the 28th metal-oxide-semiconductor, the 29th metal-oxide-semiconductor and the 30th metal-oxide-semiconductor are N
Channel MOS tube.
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| CN112311387A (en) * | 2019-08-01 | 2021-02-02 | 张伟林 | High-resistance digital phase discriminator combined by different triggers |
| US11398826B1 (en) * | 2021-09-19 | 2022-07-26 | Hcl Technologies Limited | Half rate bang-bang phase detector |
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| CN110336559A (en) * | 2019-07-11 | 2019-10-15 | 福州大学 | A kind of reset signal and sampled clock signal generating device and its control method |
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| CN112311387A (en) * | 2019-08-01 | 2021-02-02 | 张伟林 | High-resistance digital phase discriminator combined by different triggers |
| CN112311387B (en) * | 2019-08-01 | 2024-06-07 | 张伟林 | High-resistance digital phase discriminator with different trigger combinations |
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