CN106208781A - The manufacture method of a kind of power device and power device - Google Patents
The manufacture method of a kind of power device and power device Download PDFInfo
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- CN106208781A CN106208781A CN201510228095.7A CN201510228095A CN106208781A CN 106208781 A CN106208781 A CN 106208781A CN 201510228095 A CN201510228095 A CN 201510228095A CN 106208781 A CN106208781 A CN 106208781A
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- oxide layer
- power device
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- support chip
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Abstract
The present invention provides manufacture method and the power device of a kind of power device, and described method includes: S1, prepare the structure of described power device at the first surface of substrate；S2, in described structure, prepare the first oxide layer；S3, the support chip with the second oxide layer being attached to described first oxide layer, described first oxide layer is bonded together with described second oxide layer, and the material of described first oxide layer and the material of the second oxide layer are identical；S4, the second surface not preparing described structure to described substrate are ground thinning；S5, second surface after thinning prepare the Facad structure of described power device；S6, successively described support chip, the second oxide layer and the first oxide layer are removed, and prepare metal level in described structure.The present invention by the substrate making power device being placed on support chip in technical process, operation simultaneously, thus add the intensity of substrate.
Description
Technical field
The present invention relates to semiconductor chip fabrication process technical field, especially a kind of quasiconductor merit
The manufacture method of rate device and power device.
Background technology
For power device, having two particularly important parameters, one is conducting resistance, separately
One is breakdown voltage, wishes that conducting resistance is the least for application, and breakdown voltage
The highest more good.Power device, in order to bear high voltage, needs to use the thickest low-doped epitaxial layer.
By increasing epitaxy layer thickness or reducing the doping content of epitaxial layer, breakdown voltage can be improved,
But improve conducting resistance while do so, power when being unfavorable for reducing break-over of device damages
Consumption.As can be seen here, it is difficult to the two parameter is optimized simultaneously.
Current DC/DC conversion efficiency typically 80%～90% scope, have nearly half
Power consumption penalty produce on power field device, these a part of reasons lost by device power consumption
It is that conducting resistance is converted into Joule heat, causes device to heat up.Reduce the most as much as possible and lead
Energising resistance and the heat dispersion improving device are that power field effect transistor supplier improves competition
The key technology means of power.
One of solution used at present is ground thinning exactly, and the function of the device on silicon chip has
The thickness in effect region is generally 5 to 100um.But this thickness has actually only taken up whole crystalline substance
Circle thickness sub-fraction, the substrate of remaining thickness be intended merely to ensure silicon chip manufacture, test,
Enough intensity is had during encapsulation and transport.Device Facad structure on silicon chip has made
Cheng Hou, needs silicon chip is carried out thinning back side so that it is reach required thickness, some species of
Power device, also will the most thinning after, continue make structure overleaf, then make
Metal level, and then from back side extraction electrode.
The manufacture method mainly deficiency of at present conventional power device thin slice has 2 points:
1) the thin slice processing technology used is all first to make Facad structure (to include front metal electricity
Pole) after, then carry out thinning, last making devices structure.This method is making the back side
During structure, Facad structure has been fully completed.In order to prevent Facad structure from being destroyed, the back side
The technological temperature of technique is generally not capable of more than 400 DEG C, otherwise front metal pattern and device architecture
Can be affected, cause device performance and reliability decrease.
2) after wafer thinning, die strength declines, and causes fragment rate in technical process to raise,
Improve the manufacturing cost of device, the minimum thickness simultaneously limiting silicon chip have impact on the property of device
Energy
Summary of the invention
Based on the problems referred to above, the present invention provides manufacture method and the power device of a kind of power device
Part, by being placed on the substrate making power device on support chip, simultaneously in technical process
Operation, thus add the intensity of substrate.
According to an aspect of the present invention, it is provided that the manufacture method of a kind of power device, described side
Method includes:
S1, prepare the structure of described power device at the first surface of substrate；
S2, in described structure, prepare the first oxide layer；
S3, the support chip with the second oxide layer is attached to described first oxide layer, described
One oxide layer is bonded together with described second oxide layer, the material of described first oxide layer and
The material of dioxide layer is identical；
S4, the second surface not preparing described structure to described substrate are ground subtracting
Thin；
S5, second surface after thinning prepare the Facad structure of described power device；
S6, successively described support chip, the second oxide layer and the first oxide layer are removed, and in institute
State and in structure, prepare metal level.
Wherein, described substrate is silicon chip.
Wherein, described first oxide layer is silicon oxide layer, and described silicon oxide layer is by entering silicon chip
Row thermal oxide is made.
Wherein, described support chip is identical with the material of described substrate.
Wherein, described second oxide layer is prepared from by described support chip is carried out thermal oxide.
Wherein, described support chip is removed by the method ground.
According to another aspect of the present invention, it is provided that a kind of power device, it is characterised in that institute
State power device to make to make in aforementioned manners.
The manufacture method of a kind of power device of the present invention and power device, making power
The substrate of device is placed on support chip, first making devices structure, such structure system
Technological temperature during work can not be limited, it is possible to increase device performance, it addition, this
The bright use material identical with substrate, as support chip, can improve the intensity of substrate, reduce
Fragment rate in technique, reduces device manufacturing cost.
Accompanying drawing explanation
By being more clearly understood from the features and advantages of the present invention with reference to accompanying drawing, accompanying drawing is to show
Meaning property and should not be construed as the present invention is carried out any restriction, in the accompanying drawings:
Fig. 1 shows the flow chart of the method for the manufacture of a kind of power device of the present invention.
Fig. 2 to Fig. 7 shows the work of the manufacture method of the power device of one embodiment of the invention
Skill schematic diagram.
Detailed description of the invention
Below in conjunction with accompanying drawing, embodiments of the present invention is described in detail.
Fig. 1 shows the flow chart of the method for the manufacture of a kind of power device of the present invention.Fig. 2
The technique signal of the manufacture method of the power device of one embodiment of the invention is shown to Fig. 7
Figure.
With reference to Fig. 1, in one embodiment of the invention, it is provided that the manufacture of a kind of power device
Method, the method comprising the steps of:
S1, prepare the structure of described power device at the first surface of substrate.
Manufacturing during power device, first according to features such as the type of power device, functions
Selecting specific substrate, the most conventional substrate is silicon chip, and the doping content of its silicon chip can root
Specifically set according to the power device made.It addition, the crystal orientation of silicon chip, doping type can also root
Type decided according to power device.It addition, substrate can also use other materials such as gallium nitride
(GaN) prepare.
As in figure 2 it is shown, in the present embodiment, for preparing the mistake of the structure of power device
Journey does not do concrete restriction, prepares the processing technology of structure 20 over the substrate 10 according to preparation
The type of power device specifically set, and use the processing technology of existing power device to carry out
Prepare targetedly, be not described in detail herein.
S2, in described structure, prepare the first oxide layer.
As it is shown on figure 3, after overleaf prepared by structure 20, in order to prevent preparing other knots
Structure 20 is damaged, in its Surface Creation the first oxide layer 30, to protect the back side during structure
Structure 20, the thickness of the first oxide layer 30 can set according to the concrete shape of structure herein
Fixed.
S3, the support chip with the second oxide layer is attached to described first oxide layer, described
One oxide layer is bonded together with described second oxide layer, the material of described first oxide layer and
The material of dioxide layer is identical；
As shown in Figure 4, after generating the first oxide layer 30 in structure 20 overleaf, in order in preparation
To the thinning process of substrate will not damage substrate during Facad structure, combine in structure overleaf and prop up
Blade 50 is supported.When combining support chip 50, in order to more firm, at support chip 50
Surface prepare the second oxide layer 40, then the first oxide layer 30 and the second oxide layer 40 are tied
Close.It addition, support chip selects the material identical with substrate to make, mix with substrate as used
The silicon chip that dephasign is same, the second oxide layer is prepared from by described support chip is carried out thermal oxide,
Such that it is able to by the first oxide layer together with the second oxide layer Direct Bonding, without additionally
Binding material.
S4, the second surface not preparing described structure to described substrate are ground subtracting
Thin.
After combining support chip 50 in structure overleaf, carry out the preparation of Facad structure, due in system
During work, in order to not damage substrate in manufacturing process, the thickness of general substrate all can be than reality
The thickness needed, therefore before preparing Facad structure, subtracts the surface preparing Facad structure
Thin, use the mode of grinding to carry out thinning in the present embodiment, meanwhile, other thining method
Same use and the application.
At the present embodiment, as it is shown in figure 5, owing to substrate has the support of support chip, therefore grind
During the intensity of substrate be guaranteed, its silicon chip substrate thinning can be reached 100um with
In, the thickness requirement of major part power device can be met completely.
S5, second surface after thinning prepare the Facad structure of described power device.
As shown in Figure 6, the substrate after thinning carries out the preparation of Facad structure 60, with the back side
Structure is identical, is not defined the preparation technology of Facad structure,
The preparation of the Facad structure of every kind of power device needs to use corresponding technique to be prepared, herein
No longer describe in detail.
S6, successively described support chip, the second oxide layer and the first oxide layer are removed, and in institute
State and in structure, prepare metal level.
After prepared by Facad structure, by the first oxide layer in structure, the second oxidation
Layer and support chip are removed, in the present embodiment, it is possible to use the mode of grinding removes support chip,
Owing to structure top is by the protection of oxide layer, therefore can be ground subtracting to support chip
Thin, until removing completely without infringement structure.
After support chip 50 is removed, the second oxide layer 40 and the first oxide layer 30 are removed, then
Metal level 70 is prepared overleaf, as it is shown in fig. 7, thus complete the preparation of power device in mechanism.
In another embodiment of the present invention, it is provided that a kind of power device, this power device leads to
Cross above-mentioned method to make.
The manufacture method of a kind of power device of the present invention and power device, making power
The substrate of device is placed on support chip, first making devices structure, such structure system
Technological temperature during work can not be limited, it is possible to increase device performance, it addition, this
The bright use material identical with substrate, as support chip, can improve the intensity of substrate, reduce
Fragment rate in technique, reduces device manufacturing cost.
Although being described in conjunction with the accompanying embodiments of the present invention, but those skilled in the art can
To make various modifications and variations without departing from the spirit and scope of the present invention, so
Amendment and within the scope of modification each falls within and is defined by the appended claims.
Claims (7)
1. the manufacture method of a power device, it is characterised in that described method includes:
S1, prepare the structure of described power device at the first surface of substrate；
S2, in described structure, prepare the first oxide layer；
S3, the support chip with the second oxide layer is attached to described first oxide layer, wherein,
The material of described first oxide layer and the material of the second oxide layer are identical, described first oxide layer with
Described second oxide layer is bonded together；
S4, the second surface not preparing described structure to described substrate are ground subtracting
Thin；
S5, second surface after thinning prepare the Facad structure of described power device；
S6, successively described support chip, the second oxide layer and the first oxide layer are removed, and in institute
State and in structure, prepare metal level.
Method the most according to claim 1, it is characterised in that described substrate is silicon chip.
Method the most according to claim 2, it is characterised in that described first oxide layer is
Silicon oxide layer, described silicon oxide layer is made by silicon chip is carried out thermal oxide.
Method the most according to claim 1, it is characterised in that described support chip is with described
The material of substrate is identical.
Method the most according to claim 1, it is characterised in that described second oxide layer is led to
Cross and described support chip is carried out thermal oxide be prepared from.
Method the most according to claim 1, it is characterised in that described support chip is by grinding
The method of mill is removed.
7. a power device, it is characterised in that described power device uses aforesaid right to want
The method described in 1-6 is asked to make.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510228095.7A CN106208781A (en) | 2015-05-06 | 2015-05-06 | The manufacture method of a kind of power device and power device |
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| CN201510228095.7A CN106208781A (en) | 2015-05-06 | 2015-05-06 | The manufacture method of a kind of power device and power device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109003885A (en) * | 2018-07-04 | 2018-12-14 | 上海晶盟硅材料有限公司 | Production method, epitaxial wafer and the semiconductor devices of twin polishing epitaxial wafer |
| CN111670159A (en) * | 2018-01-30 | 2020-09-15 | 法国原子能源和替代能源委员会 | Method for packaging a microelectronic device comprising a step of thinning the substrate and/or the package lid |
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| JP2003197633A (en) * | 2001-12-26 | 2003-07-11 | Toshiba Corp | Manufacturing method for semiconductor device |
| US20130316498A1 (en) * | 2008-12-10 | 2013-11-28 | Denso Corporation | Method of manufacturing semiconductor device including insulated gate bipolar transistor and diode |
| CN102110605A (en) * | 2009-12-24 | 2011-06-29 | 北大方正集团有限公司 | Method and device for manufacturing insulated gate bipolar transistor (IGBT) chip |
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| CN111670159A (en) * | 2018-01-30 | 2020-09-15 | 法国原子能源和替代能源委员会 | Method for packaging a microelectronic device comprising a step of thinning the substrate and/or the package lid |
| CN111670159B (en) * | 2018-01-30 | 2024-04-09 | 法国原子能源和替代能源委员会 | Method for packaging a microelectronic device comprising a step of thinning a substrate and/or a packaging lid |
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