CN106208678A - A kind of electric charge pump and memorizer - Google Patents
A kind of electric charge pump and memorizer Download PDFInfo
- Publication number
- CN106208678A CN106208678A CN201610556219.9A CN201610556219A CN106208678A CN 106208678 A CN106208678 A CN 106208678A CN 201610556219 A CN201610556219 A CN 201610556219A CN 106208678 A CN106208678 A CN 106208678A
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- charge pump
- nmos tube
- capacitor
- clock signal
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- 239000003990 capacitor Substances 0.000 claims abstract description 77
- 230000005611 electricity Effects 0.000 claims description 5
- 230000005540 biological transmission Effects 0.000 abstract description 7
- 238000000034 method Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 235000006508 Nelumbo nucifera Nutrition 0.000 description 1
- 240000002853 Nelumbo nucifera Species 0.000 description 1
- 235000006510 Nelumbo pentapetala Nutrition 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 238000004146 energy storage Methods 0.000 description 1
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- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
- H02M3/077—Charge pumps of the Schenkel-type with parallel connected charge pump stages
Abstract
The present invention provides a kind of electric charge pump and memorizer, electric charge pump includes at least two group charge pump circuits, and charge pump circuit includes initial level circuit and the output-stage circuit being connected with initial level circuit, and initial level circuit includes the first NMOS tube, source is connected with power supply respectively with grid end, and drain terminal is as outfan；Output-stage circuit includes: one end of the first capacitor provides end or second clock signal to provide end to be connected with one end of the second capacitor respectively with the first clock signal；Second NMOS tube, source is connected with the outfan of front stage circuits and the other end of the first capacitor respectively, and the other end of grid end and the second capacitor is connected, and source is as input, and drain terminal is as outfan；3rd NMOS tube, source is connected with the source of the second NMOS tube, and grid end is connected with the input of output-stage circuit in another charge pump circuit, and the other end of drain terminal and the second capacitor is connected.The present invention effectively reduces voltage transmission loss, greatly improves the efficiency of electric charge pump.
Description
Technical field
The present invention relates to circuit engineering field, particularly relate to a kind of electric charge pump and a kind of memorizer.
Background technology
Electric charge pump, as the basic module of flash storage, has been largely fixed the program/erase speed of Flash.
Progress along with integrated circuit fabrication process, the pursuit to low-power consumption, the supply voltage of integrated circuit constantly declines, meanwhile,
In flash storage, the program/erase operation of memory element remains a need for higher voltage, and this allows at integrated circuit not
In disconnected evolution, electric charge pump progressively shows its consequence.
Electric charge pump is also referred to as switched capacitor voltage changer, is that one utilizes so-called " soon " (flying) or " pumping "
Electric capacity (rather than inductance or transformator) carrys out DC-DC (DC-to-dc) changer of energy storage.Electric charge pump can make input voltage raise or
Reducing, the switch arrays within the utilization of electric charge pump control the transmission of electric charge on electric capacity, in some way generally with clock signal
Control the discharge and recharge of electric capacity in electric charge pump, so that input voltage raises (or reduction) in some way, to reach required
Output voltage.
Conventional charge pump structure is as shown in Figure 1.In Fig. 1, electric charge pump includes that (i.e. electric charge pump passes 7 electric charge pump transfer tubes
Defeated pipe N1 ', electric charge pump transfer tube N2 ', electric charge pump transfer tube N3 ', electric charge pump transfer tube N4 ', electric charge pump transfer tube N5 ', electric charge
Pump transfer tube N6 ', electric charge pump transfer tube N7 ') and 6 electric capacity (i.e. electric capacity C1 ', electric capacity C2 ', electric capacity C3 ', electric capacity C4 ', electric capacity
C5 ', electric capacity C6 ', electric capacity C7 '), it is non-overlapping clock letter that 7 electric charge pump transfer tubes are connected into diode, clk ' and clkb '
Number.
In conventional charge pump, each electric charge pump transfer tube can have the loss of threshold voltage, therefore, the effect of conventional charge pump
Rate is the lowest.
Summary of the invention
In view of the above problems, the purpose of the embodiment of the present invention is to provide a kind of electric charge pump and a kind of memorizer, to solve
The problem that the efficiency of conventional charge pump is the lowest.
In order to solve the problems referred to above, the embodiment of the invention discloses a kind of electric charge pump, described electric charge pump includes at least two groups
Charge pump circuit, described charge pump circuit for being promoted to setting voltage value and exporting, described charge pump circuit by supply voltage
Including initial level circuit and the output-stage circuit that is connected with described initial level circuit, wherein,
Described initial level circuit includes the first NMOS tube, the source of described first NMOS tube and grid end respectively with power supply phase
Even, the drain terminal of described first NMOS tube is as the outfan of described initial level circuit；
Described output-stage circuit includes the second NMOS tube, the 3rd NMOS tube, the first capacitor and the second capacitor, wherein,
One end of described first capacitor and one end of described second capacitor respectively with first clock signal provide end or
Second clock signal provides end to be connected；Described first clock signal provides the first clock signal of end offer and described second clock
The second clock signal that signal provides end to provide is non-overlapping clock signal；
The source of described second NMOS tube respectively with the outfan of the front stage circuits of described output-stage circuit and described first
The other end of capacitor is connected, and the grid end of described second NMOS tube is connected with the other end of described second capacitor, and described second
The source of NMOS tube is as the input of described output-stage circuit, and the drain terminal of described second NMOS tube is as described output-stage circuit
Outfan；
The source of described 3rd NMOS tube is connected with the source of described second NMOS tube, the grid end of described 3rd NMOS tube with
In another charge pump circuit, the input of output-stage circuit is connected, the drain terminal of described 3rd NMOS tube and described second capacitor
The other end is connected.
Alternatively, described charge pump circuit also includes M intergrade circuit, described initial level circuit, described M intergrade
Circuit, described output-stage circuit are sequentially connected in series, and M is the integer more than or equal to 0, and described intergrade circuit includes the 4th NMOS
Pipe, the 5th NMOS tube, the 3rd capacitor and the 4th capacitor, wherein,
When front stage circuits and/or the late-class circuit of described intergrade circuit provide end to be connected with described first clock signal
Time, one end of described 3rd capacitor and one end of described 4th capacitor provide end phase with described second clock signal respectively
Even, and when the front stage circuits of described intergrade circuit and/or late-class circuit provide end to be connected with described second clock signal,
One end of described 3rd capacitor provides end to be connected with described first clock signal with one end of described 4th capacitor respectively；
The source of described 4th NMOS tube respectively with the outfan and the described 3rd of the front stage circuits of described intergrade circuit
The other end of capacitor is connected, and the grid end of described 4th NMOS tube is connected with the other end of described 4th capacitor, and the described 4th
The source of NMOS tube is as the input of described intergrade circuit, and the drain terminal of described 4th NMOS tube is as described intergrade circuit
Outfan；
The source of described 5th NMOS tube is connected with the source of described 4th NMOS tube, the grid end of described 5th NMOS tube with
The drain terminal of described 4th NMOS tube is connected, and the drain terminal of described 5th NMOS tube is connected with the other end of described 4th capacitor.
Alternatively, the quantity of described intergrade circuit is three.
Alternatively, the first intergrade circuit in described three intergrade circuit and the 3rd intergrade circuit are respectively with described
First clock signal provides end to be connected, and the second intergrade circuit in described output-stage circuit and described three intergrade circuit divides
End is not provided to be connected with described second clock signal.
Alternatively, the first intergrade circuit in described three intergrade circuit and the 3rd intergrade circuit are respectively with described
Second clock signal provides end to be connected, and the second intergrade circuit in described output-stage circuit and described three intergrade circuit divides
End is not provided to be connected with described first clock signal.
Alternatively, the quantity of described charge pump circuit is two groups.
Specifically, when one end of described first capacitor of one group of charge pump circuit and institute in described two groups of charge pump circuits
State one end of the second capacitor when providing end to be connected with described first clock signal respectively, described in another group charge pump circuit the
One end of one capacitor provides end to be connected with described first clock signal with one end of described second capacitor respectively；When described two
Organize one end of described first capacitor of one group of charge pump circuit in charge pump circuit and one end difference of described second capacitor
When providing end to be connected with described second clock signal, one end and described the of the first capacitor described in another group charge pump circuit
One end of two capacitors provides end to be connected with described second clock signal respectively.
Specifically, described charge pump circuit is positive voltage charge pump circuit.
In order to solve the problems referred to above, the embodiment of the invention also discloses a kind of memorizer, including the electricity at least one described
Lotus pump.
The embodiment of the present invention includes advantages below: arranges electric charge pump and includes at least two group charge pump circuits, charge pump circuit
Including initial level circuit and the output-stage circuit that is connected with initial level circuit, wherein, the first NMOS tube in initial level circuit, with
And the second NMOS tube and the 3rd NMOS tube in output-stage circuit is not connected into diode, but make as switching tube
With, such voltage transmission loss only has the voltage difference between source and the drain terminal of each NMOS tube, and this voltage difference is the least, especially when
When the grid terminal voltage of NMOS tube is the highest, this voltage difference can be less than 10mv, therefore, greatly improves the efficiency of electric charge pump.
Accompanying drawing explanation
Fig. 1 is conventional charge pump structure schematic diagram；
Fig. 2 is the structural representation of a kind of electric charge pump embodiment of the present invention；
Fig. 3 be the present invention a kind of electric charge pump embodiment in the first clock signal and the schematic diagram of second clock signal；
Fig. 4 is the structural representation of the another kind of electric charge pump embodiment of the present invention.
Detailed description of the invention
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, real with concrete below in conjunction with the accompanying drawings
The present invention is further detailed explanation to execute mode.
With reference to Fig. 2, it is shown that the structural representation of a kind of electric charge pump embodiment of the present invention, this electric charge pump includes at least two
Group charge pump circuit 1, charge pump circuit 1 is for being promoted to setting voltage value VOUT by supply voltage VDD and exporting, and electric charge pump is electric
Road 1 includes initial level circuit 10 and the output-stage circuit 20 being connected with initial level circuit 10, and wherein, initial level circuit 10 includes
One NMOS tube N1, the source of the first NMOS tube N1 is connected with power supply respectively with grid end, power supply output supply voltage VDD, and first
The drain terminal of NMOS tube N1 is as the outfan of initial level circuit 10；Output-stage circuit 20 includes the second NMOS tube N2, the 3rd NMOS
Pipe N3, the first capacitor C1 and the second capacitor C2, wherein, one end of the first capacitor C1 and one end of the second capacitor C2 are divided
Do not provide end or second clock signal to provide end to be connected with the first clock signal；With reference to Fig. 3, the first clock signal provides end to provide
The first clock signal clk and the second clock signal second clock signal clkb that provides end to provide be non-overlapping clock signal,
The amplitude of oscillation of the first clock signal clk, the amplitude of oscillation of second clock signal clkb can be VDD；The source of the second NMOS tube N2 is respectively
It is connected with the outfan of front stage circuits and the other end of the first capacitor C1 of output-stage circuit 20, the grid end of the second NMOS tube N2
Be connected with the other end of the second capacitor C2, the source of the second NMOS tube N2 as the input of output-stage circuit 20, second
The drain terminal of NMOS tube N2 is as the outfan of output-stage circuit 20；The source of the 3rd NMOS tube N3 and the source of the second NMOS tube N2
Being connected, the grid end of the 3rd NMOS tube N3 is connected with the input of output-stage circuit 20 in another charge pump circuit 1, the 3rd NMOS tube
The drain terminal of N3 and the other end of the second capacitor C2 are connected.
In the embodiment of the present invention, the first NMOS tube N1 in initial level circuit 10, and second in output-stage circuit 20
NMOS tube N2 and the 3rd NMOS tube N3 are not connected into diode, but use as switching tube, and the transmission of such voltage is damaged
Losing the voltage difference between source and the drain terminal of only each NMOS tube, this voltage difference is the least, especially when the grid terminal voltage of NMOS tube
Time the highest, this voltage difference can be less than 10mv, therefore, greatly improves the efficiency of electric charge pump.
Alternatively, in another embodiment of the present invention, charge pump circuit 1 can also include M intergrade circuit, just
Beginning level circuit 10, M intergrade circuit, output-stage circuit 20 are sequentially connected in series, and M is the integer more than or equal to 0, intergrade circuit
The 4th NMOS tube N4, the 5th NMOS tube N5, the 3rd capacitor C3 and the 4th capacitor C4 can be included, wherein, when intergrade electricity
When the front stage circuits on road and/or late-class circuit and the first clock signal provide end to be connected, one end and the 4th of the 3rd capacitor C3
One end of capacitor C4 respectively with second clock signal provide end be connected, and when intergrade circuit front stage circuits and/or after
When level circuit and second clock signal provide end to be connected, one end of the 3rd capacitor C3 and one end of the 4th capacitor C4 respectively with
First clock signal provides end to be connected；The source of the 4th NMOS tube N4 respectively with the outfan of the front stage circuits of intergrade circuit and
The other end of the 3rd capacitor C3 is connected, and the grid end of the 4th NMOS tube N4 and the other end of the 4th capacitor C4 are connected, and the 4th
The source of NMOS tube N4 is as the input of intergrade circuit, and the drain terminal of the 4th NMOS tube N4 is as the output of intergrade circuit
End；The source of the 5th NMOS tube N5 is connected with the source of the 4th NMOS tube N4, the grid end of the 5th NMOS tube N5 and the 4th NMOS tube
The drain terminal of N4 is connected, and the drain terminal of the 5th NMOS tube N5 and the other end of the 4th capacitor C4 are connected.
In one embodiment of the invention, with reference to Fig. 4, the quantity of intergrade circuit can be three.In Fig. 4, three
The first intergrade circuit 31 in intergrade circuit provides end to be connected with second clock signal with the 3rd intergrade circuit 33 respectively,
Output-stage circuit 20 provides end to be connected with the first clock signal with the second intergrade circuit 32 in three intergrade circuit respectively.
In another embodiment of the present invention, in the middle of the first intergrade circuit 31 and the 3rd in three intergrade circuit
Level circuit 33 can provide end to be connected with the first clock signal respectively, second in output-stage circuit 20 and three intergrade circuit
Intergrade circuit 32 can provide end to be connected with second clock signal respectively.
Alternatively, with reference to Fig. 2 and Fig. 4, the quantity of charge pump circuit 1 can be two groups.Wherein, when two groups of charge pump circuits
In 1 one end of one end of first capacitor C1 of one group of charge pump circuit 1 and the second capacitor C2 respectively with the first clock signal
End when being connected is provided, in another group charge pump circuit 1 one end of one end of first capacitor C1 and the second capacitor C2 respectively with
First clock signal provides end to be connected；When one end of the first capacitor C1 of one group of charge pump circuit 1 in two groups of charge pump circuits 1
When providing end to be connected with second clock signal respectively with one end of the second capacitor C2, the first electricity in another group charge pump circuit 1
One end of container C1 provides end to be connected with second clock signal with one end of the second capacitor C2 respectively.
Specifically, charge pump circuit 1 can be positive voltage charge pump circuit.
Being below the operation principle of the charge pump circuit 1 of top half in Fig. 4: when charge pump, a point voltage is almost
Equal to VDD-Vt, wherein Vt is the threshold voltage of the first NMOS tube N1.The when that second clock signal clkb being high, a point voltage
For VDD+ (VDD-Vt), b point voltage is also high, owing at initial time, b point voltage can be precharged to VDD-Vt, so this
Time b point voltage be about VDD+ (VDD-Vt), in the first intergrade circuit 31 the 4th NMOS tube N4 conducting, electric charge is transferred to c from a point
Point, c point voltage is VDD+ (VDD-Vt), now, in the first intergrade circuit 31 at the 3rd capacitor C3 and the 4th capacitor C4
In charged state.When the first clock signal clk is high when, second clock signal clkb is low, and c point voltage is 2*VDD+
(VDD-Vt), c point voltage makes the 5th NMOS tube N5 conducting, the grid end of the 4th NMOS tube N4 and source short circuit, thus blocks the 4th
NMOS tube N4 turns on, and electric charge cannot be transferred to c point, now, the 3rd capacitor C3 and the 4th in the first intergrade circuit 31 from a point
Capacitor C4 is in discharge condition.In above procedure, the first NMOS tube N1, the 4th NMOS tube N4 and the 5th NMOS tube N5 are only used as
Switching tube uses, and such voltage transmission loss only has the voltage difference between source and the drain terminal of each NMOS tube, and this voltage difference is the least,
Thus greatly improve charge transfer efficiency.Second intergrade circuit the 32, the 3rd intergrade circuit 33 and output-stage circuit 20
Operation principle be similar to, below repeat no more.Electric charge pump shown in Fig. 2 by constantly each electric capacity being charged and discharged,
Output voltage is finally made to reach setting voltage value VOUT.
It should be noted that for output-stage circuit 20, if the grid end of the 3rd NMOS tube N3 and the second NMOS tube N2
Drain terminal is connected, then when the first clock signal clk is low, the source voltage terminal of the second NMOS tube N2 is about VOUT+Vds-2*
VDD, and the grid terminal voltage of the second NMOS tube N2 is also about VOUT+Vds-2*VDD.Now, if the grid of the 3rd NMOS tube N3
If terminal voltage is controlled by the drain terminal voltage of the second NMOS tube N2, it is likely that occur that the drain terminal voltage of the second NMOS tube N2 is less than
The source voltage terminal of the second NMOS tube N2 and the situation of the grid terminal voltage of the 3rd NMOS tube N3, cause the second NMOS tube N2 to close
Disconnected, then originally to give the electric charge of the source charging of the second NMOS tube N2, will be by the 4th of the 3rd intergrade circuit 33 the
NMOS tube N4 leaks into the drain terminal of the second NMOS tube N2, causes the electric charge efficiency of pump to reduce.
The embodiment of the present invention includes advantages below: arranges electric charge pump and includes at least two group charge pump circuits, charge pump circuit
Including initial level circuit and the output-stage circuit that is connected with initial level circuit, wherein, the first NMOS tube in initial level circuit, with
And the second NMOS tube and the 3rd NMOS tube in output-stage circuit is not connected into diode, but make as switching tube
With；Or charge pump circuit includes initial level circuit, M intergrade circuit and output-stage circuit, wherein, in initial level circuit
One NMOS tube, the second NMOS tube in output-stage circuit and the 4th NMOS tube in the 3rd NMOS tube, and intergrade circuit and
5th NMOS tube is not connected into diode, but uses as switching tube, and such voltage transmission loss only has each NMOS
Voltage difference between source and the drain terminal of pipe, this voltage difference is the least, especially when the grid terminal voltage of NMOS tube is the highest, this voltage
Difference can be less than 10mv, therefore, greatly improves the efficiency of electric charge pump.
It addition, the embodiment of the invention also discloses a kind of memorizer, including the electric charge pump that at least one is above-mentioned.
The embodiment of the present invention includes advantages below: arranges electric charge pump and includes at least two group charge pump circuits, charge pump circuit
Including initial level circuit and the output-stage circuit that is connected with initial level circuit, wherein, the first NMOS tube in initial level circuit, with
And the second NMOS tube and the 3rd NMOS tube in output-stage circuit is not connected into diode, but make as switching tube
With；Or charge pump circuit includes initial level circuit, M intergrade circuit and output-stage circuit, wherein, in initial level circuit
One NMOS tube, the second NMOS tube in output-stage circuit and the 4th NMOS tube in the 3rd NMOS tube, and intergrade circuit and
5th NMOS tube is not connected into diode, but uses as switching tube, and such voltage transmission loss only has each NMOS
Voltage difference between source and the drain terminal of pipe, this voltage difference is the least, especially when the grid terminal voltage of NMOS tube is the highest, this voltage
Difference can be less than 10mv, therefore, greatly improves the efficiency of electric charge pump, memorizer.
Owing to memorizer includes electric charge pump, so the description of memorizer embodiment is fairly simple, relevant part sees electric charge
The part of pump embodiment illustrates.
Each embodiment in this specification all uses the mode gone forward one by one to describe, what each embodiment stressed is with
The difference of other embodiments, between each embodiment, identical similar part sees mutually.
Although having been described for the preferred embodiment of the embodiment of the present invention, but those skilled in the art once knowing base
This creativeness concept, then can make other change and amendment to these embodiments.So, claims are intended to be construed to
The all changes including preferred embodiment and falling into range of embodiment of the invention and amendment.
Finally, in addition it is also necessary to explanation, in this article, the relational terms of such as first and second or the like be used merely to by
One entity or operation separate with another entity or operating space, and not necessarily require or imply these entities or operation
Between exist any this reality relation or order.And, term " includes ", " comprising " or its any other variant meaning
Containing comprising of nonexcludability, so that include that the process of a series of key element, method, article or terminal unit not only wrap
Include those key elements, but also include other key elements being not expressly set out, or also include for this process, method, article
Or the key element that terminal unit is intrinsic.In the case of there is no more restriction, by wanting that statement " including ... " limits
Element, it is not excluded that there is also other identical element in including the process of described key element, method, article or terminal unit.
Above to a kind of electric charge pump provided by the present invention and a kind of memorizer, it is described in detail, used herein
Principle and the embodiment of the present invention are set forth by specific case, and the explanation of above example is only intended to help to understand
The method of the present invention and core concept thereof；Simultaneously for one of ordinary skill in the art, according to the thought of the present invention, at tool
All will change on body embodiment and range of application, in sum, this specification content should not be construed as the present invention
Restriction.
Claims (9)
1. an electric charge pump, it is characterised in that described electric charge pump includes at least two group charge pump circuits, described charge pump circuit is used
In supply voltage being promoted to setting voltage value and exporting, described charge pump circuit include initial level circuit and with described initial level
The output-stage circuit that circuit is connected, wherein,
Described initial level circuit includes that the first NMOS tube, the source of described first NMOS tube are connected with power supply respectively with grid end, institute
State the drain terminal outfan as described initial level circuit of the first NMOS tube；
Described output-stage circuit includes the second NMOS tube, the 3rd NMOS tube, the first capacitor and the second capacitor, wherein,
One end of described first capacitor and one end of described second capacitor provide end or second with the first clock signal respectively
Clock signal provides end to be connected；Described first clock signal provides the first clock signal of end offer and described second clock signal
The second clock signal providing end to provide is non-overlapping clock signal；
The source of described second NMOS tube respectively with the outfan of the front stage circuits of described output-stage circuit and described first electric capacity
The other end of device is connected, and the grid end of described second NMOS tube is connected with the other end of described second capacitor, described 2nd NMOS
The source of pipe as the input of described output-stage circuit, defeated as described output-stage circuit of the drain terminal of described second NMOS tube
Go out end；
The source of described 3rd NMOS tube is connected with the source of described second NMOS tube, the grid end of described 3rd NMOS tube and another
In charge pump circuit, the input of output-stage circuit is connected, another of the drain terminal of described 3rd NMOS tube and described second capacitor
End is connected.
Electric charge pump the most according to claim 1, it is characterised in that described charge pump circuit also includes M intergrade circuit,
Described initial level circuit, described M intergrade circuit, described output-stage circuit are sequentially connected in series, and M is the integer more than or equal to 0,
Described intergrade circuit includes the 4th NMOS tube, the 5th NMOS tube, the 3rd capacitor and the 4th capacitor, wherein,
When the front stage circuits of described intergrade circuit and/or late-class circuit provide end to be connected with described first clock signal, institute
One end of one end and described 4th capacitor of stating the 3rd capacitor provides end to be connected with described second clock signal respectively, and
When the front stage circuits of described intergrade circuit and/or late-class circuit provide end to be connected with described second clock signal, described the
One end of three capacitors provides end to be connected with described first clock signal with one end of described 4th capacitor respectively；
The source of described 4th NMOS tube respectively with the outfan of the front stage circuits of described intergrade circuit and described 3rd electric capacity
The other end of device is connected, and the grid end of described 4th NMOS tube is connected with the other end of described 4th capacitor, described 4th NMOS
The source of pipe as the input of described intergrade circuit, defeated as described intergrade circuit of the drain terminal of described 4th NMOS tube
Go out end；
The source of described 5th NMOS tube is connected with the source of described 4th NMOS tube, and the grid end of described 5th NMOS tube is with described
The drain terminal of the 4th NMOS tube is connected, and the drain terminal of described 5th NMOS tube is connected with the other end of described 4th capacitor.
Electric charge pump the most according to claim 2, it is characterised in that the quantity of described intergrade circuit is three.
Electric charge pump the most according to claim 3, it is characterised in that the first intergrade electricity in described three intergrade circuit
Road and the 3rd intergrade circuit provide end to be connected with described first clock signal respectively, in described output-stage circuit and described three
The second intergrade circuit in intercaste circuit provides end to be connected with described second clock signal respectively.
Electric charge pump the most according to claim 3, it is characterised in that the first intergrade electricity in described three intergrade circuit
Road and the 3rd intergrade circuit provide end to be connected with described second clock signal respectively, in described output-stage circuit and described three
The second intergrade circuit in intercaste circuit provides end to be connected with described first clock signal respectively.
Electric charge pump the most according to claim 1, it is characterised in that the quantity of described charge pump circuit is two groups.
Electric charge pump the most according to claim 6, it is characterised in that
When one end of described first capacitor of one group of charge pump circuit and described second electric capacity in described two groups of charge pump circuits
When one end of device provides end to be connected with described first clock signal respectively, the first capacitor described in another group charge pump circuit
One end provides end to be connected with described first clock signal with one end of described second capacitor respectively；
When one end of described first capacitor of one group of charge pump circuit and described second electric capacity in described two groups of charge pump circuits
When one end of device provides end to be connected with described second clock signal respectively, the first capacitor described in another group charge pump circuit
One end provides end to be connected with described second clock signal with one end of described second capacitor respectively.
Electric charge pump the most according to claim 1, it is characterised in that described charge pump circuit is positive voltage charge pump circuit.
9. a memorizer, it is characterised in that include that at least one is according to the electric charge pump according to any one of claim 1-8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610556219.9A CN106208678B (en) | 2016-07-14 | 2016-07-14 | A kind of charge pump and memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610556219.9A CN106208678B (en) | 2016-07-14 | 2016-07-14 | A kind of charge pump and memory |
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| CN106208678A true CN106208678A (en) | 2016-12-07 |
| CN106208678B CN106208678B (en) | 2019-05-31 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5982223A (en) * | 1997-06-20 | 1999-11-09 | Integrated Silicon Solution, Inc. | Charge pump system with improved programming current distribution |
| US20050212586A1 (en) * | 2003-12-19 | 2005-09-29 | Jean-Michel Daga | High efficiency, low cost, charge pump circuit |
| CN1825485A (en) * | 2005-02-24 | 2006-08-30 | 旺宏电子股份有限公司 | Multi-pattern multi-stage charge pump |
-
2016
- 2016-07-14 CN CN201610556219.9A patent/CN106208678B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5982223A (en) * | 1997-06-20 | 1999-11-09 | Integrated Silicon Solution, Inc. | Charge pump system with improved programming current distribution |
| US20050212586A1 (en) * | 2003-12-19 | 2005-09-29 | Jean-Michel Daga | High efficiency, low cost, charge pump circuit |
| CN1825485A (en) * | 2005-02-24 | 2006-08-30 | 旺宏电子股份有限公司 | Multi-pattern multi-stage charge pump |
Non-Patent Citations (1)
| Title |
|---|
| 李卿等: "一种完全消除阈值电压损失的低纹波高效电荷泵", 《微电子学与计算机》 * |
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| CN106208678B (en) | 2019-05-31 |
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Address after: 230601 Building 1, Pearl Plaza, Hefei Economic and Technological Development Zone, Anhui Province Patentee after: HEFEI GEYI INTEGRATED CIRCUIT Co.,Ltd. Patentee after: Zhaoyi Innovation Technology Group Co.,Ltd. Address before: 230601 Building 1, Pearl Plaza, Hefei Economic and Technological Development Zone, Anhui Province Patentee before: HEFEI GEYI INTEGRATED CIRCUIT Co.,Ltd. Patentee before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. |