CN106452426B - A kind of N pipe feedback-type bootstrapping adiabatic circuits and level Four inverters/buffers - Google Patents
A kind of N pipe feedback-type bootstrapping adiabatic circuits and level Four inverters/buffers Download PDFInfo
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- CN106452426B CN106452426B CN201610836630.1A CN201610836630A CN106452426B CN 106452426 B CN106452426 B CN 106452426B CN 201610836630 A CN201610836630 A CN 201610836630A CN 106452426 B CN106452426 B CN 106452426B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
Abstract
The invention discloses a kind of N pipe feedback-type bootstrapping adiabatic circuits and level Four inverters/buffers, N pipe feedback-type bootstrapping adiabatic circuits include the first PMOS tube, the second PMOS tube, the first NMOS tube, the second NMOS tube, third NMOS tube, the 4th NMOS tube, the 5th NMOS tube and the 6th NMOS tube, and level Four inverters/buffers include four N pipe feedback-types bootstrapping adiabatic circuits；Advantage is that circuit structure is simple, delay and power consumption are all reduced, feed back the setting of the 5th NMOS tube of pipe or the 6th NMOS tube, so that in the energy regenerating stage, the energy regenerating of output node is more thorough to power clock, it avoids because PMOS threshold voltage prevents output node to cause energy loss from being fully retrieved to due to power clock is gone, power consumption obtains very big optimization, thus, for level Four inverters/buffers of the invention on the basis of not influencing circuit performance, delay, power consumption and power-consumption design are smaller.
Description
Technical field
The present invention relates to a kind of adiabatic circuits, more particularly, to a kind of N pipe feedback-type bootstrapping adiabatic circuits and level Four reverse phase
Device/buffer.
Background technique
Adiabatic circuits are a kind of double track inputs, and double track export structure circuit breaks traditional energy transmission mode, by original
Power supply-output node-the ground come is converted into from power supply-output node-power supply.Adiabatic circuits use alternating source driving circuit,
By alternating source to output node charging complete assignment, and by recycling nod charge to power supply, energy recovery is realized.It is existing
Insulation ECRL structural insulation circuit circuit diagram such as Fig. 1 (a) shown in, shown in graphical diagram such as Fig. 1 (b), using the insulation
The structure charts of the level Four inverters/buffers of ECRL structural insulation circuit design as shown in Fig. 2, the four phases power clock figure wave
Shape figure is as shown in Figure 3.In insulation ECRL structural insulation circuit, metal-oxide-semiconductor due to threshold voltage presence so that energy is pre-
Filling stage and energy recovery phase cannot all be able to all discharge or recycle, in addition, causing circuit since its output end is hanging
Additional power consumption increases the unstability of circuit.And for ECRL structural insulation circuit, load is bigger, caused by
Nonadiabatic power consumption is bigger, and delay also compares larger.
Summary of the invention
The first technical problem to be solved by the present invention is to provide one kind on the basis of not influencing circuit performance, delay,
Power consumption and the lesser N pipe feedback-type bootstrapping adiabatic circuits of power-consumption design.
The present invention solves technical solution used by one of above-mentioned technical problem are as follows: a kind of N pipe feedback-type bootstrapping insulation electricity
Road, including the first PMOS tube, the second PMOS tube, the first NMOS tube, the second NMOS tube, third NMOS tube, the 4th NMOS tube, the 5th
NMOS tube and the 6th NMOS tube；The source electrode of first PMOS tube, the source electrode of second PMOS tube, the third
The drain electrode of NMOS tube and the drain electrode connection of the 4th NMOS tube and its connecting pin are the N pipe feedback-type bootstrapping insulation electricity
First clock end on road, the drain electrode of first PMOS tube, the grid of second PMOS tube, first NMOS tube
Drain electrode, the third NMOS tube source electrode connected with the grid of the 5th NMOS tube and its connecting pin be the N
The output end of pipe feedback-type bootstrapping adiabatic circuits, the grid of first PMOS tube, the drain electrode of second PMOS tube, institute
The drain electrode for the second NMOS tube stated, the 4th NMOS tube source electrode connected with the grid of the 6th NMOS tube and its connect
The reversed-phase output that end is the N pipe feedback-type bootstrapping adiabatic circuits is connect, the grid of first NMOS tube is the N
The inverting input terminal of pipe feedback-type bootstrapping adiabatic circuits, the grid of second NMOS tube are that the N pipe feedback-type is booted
The input terminal of adiabatic circuits, the source grounding of the source electrode of first NMOS tube and second NMOS tube；Described
The grid of third NMOS tube is connected with the drain electrode of the 5th NMOS tube, the grid of the 4th NMOS tube and described
The drain electrode of six NMOS tubes connects, and the source electrode of the 5th NMOS tube is connected with the source electrode of the 6th NMOS tube and it is connected
End is the second clock end of the N pipe feedback-type bootstrapping adiabatic circuits；The first of the N pipe feedback-type bootstrapping adiabatic circuits
The second clock of clock end and N pipe feedback-type bootstrapping adiabatic circuits terminate into clock signal amplitude it is identical, but phase
90 degree of phase difference.
The breadth length ratio of first PMOS tube and second PMOS tube is5th NMOS tube, institute
The width for the 6th NMOS tube stated it is long than forFirst NMOS tube, second NMOS tube, the third
The breadth length ratio of NMOS tube and the 4th NMOS tube isIn the circuit, the width of the 5th NMOS tube and the 6th NMOS tube is long
Than forThe connecting node or the 4th NMOS tube of the drain electrode of the grid and the 5th NMOS tube for the third NMOS tube that can be improved
Grid and the 6th NMOS tube drain electrode connecting node voltage, energy is further sufficiently returned in recovery stage
It receives, is further reduced power consumption；The breadth length ratio of first PMOS tube and the second PMOS tube isFirst NMOS tube, the 2nd NMOS
Pipe, third NMOS tube and the 4th NMOS tube breadth length ratio beIt can guarantee the performance and optimum noise tolerance of circuit.
Compared with prior art, N pipe feedback-type of the invention boot adiabatic circuits the advantages of be by the first PMOS tube,
Second PMOS tube, the first NMOS tube, the second NMOS tube, third NMOS tube, the 4th NMOS tube, the 5th NMOS tube and the 6th NMOS tube
This eight metal-oxide-semiconductors constitute N pipe feedback-type bootstrapping adiabatic circuits, and circuit structure is simple, and delay and power consumption are all reduced, and first
The drain electrode of the source electrode of PMOS tube, the source electrode of the second PMOS tube, third NMOS tube is connected with the drain electrode of the 4th NMOS tube and it is connected
End is the first clock end of N pipe feedback-type bootstrapping adiabatic circuits, the drain electrode of the first PMOS tube, the grid of the second PMOS tube, first
The grid of the drain electrode of NMOS tube, the source electrode of third NMOS tube and the 5th NMOS tube connects and its connecting pin is the bootstrapping of N pipe feedback-type
The output end of adiabatic circuits, the grid of the first PMOS tube, the drain electrode of the second PMOS tube, the drain electrode of the second NMOS tube, the 4th NMOS
The source electrode of pipe and the connection of the grid of the 6th NMOS tube and its connecting pin are the reversed-phase output of N pipe feedback-type bootstrapping adiabatic circuits,
The grid of first NMOS tube is the inverting input terminal of N pipe feedback-type bootstrapping adiabatic circuits, and the grid of the second NMOS tube is N pipe feedback
The input terminal of type bootstrapping adiabatic circuits, the source grounding of the source electrode of the first NMOS tube and the second NMOS tube；Third NMOS tube
The drain electrode of grid and the 5th NMOS tube connects, the grid of the 4th NMOS tube and the drain electrode connection of the 6th NMOS tube, the 5th NMOS tube
Source electrode and the 6th NMOS tube source electrode connection and its connecting pin be N pipe feedback-type boot adiabatic circuits second clock end；N pipe
Feedback-type bootstrapping adiabatic circuits the first clock end and N pipe feedback-type bootstrapping adiabatic circuits second clock terminate into clock letter
Number amplitude is identical, but 90 degree of phase phase difference, during precharge and holding, N pipe feedback-type boot adiabatic circuits second when
Clock terminate into auxiliary power clock CLK2 to the connecting node A of the grid of third NMOS tube and the drain electrode of the 5th NMOS tube or
The connecting node B of the drain electrode of the grid of four NMOS tubes and the 6th NMOS tube charges, in energy regenerating node, due to feeding back pipe the 5th
NMOS tube or the cut-off of the 6th NMOS tube, then A node or B node keep certain level, so that third NMOS tube or the 4th NMSO
Pipe is held on, due to the coupling of capacitor, A node or B node bootstrapping, so that in the energy regenerating stage, output node
Energy regenerating is more thorough to power clock, avoids because PMOS threshold voltage prevents output node from being fully retrieved to power
Clock goes and causes energy loss, and power consumption obtains very big optimization, and N pipe feedback-type of the invention bootstrapping adiabatic circuits are not as a result,
On the basis of influencing circuit performance, delay, power consumption and power-consumption design are smaller.
The second technical problem to be solved by the present invention is to provide one kind on the basis of not influencing circuit performance, delay,
Power consumption and the lesser level Four inverters/buffers of power-consumption design.
The present invention solves technical solution used by the two of above-mentioned technical problem are as follows: a kind of level Four inverters/buffers, packet
Four N pipe feedback-type bootstrapping adiabatic circuits are included, the N pipe feedback-type bootstrapping adiabatic circuits described in each respectively include the first PMOS
Pipe, the second PMOS tube, the first NMOS tube, the second NMOS tube, third NMOS tube, the 4th NMOS tube, the 5th NMOS tube and the 6th
NMOS tube；The source electrode of first PMOS tube, the source electrode of second PMOS tube, the third NMOS tube drain electrode and
The drain electrode of 4th NMOS tube connects and its connecting pin is the first clock of the N pipe feedback-type bootstrapping adiabatic circuits
End, the drain electrode of first PMOS tube, the drain electrode, described of the grid of second PMOS tube, first NMOS tube
The source electrode of third NMOS tube connected with the grid of the 5th NMOS tube and its connecting pin is that the N pipe feedback-type is booted
The output end of adiabatic circuits, the grid of first PMOS tube, the drain electrode of second PMOS tube, the 2nd NMOS
The drain electrode of pipe, the 4th NMOS tube source electrode connected with the grid of the 6th NMOS tube and its connecting pin be it is described
The reversed-phase output of N pipe feedback-type bootstrapping adiabatic circuits, the grid of first NMOS tube are that the N pipe feedback-type is booted
The inverting input terminal of adiabatic circuits, the grid of second NMOS tube are the defeated of the N pipe feedback-type bootstrapping adiabatic circuits
Enter end, the source grounding of the source electrode of first NMOS tube and second NMOS tube；The third NMOS tube
Grid is connected with the drain electrode of the 5th NMOS tube, the grid of the 4th NMOS tube and the leakage of the 6th NMOS tube
Pole connection, the source electrode of the 5th NMOS tube is connected with the source electrode of the 6th NMOS tube and its connecting pin is the N
The second clock end of pipe feedback-type bootstrapping adiabatic circuits；N pipe feedback-type described in first bootstrapping adiabatic circuits input terminal be
The input terminal of the level Four inverters/buffers, the inverting input terminal of the bootstrapping adiabatic circuits of N pipe feedback-type described in first
For the inverting input terminal of the level Four inverters/buffers, the output of the bootstrapping adiabatic circuits of N pipe feedback-type described in first
It holds and is connected with the input terminal of the bootstrapping adiabatic circuits of N pipe feedback-type described in second, the bootstrapping of N pipe feedback-type described in first is exhausted
The inverting input terminal connection of the bootstrapping adiabatic circuits of N pipe feedback-type described in the reversed-phase output of heater circuit and second, second
The input of the output end and third of the N pipe feedback-type bootstrapping adiabatic circuits N pipe feedback-type bootstrapping adiabatic circuits
Connection is held, the reversed-phase output and third of the bootstrapping adiabatic circuits of N pipe feedback-type described in second the N pipe feedback-type are certainly
Lift the inverting input terminal connection of adiabatic circuits, the output end of the third N pipe feedback-type bootstrapping adiabatic circuits and the 4th
The input terminal of the N pipe feedback-type bootstrapping adiabatic circuits connects, and N pipe feedback-type bootstrapping adiabatic circuits is anti-described in third
The inverting input terminal connection of the bootstrapping adiabatic circuits of N pipe feedback-type described in phase output terminal and the 4th, the pipe of N described in the 4th are anti-
The output end of feedback type bootstrapping adiabatic circuits is the output end of the level Four inverters/buffers, the feedback of N pipe described in the 4th
The reversed-phase output of type bootstrapping adiabatic circuits is the reversed-phase output of the level Four inverters/buffers, N described in the 4th
The second clock of the first clock end and third of pipe feedback-type bootstrapping adiabatic circuits the N pipe feedback-type bootstrapping adiabatic circuits
End connection and its connecting pin are the first clock end of the level Four inverters/buffers, and N pipe feedback-type described in first is certainly
The first clock end for lifting adiabatic circuits is connected with the second clock end of the bootstrapping adiabatic circuits of N pipe feedback-type described in the 4th and it
Connecting pin is the second clock end of the level Four inverters/buffers, the bootstrapping adiabatic circuits of N pipe feedback-type described in first
The first clock end of second clock end and N pipe feedback-type described in second bootstrapping adiabatic circuits connect and its connecting pin is institute
The third clock end for the level Four inverters/buffers stated, the second clock of the bootstrapping adiabatic circuits of N pipe feedback-type described in second
First clock end of the end N pipe feedback-type bootstrapping adiabatic circuits described with third connects and its connecting pin is that the level Four is anti-
First clock end of the 4th clock end of phase device/buffer, the level Four inverters/buffers accesses the first clock signal,
The second clock of the level Four inverters/buffers is terminated into second clock signal, the level Four inverters/buffers
Third clock end accesses third clock signal, and the 4th clock end of the level Four inverters/buffers accesses the 4th clock letter
Number, the first clock signal, the second clock signal, the third clock signal and the 4th clock letter
Number amplitude it is identical, 90 degree of phase phase difference of first clock signal and the second clock signal, described first
The phase phase difference 180 degree of clock signal and the third clock signal, first clock signal and it is described 4th when
270 degree of the phase phase difference of clock signal.
The breadth length ratio of first PMOS tube and second PMOS tube is5th NMOS tube, institute
The width for the 6th NMOS tube stated it is long than forFirst NMOS tube, second NMOS tube, the third
The breadth length ratio of NMOS tube and the 4th NMOS tube isIn the circuit, the width of the 5th NMOS tube and the 6th NMOS tube is long
Than forThe connecting node or the 4th NMOS tube of the drain electrode of the grid and the 5th NMOS tube for the third NMOS tube that can be improved
Grid and the 6th NMOS tube drain electrode connecting node voltage, energy is further sufficiently returned in recovery stage
It receives, is further reduced power consumption；The breadth length ratio of first PMOS tube and the second PMOS tube isFirst NMOS tube, the 2nd NMOS
Pipe, third NMOS tube and the 4th NMOS tube breadth length ratio beIt can guarantee the performance and optimum noise tolerance of circuit.
Compared with prior art, the advantages of level Four inverters/buffers of the invention, is through four N pipe feedback-types certainly
It lifts adiabatic circuits and constitutes level Four inverters/buffers, level Four inverters/buffers include the first PMOS tube, the second PMOS tube, the
One NMOS tube, the second NMOS tube, third NMOS tube, the 4th NMOS tube, the 5th NMOS tube and the 6th NMOS tube this eight metal-oxide-semiconductors,
Circuit structure is simple, and delay and power consumption are all reduced, the source electrode of the first PMOS tube, the source electrode of the second PMOS tube, third
The drain electrode with the 4th NMOS tube that drains of NMOS tube connects and its connecting pin is the first clock of N pipe feedback-type bootstrapping adiabatic circuits
End, the drain electrode of the first PMOS tube, the grid of the second PMOS tube, the drain electrode of the first NMOS tube, the source electrode of third NMOS tube and the 5th
The grid of NMOS tube connects and its connecting pin is that N pipe feedback-type is booted the output ends of adiabatic circuits, the grid of the first PMOS tube, the
The drain electrode of two PMOS tube, the drain electrode of the second NMOS tube, the grid connection of the source electrode of the 4th NMOS tube and the 6th NMOS tube and its connect
The reversed-phase output that end is N pipe feedback-type bootstrapping adiabatic circuits is connect, the grid of the first NMOS tube is N pipe feedback-type bootstrapping insulation electricity
The inverting input terminal on road, the grid of the second NMOS tube are the input terminal of N pipe feedback-type bootstrapping adiabatic circuits, the source of the first NMOS tube
The source grounding of pole and the second NMOS tube；The drain electrode of the grid of third NMOS tube and the 5th NMOS tube connects, the 4th NMOS tube
Grid and the 6th NMOS tube drain electrode connection, the source electrode connection of the source electrode of the 5th NMOS tube and the 6th NMOS tube and its connecting pin
For the second clock end of N pipe feedback-type bootstrapping adiabatic circuits；The first clock end and N pipe of N pipe feedback-type bootstrapping adiabatic circuits are anti-
The second clock of feedback type bootstrapping adiabatic circuits terminate into clock signal amplitude it is identical, but 90 degree of phase phase difference, be pre-charged
With during holding, N pipe feedback-type bootstrapping adiabatic circuits second clock terminate into auxiliary power clock CLK2 to the 3rd NMOS
The company of the drain electrode of the grid and the 6th NMOS tube of the connecting node A or the 4th NMOS tube of the drain electrode of the grid of pipe and the 5th NMOS tube
Node B charging is connect, in energy regenerating node, due to feedback the 5th NMOS tube of pipe or the cut-off of the 6th NMOS tube, then A node or B are saved
Point keeps certain level, so that third NMOS tube or the 4th NMSO pipe are held on, due to the coupling of capacitor, A node
Or B node bootstrapping so that the energy regenerating of output node is more thorough to power clock in the energy regenerating stage, avoid because
PMOS threshold voltage goes output node from being fully retrieved to power clock and causes energy loss, and power consumption obtains very big excellent
Change, level Four inverters/buffers of the invention are not on the basis of influencing circuit performance as a result, delay, power consumption and power consumption delay
Product is smaller.
Detailed description of the invention
Fig. 1 (a) is the circuit diagram of existing insulation ECRL structural insulation circuit；
Fig. 1 (b) is the graphical diagram of existing insulation ECRL structural insulation circuit；
Fig. 2 is the structure chart of the existing level Four inverters/buffers based on ECRL structural insulation circuit；
Fig. 3 is four phase power clocks of the existing level Four inverters/buffers access based on ECRL structural insulation circuit
The waveform diagram of figure；
Fig. 4 (a) is the circuit diagram of N pipe feedback-type bootstrapping adiabatic circuits of the invention；
Fig. 4 (b) is the graphical diagram of N pipe feedback-type bootstrapping adiabatic circuits of the invention；
Fig. 4 (c) is the clock waveform figure of N pipe feedback-type bootstrapping adiabatic circuits of the invention；
Fig. 5 is the structure chart of level Four inverters/buffers of the invention；
Fig. 6 is the waveform diagram of four phase power clock figures of the access of level Four inverters/buffers of the invention；
Fig. 7 is under normal voltage (1v), and existing insulation ECRL structural insulation circuit is imitative under PTM32nm standard technology
True waveform diagram
Fig. 8 is under normal voltage (1v), and N pipe feedback-type bootstrapping adiabatic circuits of the invention are under PTM32nm standard technology
Simulation waveform.
Specific embodiment
The invention discloses a kind of N pipe feedback-type bootstrapping adiabatic circuits, manage below in conjunction with figure embodiment to N of the invention
Feedback-type bootstrapping adiabatic circuits are described in further detail.
Embodiment one: as shown in Fig. 4 (a), Fig. 4 (b) and Fig. 4 (c), a kind of N pipe feedback-type bootstrapping adiabatic circuits, including the
One PMOS tube P1, the second PMOS tube P2, the first NMOS tube N1, the second NMOS tube N2, third NMOS tube N3, the 4th NMOS tube N4,
5th NMOS tube N5 and the 6th NMOS tube N6；The source electrode of first PMOS tube P1, the source electrode of the second PMOS tube P2, third NMOS tube N3
Drain electrode and the 4th NMOS tube N4 drain electrode connection and its connecting pin be N pipe feedback-type boot adiabatic circuits the first clock end,
The drain electrode of first PMOS tube P1, the grid of the second PMOS tube P2, the drain electrode of the first NMOS tube N1, third NMOS tube N3 source electrode and
The grid of 5th NMOS tube N5 connects and its connecting pin is the output end of N pipe feedback-type bootstrapping adiabatic circuits, the first PMOS tube P1
Grid, the drain electrode of the second PMOS tube P2, the drain electrode of the second NMOS tube N2, the 4th NMOS tube N4 source electrode and the 6th NMOS tube N6
Grid connection and its connecting pin be that N pipe feedback-type is booted the reversed-phase outputs of adiabatic circuits, the grid of the first NMOS tube N1 is N
The inverting input terminal of pipe feedback-type bootstrapping adiabatic circuits, the grid of the second NMOS tube N2 are N pipe feedback-type bootstrapping adiabatic circuits
Input terminal, the source grounding of the source electrode of the first NMOS tube N1 and the second NMOS tube N2；The grid and the 5th of third NMOS tube N3
The drain electrode of NMOS tube N5 connects, the drain electrode connection of the grid and the 6th NMOS tube N6 of the 4th NMOS tube N4, the 5th NMOS tube N5's
The connection of the source electrode of source electrode and the 6th NMOS tube N6 and its connecting pin are the second clock end of N pipe feedback-type bootstrapping adiabatic circuits；N pipe
Feedback-type bootstrapping adiabatic circuits the first clock end and N pipe feedback-type bootstrapping adiabatic circuits second clock terminate into clock letter
Number amplitude is identical, but 90 degree of phase phase difference.
Embodiment two: as shown in Fig. 4 (a), Fig. 4 (b) and Fig. 4 (c), a kind of N pipe feedback-type bootstrapping adiabatic circuits, including the
One PMOS tube P1, the second PMOS tube P2, the first NMOS tube N1, the second NMOS tube N2, third NMOS tube N3, the 4th NMOS tube N4,
5th NMOS tube N5 and the 6th NMOS tube N6；The source electrode of first PMOS tube P1, the source electrode of the second PMOS tube P2, third NMOS tube N3
Drain electrode and the 4th NMOS tube N4 drain electrode connection and its connecting pin be N pipe feedback-type boot adiabatic circuits the first clock end,
The drain electrode of first PMOS tube P1, the grid of the second PMOS tube P2, the drain electrode of the first NMOS tube N1, third NMOS tube N3 source electrode and
The grid of 5th NMOS tube N5 connects and its connecting pin is the output end of N pipe feedback-type bootstrapping adiabatic circuits, the first PMOS tube P1
Grid, the drain electrode of the second PMOS tube P2, the drain electrode of the second NMOS tube N2, the 4th NMOS tube N4 source electrode and the 6th NMOS tube N6
Grid connection and its connecting pin be that N pipe feedback-type is booted the reversed-phase outputs of adiabatic circuits, the grid of the first NMOS tube N1 is N
The inverting input terminal of pipe feedback-type bootstrapping adiabatic circuits, the grid of the second NMOS tube N2 are N pipe feedback-type bootstrapping adiabatic circuits
Input terminal, the source grounding of the source electrode of the first NMOS tube N1 and the second NMOS tube N2；The grid and the 5th of third NMOS tube N3
The drain electrode of NMOS tube N5 connects, the drain electrode connection of the grid and the 6th NMOS tube N6 of the 4th NMOS tube N4, the 5th NMOS tube N5's
The connection of the source electrode of source electrode and the 6th NMOS tube N6 and its connecting pin are the second clock end of N pipe feedback-type bootstrapping adiabatic circuits；N pipe
Feedback-type bootstrapping adiabatic circuits the first clock end and N pipe feedback-type bootstrapping adiabatic circuits second clock terminate into clock letter
Number amplitude is identical, but 90 degree of phase phase difference.
In the present embodiment, the breadth length ratio of the first PMOS tube P1 and the second PMOS tube P2 are5th NMOS tube N5,
The width of six NMOS tube N6 it is long than forFirst NMOS tube N1, the second NMOS tube N2, third NMOS tube N3 and the 4th NMOS tube
The breadth length ratio of N4 is
By N pipe feedback-type bootstrapping adiabatic circuits of the invention in PTM32nm and existing insulation ECRL structural insulation circuit,
It is emulated respectively under PTM32nm standard technology.Under normal voltage (1v), existing insulation ECRL structural insulation circuit exists
Simulation waveform under PTM32nm standard technology is as shown in Figure 7；Under normal voltage (1v), of the invention uses clock transmission gate
Simulation waveform of the bootstrapping insulation electricity under PTM32nm standard technology is as shown in Figure 8.Analysis chart 7 and Fig. 8 are it is found that of the invention
Insulation electricity is booted with correct logic and apparent low power consumption characteristic using clock transmission gate.
The invention also discloses it is a kind of using above-mentioned N pipe feedback-type bootstrapping adiabatic circuits level Four inverters/buffers, with
Lower combination figure embodiment is described in further detail N pipe feedback-type bootstrapping adiabatic circuits of the invention.
Embodiment one: as shown in Fig. 4 (a), Fig. 4 (b), Fig. 4 (c), Fig. 5 and Fig. 6, a kind of level Four inverters/buffers, packet
Include four N pipe feedback-types bootstrapping adiabatic circuits, each N pipe feedback-type bootstrapping adiabatic circuits respectively include the first PMOS tube P1,
Second PMOS tube P2, the first NMOS tube N1, the second NMOS tube N2, third NMOS tube N3, the 4th NMOS tube N4, the 5th NMOS tube N5
With the 6th NMOS tube N6；The drain electrode and the 4th of the source electrode of first PMOS tube P1, the source electrode of the second PMOS tube P2, third NMOS tube N3
First clock end of the drain electrode connection and its connecting pin of NMOS tube N4 for N pipe feedback-type bootstrapping adiabatic circuits, the first PMOS tube P1
Drain electrode, the grid of the second PMOS tube P2, the drain electrode of the first NMOS tube N1, third NMOS tube N3 source electrode and the 5th NMOS tube N5
Grid connection and its connecting pin be N pipe feedback-type boot adiabatic circuits output end, the grid of the first PMOS tube P1, second
The drain electrode of PMOS tube P2, the drain electrode of the second NMOS tube N2, the grid connection of the source electrode of the 4th NMOS tube N4 and the 6th NMOS tube N6
And its connecting pin is that N pipe feedback-type is booted the reversed-phase outputs of adiabatic circuits, the grid of the first NMOS tube N1 be N pipe feedback-type from
Lift the inverting input terminal of adiabatic circuits, the grid of the second NMOS tube N2 is that N pipe feedback-type is booted the input terminals of adiabatic circuits, first
The source grounding of the source electrode of NMOS tube N1 and the second NMOS tube N2；The leakage of the grid and the 5th NMOS tube N5 of third NMOS tube N3
Pole connection, the drain electrode connection of the grid and the 6th NMOS tube N6 of the 4th NMOS tube N4, the source electrode and the 6th of the 5th NMOS tube N5
The source electrode of NMOS tube N6 connects and its connecting pin is the second clock end of N pipe feedback-type bootstrapping adiabatic circuits；First N pipe feedback
The input terminal of type bootstrapping adiabatic circuits is the input terminal of level Four inverters/buffers, first N pipe feedback-type bootstrapping adiabatic circuits
Inverting input terminal be level Four inverters/buffers inverting input terminal, the output of first N pipe feedback-type bootstrapping adiabatic circuits
It holds and is connected with the input terminal of second N pipe feedback-type bootstrapping adiabatic circuits, the reverse phase of first N pipe feedback-type bootstrapping adiabatic circuits
The inverting input terminal connection of output end and second N pipe feedback-type bootstrapping adiabatic circuits, second N pipe feedback-type bootstrapping insulation electricity
The output end on road is connected with the input terminal of third N pipe feedback-type bootstrapping adiabatic circuits, second N pipe feedback-type bootstrapping insulation electricity
The reversed-phase output on road is connected with the inverting input terminal of third N pipe feedback-type bootstrapping adiabatic circuits, and third N pipe feedback-type is certainly
The output end of adiabatic circuits and the input terminal connection of the 4th N pipe feedback-type bootstrapping adiabatic circuits are lifted, third N pipe feedback-type is certainly
Lift the reversed-phase output of adiabatic circuits and the inverting input terminal connection of the 4th N pipe feedback-type bootstrapping adiabatic circuits, the 4th N pipe
The output end of feedback-type bootstrapping adiabatic circuits is the output end of level Four inverters/buffers, the 4th N pipe feedback-type bootstrapping insulation
The reversed-phase output of circuit is the reversed-phase output of level Four inverters/buffers, the 4th N pipe feedback-type bootstrapping adiabatic circuits
First clock end is connected with the second clock end of third N pipe feedback-type bootstrapping adiabatic circuits and its connecting pin is level Four reverse phase
The first clock end of device/buffer, the first clock end and the 4th N pipe feedback of first N pipe feedback-type bootstrapping adiabatic circuits
Type boot adiabatic circuits second clock end connection and its connecting pin be level Four inverters/buffers second clock end, first
First clock end at the second clock end of a N pipe feedback-type bootstrapping adiabatic circuits and second N pipe feedback-type bootstrapping adiabatic circuits
Connection and its connecting pin are the third clock end of level Four inverters/buffers, the of second N pipe feedback-type bootstrapping adiabatic circuits
First clock end of two clock ends and third N pipe feedback-type bootstrapping adiabatic circuits connect and its connecting pin for level Four phase inverter/
First clock end of the 4th clock end of buffer, level Four inverters/buffers accesses the first clock signal clk 1, level Four reverse phase
Device/buffer second clock is terminated into second clock signal CLK2, the third clock end access of level Four inverters/buffers the
4th clock end of three clock signal clks 3, level Four inverters/buffers accesses the 4th clock signal clk 4, the first clock signal
CLK1, second clock signal CLK2, third clock signal clk 3 are identical with the amplitude of the 4th clock signal clk 4, the first clock letter
90 degree of phase phase difference of number CLK1 and second clock signal CLK2, the phase of the first clock signal clk 1 and third clock signal clk 3
Phase difference 180 degree, 270 degree of phase phase difference of the first clock signal clk 1 and the 4th clock signal clk 4.
Embodiment two: as shown in Fig. 4 (a), Fig. 4 (b), Fig. 4 (c), Fig. 5 and Fig. 6, a kind of level Four inverters/buffers, packet
Include four N pipe feedback-types bootstrapping adiabatic circuits, each N pipe feedback-type bootstrapping adiabatic circuits respectively include the first PMOS tube P1,
Second PMOS tube P2, the first NMOS tube N1, the second NMOS tube N2, third NMOS tube N3, the 4th NMOS tube N4, the 5th NMOS tube N5
With the 6th NMOS tube N6；The drain electrode and the 4th of the source electrode of first PMOS tube P1, the source electrode of the second PMOS tube P2, third NMOS tube N3
First clock end of the drain electrode connection and its connecting pin of NMOS tube N4 for N pipe feedback-type bootstrapping adiabatic circuits, the first PMOS tube P1
Drain electrode, the grid of the second PMOS tube P2, the drain electrode of the first NMOS tube N1, third NMOS tube N3 source electrode and the 5th NMOS tube N5
Grid connection and its connecting pin be N pipe feedback-type boot adiabatic circuits output end, the grid of the first PMOS tube P1, second
The drain electrode of PMOS tube P2, the drain electrode of the second NMOS tube N2, the grid connection of the source electrode of the 4th NMOS tube N4 and the 6th NMOS tube N6
And its connecting pin is that N pipe feedback-type is booted the reversed-phase outputs of adiabatic circuits, the grid of the first NMOS tube N1 be N pipe feedback-type from
Lift the inverting input terminal of adiabatic circuits, the grid of the second NMOS tube N2 is that N pipe feedback-type is booted the input terminals of adiabatic circuits, first
The source grounding of the source electrode of NMOS tube N1 and the second NMOS tube N2；The leakage of the grid and the 5th NMOS tube N5 of third NMOS tube N3
Pole connection, the drain electrode connection of the grid and the 6th NMOS tube N6 of the 4th NMOS tube N4, the source electrode and the 6th of the 5th NMOS tube N5
The source electrode of NMOS tube N6 connects and its connecting pin is the second clock end of N pipe feedback-type bootstrapping adiabatic circuits；First N pipe feedback
The inverting input terminal of type bootstrapping adiabatic circuits is the inverting input terminal of level Four inverters/buffers, first N pipe feedback-type bootstrapping
The input terminal connection of the output end of adiabatic circuits and second N pipe feedback-type bootstrapping adiabatic circuits, first N pipe feedback-type bootstrapping
The inverting input terminal connection of the reversed-phase output of adiabatic circuits and second N pipe feedback-type bootstrapping adiabatic circuits, second N pipe are anti-
The output end of feedback type bootstrapping adiabatic circuits is connected with the input terminal of third N pipe feedback-type bootstrapping adiabatic circuits, and second N pipe is anti-
The reversed-phase output of feedback type bootstrapping adiabatic circuits is connected with the inverting input terminal of third N pipe feedback-type bootstrapping adiabatic circuits, the
The input terminal connection of the output end of three N pipe feedback-types bootstrapping adiabatic circuits and the 4th N pipe feedback-type bootstrapping adiabatic circuits, the
The anti-phase input of the reversed-phase output of three N pipe feedback-types bootstrapping adiabatic circuits and the 4th N pipe feedback-type bootstrapping adiabatic circuits
End connection, the output end of the 4th N pipe feedback-type bootstrapping adiabatic circuits are the output end of level Four inverters/buffers, the 4th N
The reversed-phase output of pipe feedback-type bootstrapping adiabatic circuits is the reversed-phase output of level Four inverters/buffers, the 4th N pipe feedback
First clock end of type bootstrapping adiabatic circuits is connected with the second clock end of third N pipe feedback-type bootstrapping adiabatic circuits and it connects
Connect the first clock end that end is level Four inverters/buffers, the first clock end of first N pipe feedback-type bootstrapping adiabatic circuits and
The second clock end connections of 4th N pipe feedback-type bootstrapping adiabatic circuits and its connecting pin are the of level Four inverters/buffers
Two clock ends, the second clock end of first N pipe feedback-type bootstrapping adiabatic circuits and second N pipe feedback-type are booted adiabatic circuits
The connection of the first clock end and its connecting pin be level Four inverters/buffers third clock end, the bootstrapping of second N pipe feedback-type
The second clock end of adiabatic circuits is connected with the first clock end of third N pipe feedback-type bootstrapping adiabatic circuits and its connecting pin is
First clock end of the 4th clock end of level Four inverters/buffers, level Four inverters/buffers accesses the first clock signal
CLK1, the second clock of level Four inverters/buffers are terminated into second clock signal CLK2, and the of level Four inverters/buffers
Three clock ends access third clock signal clk 3, and the 4th clock end of level Four inverters/buffers accesses the 4th clock signal
CLK4, the first clock signal clk 1, second clock signal CLK2, third clock signal clk 3 and the 4th clock signal clk 4 width
It is worth identical, 90 degree of the phase phase difference of the first clock signal clk 1 and second clock signal CLK2, the first clock signal clk 1 and
The phase phase difference 180 degree of three clock signal clks 3, the phase phase difference 270 of the first clock signal clk 1 and the 4th clock signal clk 4
Degree.
In the present embodiment, the breadth length ratio of the first PMOS tube P1 and the second PMOS tube P2 are5th NMOS tube N5,
The width of six NMOS tube N6 it is long than forFirst NMOS tube N1, the second NMOS tube N2, third NMOS tube N3 and the 4th NMOS tube
The breadth length ratio of N4 is
In order to verify the superiority of level Four inverters/buffers of the invention, by level Four inverters/buffers of the invention
It is compared with various performances of the existing level Four inverters/buffers under PTM32nm standard technology.Use circuit simulation work
Have HSPICE circuit input frequency be 100MHz, 200MHz, load be respectively 10fF, 20fF, 30fF, 40fF under conditions of
Comparative Simulation is carried out to two kinds of circuit structures, the corresponding standard mains voltage of PTM technology library is 1V.
Table 1 is in PTM32nm standard technology, and input frequency is 100MHz, is loaded as level Four reverse phase of the invention under 10fF
Device/buffer and existing level Four inverters/buffers are in 100ns-200ns compared with performance.
Table 1
As can be drawn from Table 1: level Four inverters/buffers of the invention and existing level Four inverters/buffers ratio
Compared with delay reduces 23%, and average total power consumption reduces 35%, and power-consumption design reduces 50%.
Table 2 is in PTM32nm standard technology, and input frequency is 100MHz, is loaded as level Four reverse phase of the invention under 20fF
Device/buffer and existing level Four inverters/buffers are in 100ns-200ns compared with performance.
Table 2
As can be drawn from Table 2: level Four inverters/buffers of the invention and existing level Four inverters/buffers ratio
Compared with delay reduces 25%, and average total power consumption reduces 39%, and power-consumption design reduces 54%.
Table 3 is in PTM32nm standard technology, and input frequency is 100MHz, is loaded as level Four reverse phase of the invention under 30fF
Device/buffer and existing level Four inverters/buffers are in 100ns-200ns compared with performance.
Table 3
As can be drawn from Table 3: level Four inverters/buffers of the invention and existing level Four inverters/buffers ratio
Compared with delay reduces 27%, and average total power consumption reduces 46%, and power-consumption design reduces 60%.
Table 4 is in PTM32nm standard technology, and input frequency is 100MHz, is loaded as level Four reverse phase of the invention under 40fF
Device/buffer and existing level Four inverters/buffers are in 100ns-200ns compared with performance.
Table 4
As can be drawn from Table 4: level Four inverters/buffers of the invention and existing level Four inverters/buffers ratio
Compared with delay reduces 27%, and average total power consumption reduces 53%, and power-consumption design reduces 66%.
Table 5 is in PTM32nm standard technology, and input frequency is 200MHz, is loaded as level Four reverse phase of the invention under 10fF
Device/buffer and existing level Four inverters/buffers are in 100ns-200ns compared with performance.
Table 5
As can be drawn from Table 5: level Four inverters/buffers of the invention and existing level Four inverters/buffers ratio
Compared with delay reduces 23%, average total power consumption reduces 38%, and power-consumption design reduces by 52 %.
Table 6 is in PTM32nm standard technology, and input frequency is 200MHz, is loaded as level Four reverse phase of the invention under 20fF
Device/buffer and existing level Four inverters/buffers are in 100ns-200ns compared with performance.
Table 6
As can be drawn from Table 6: level Four inverters/buffers of the invention and existing level Four inverters/buffers ratio
Compared with delay reduces 25%, and average total power consumption reduces 42%, and power-consumption design reduces 56%.
Table 7 is in PTM32nm standard technology, and input frequency is 200MHz, is loaded as level Four reverse phase of the invention under 30fF
Device/buffer and existing level Four inverters/buffers are in 100ns-200ns compared with performance.
Table 7
As can be drawn from Table 7: level Four inverters/buffers of the invention and existing level Four inverters/buffers ratio
Compared with delay reduces 27%, and average total power consumption reduces 49%, and power-consumption design reduces 63%.
Table 8 is in PTM32nm standard technology, and input frequency is 200MHz, is loaded as level Four reverse phase of the invention under 40fF
Device/buffer and existing level Four inverters/buffers are in 100ns-200ns compared with performance.
Table 8
As can be drawn from Table 8: level Four inverters/buffers of the invention and existing level Four inverters/buffers ratio
Compared with delay reduces 27%, and average total power consumption reduces 58%, and power-consumption design reduces 69%.
By above-mentioned comparison data as it can be seen that under the premise of not influencing circuit performance, level Four phase inverter/buffering of the invention
For device compared with existing level Four inverters/buffers, delay, power consumption and power-consumption design have also arrived optimization.
Claims (4)
- The adiabatic circuits 1. a kind of N pipe feedback-type is booted, it is characterised in that including the first PMOS tube, the second PMOS tube, the first NMOS Pipe, the second NMOS tube, third NMOS tube, the 4th NMOS tube, the 5th NMOS tube and the 6th NMOS tube；The source electrode of first PMOS tube, the source electrode of second PMOS tube, the drain electrode of the third NMOS tube and institute The drain electrode for the 4th NMOS tube stated connects and its connecting pin is the first clock end of the N pipe feedback-type bootstrapping adiabatic circuits, The drain electrode of first PMOS tube, the grid of second PMOS tube, the drain electrode of first NMOS tube, described The source electrode of three NMOS tubes is connected with the grid of the 5th NMOS tube and its connecting pin is the N pipe feedback-type bootstrapping insulation The output end of circuit, the grid of first PMOS tube, the drain electrode of second PMOS tube, second NMOS tube It drains, the source electrode of the 4th NMOS tube is connected with the grid of the 6th NMOS tube and its connecting pin is that the N is managed The reversed-phase output of feedback-type bootstrapping adiabatic circuits, the grid of first NMOS tube are that the N pipe feedback-type bootstrapping is exhausted The inverting input terminal of heater circuit, the grid of second NMOS tube are the input of the N pipe feedback-type bootstrapping adiabatic circuits End, the source grounding of the source electrode of first NMOS tube and second NMOS tube；The grid of the third NMOS tube Pole is connected with the drain electrode of the 5th NMOS tube, the grid of the 4th NMOS tube and the drain electrode of the 6th NMOS tube Connection, the source electrode of the 5th NMOS tube is connected with the source electrode of the 6th NMOS tube and its connecting pin is that the N is managed The second clock end of feedback-type bootstrapping adiabatic circuits；First clock end of the described N pipe feedback-type bootstrapping adiabatic circuits and described N pipe feedback-type bootstrapping adiabatic circuits second clock terminate into clock signal amplitude it is identical, but 90 degree of phase phase difference.
- The adiabatic circuits 2. a kind of N pipe feedback-type according to claim 1 is booted, it is characterised in that first PMOS tube Breadth length ratio with second PMOS tube isThe width length of 5th NMOS tube, the 6th NMOS tube compares ForFirst NMOS tube, second NMOS tube, the third NMOS tube and the 4th NMOS tube Breadth length ratio is
- 3. a kind of level Four inverters/buffers, it is characterised in that including four N pipe feedback-types bootstrapping adiabatic circuits, each institute State N pipe feedback-type bootstrapping adiabatic circuits respectively include the first PMOS tube, the second PMOS tube, the first NMOS tube, the second NMOS tube, Third NMOS tube, the 4th NMOS tube, the 5th NMOS tube and the 6th NMOS tube；The source electrode of first PMOS tube, described The drain electrode of the source electrode of two PMOS tube, the third NMOS tube is connected with the drain electrode of the 4th NMOS tube and its connecting pin is First clock end of the N pipe feedback-type bootstrapping adiabatic circuits, the drain electrode of first PMOS tube, the 2nd PMOS The grid of pipe, the drain electrode of first NMOS tube, the source electrode of the third NMOS tube and the 5th NMOS tube grid Pole connection and its connecting pin are that the N pipe feedback-type is booted the output ends of adiabatic circuits, the grid of first PMOS tube, The drain electrode of second PMOS tube, the drain electrode of second NMOS tube, the source electrode of the 4th NMOS tube and described The grid of 6th NMOS tube connects and its connecting pin is the reversed-phase output of the N pipe feedback-type bootstrapping adiabatic circuits, described The grid of the first NMOS tube be that the N pipe feedback-type is booted the inverting input terminals of adiabatic circuits, second NMOS tube Grid be that the N pipe feedback-type is booted the input terminals of adiabatic circuits, the source electrode of first NMOS tube and described the The source grounding of two NMOS tubes；The grid of the third NMOS tube is connected with the drain electrode of the 5th NMOS tube, described The grid of the 4th NMOS tube connected with the drain electrode of the 6th NMOS tube, the source electrode of the 5th NMOS tube and described The source electrode of 6th NMOS tube connects and its connecting pin is the second clock end of the N pipe feedback-type bootstrapping adiabatic circuits；The input terminal of the bootstrapping adiabatic circuits of N pipe feedback-type described in first is the input of the level Four inverters/buffers The inverting input terminal at end, the bootstrapping adiabatic circuits of N pipe feedback-type described in first is the anti-of the level Four inverters/buffers Phase input terminal, N pipe feedback-type described in first boot adiabatic circuits output end and second described in N pipe feedback-type bootstrapping The input terminal of adiabatic circuits connects, the reversed-phase output of the bootstrapping adiabatic circuits of N pipe feedback-type described in first and second institute The inverting input terminal connection for the N pipe feedback-type bootstrapping adiabatic circuits stated, the bootstrapping adiabatic circuits of N pipe feedback-type described in second The input terminal of the output end N pipe feedback-type bootstrapping adiabatic circuits described with third connects, and N pipe feedback-type described in second is certainly The reversed-phase output for lifting adiabatic circuits is connected with the inverting input terminal of N pipe feedback-type bootstrapping adiabatic circuits described in third, the N pipe feedback-type described in three boot adiabatic circuits output end and the 4th described in N pipe feedback-type bootstrapping adiabatic circuits Input terminal connection, N pipe feedback described in the reversed-phase output of the third N pipe feedback-type bootstrapping adiabatic circuits and the 4th The output end of the inverting input terminal connection of type bootstrapping adiabatic circuits, the bootstrapping adiabatic circuits of N pipe feedback-type described in the 4th is institute The output end for the level Four inverters/buffers stated, N pipe feedback-type described in the 4th bootstrapping adiabatic circuits reversed-phase output be The reversed-phase output of the level Four inverters/buffers, N pipe feedback-type described in the 4th boot adiabatic circuits first when The second clock end of N pipe feedback-type bootstrapping adiabatic circuits Zhong Duan described with third connects and its connecting pin is the level Four First clock end of inverters/buffers, the first clock end and the 4th of the bootstrapping adiabatic circuits of N pipe feedback-type described in first The second clock end connections of a N pipe feedback-type bootstrapping adiabatic circuits and its connecting pin are the level Four phase inverter/slow Rush the second clock end of device, N pipe feedback-type described in first boot adiabatic circuits second clock end and second described in N First clock end of pipe feedback-type bootstrapping adiabatic circuits connects and its connecting pin is the third of the level Four inverters/buffers Clock end, the second clock end of the bootstrapping adiabatic circuits of N pipe feedback-type described in second and a N pipe feedback-type of third are certainly It lifts the first clock end connection of adiabatic circuits and its connecting pin is the 4th clock end of the level Four inverters/buffers, institute First clock end of the level Four inverters/buffers stated accesses the first clock signal, and the of the level Four inverters/buffers Two clock ends access second clock signal, and the third clock end of the level Four inverters/buffers accesses third clock signal, 4th clock end of the level Four inverters/buffers accesses the 4th clock signal, first clock signal, described Second clock signal, the third clock signal first clock identical, described with the amplitude of the 4th clock signal 90 degree of phase phase difference of signal and the second clock signal, first clock signal and the third clock signal Phase phase difference 180 degree, 270 degree of phase phase difference of first clock signal and the 4th clock signal.
- 4. a kind of level Four inverters/buffers according to claim 3, it is characterised in that first PMOS tube and institute The breadth length ratio for the second PMOS tube stated is5th NMOS tube, the 6th NMOS tube width it is long than forThe width of first NMOS tube, second NMOS tube, the third NMOS tube and the 4th NMOS tube Growing ratio is
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