CN106208678B - A kind of charge pump and memory - Google Patents
A kind of charge pump and memory Download PDFInfo
- Publication number
- CN106208678B CN106208678B CN201610556219.9A CN201610556219A CN106208678B CN 106208678 B CN106208678 B CN 106208678B CN 201610556219 A CN201610556219 A CN 201610556219A CN 106208678 B CN106208678 B CN 106208678B
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- charge pump
- nmos tube
- capacitor
- clock signal
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Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
- H02M3/077—Charge pumps of the Schenkel-type with parallel connected charge pump stages
Abstract
The present invention provides a kind of charge pump and memory, charge pump includes at least two groups charge pump circuit, and charge pump circuit includes initial level circuit and the output-stage circuit that is connected with initial level circuit, and initial level circuit includes the first NMOS tube, source and grid end are connected with power supply respectively, and drain terminal is as output end；Output-stage circuit includes: one end of first capacitor device and one end of the second capacitor provides end with the first clock signal respectively or second clock signal provides end and is connected；Second NMOS tube, source are connected with the other end of the output end of front stage circuits and first capacitor device respectively, and grid end is connected with the other end of the second capacitor, and source is as input terminal, and drain terminal is as output end；Third NMOS tube, source are connected with the source of the second NMOS tube, and grid end is connected with the input terminal of output-stage circuit in another charge pump circuit, and drain terminal is connected with the other end of the second capacitor.The present invention effectively reduces voltage transmission loss, greatly improves the efficiency of charge pump.
Description
Technical field
The present invention relates to field of circuit technology, more particularly to a kind of charge pump and a kind of memory.
Background technique
Basic module of the charge pump as flash storage has been largely fixed the program/erase speed of Flash.
With the progress of integrated circuit fabrication process, to the pursuit of low-power consumption, the supply voltage of integrated circuit constantly declines, meanwhile,
In flash storage, the operation of the program/erase of storage unit there is still a need for higher voltage, this allow for integrated circuit not
Charge pump gradually shows its consequence in disconnected development process.
Charge pump is also referred to as switched capacitor voltage changer, is a kind of utilization so-called " fast " (flying) or " pumping "
Capacitor (rather than inductance or transformer) carrys out DC-DC (DC-DC) converter of energy storage.Charge pump can make input voltage increase or
It reduces, charge pump controls the transmission of charge on capacitor using internal switch arrays in some way, usually with clock signal
The charge and discharge of capacitor in charge pump are controlled, to make input voltage increase (or reduction) in some way, required for reaching
Output voltage.
The structure of conventional charge pump is as shown in Figure 1.In Fig. 1, charge pump includes that (i.e. charge pump passes 7 charge pump transfer tubes
Defeated pipe N1 ', charge pump transfer tube N2 ', charge pump transfer tube N3 ', charge pump transfer tube N4 ', charge pump transfer tube N5 ', charge
Pump transfer tube N6 ', charge pump transfer tube N7 ') and 6 capacitors (i.e. capacitor C1 ', capacitor C2 ', capacitor C3 ', capacitor C4 ', capacitor
C5 ', capacitor C6 ', capacitor C7 '), 7 charge pump transfer tubes are connected into diode, clk ' and clkb ' as non-overlapping clock letter
Number.
Each charge pump transfer tube can have the loss of threshold voltage in conventional charge pump, therefore, the effect of conventional charge pump
Rate is very low.
Summary of the invention
In view of the above problems, the embodiment of the present invention is designed to provide a kind of charge pump and a kind of memory, to solve
The very low problem of the efficiency of conventional charge pump.
To solve the above-mentioned problems, the embodiment of the invention discloses a kind of charge pump, the charge pump includes at least two groups
Charge pump circuit, the charge pump circuit are used to for supply voltage to be promoted to setting voltage value and export, the charge pump circuit
Including initial level circuit and the output-stage circuit being connected with the initial level circuit, wherein
The initial level circuit include the first NMOS tube, the source and grid end of first NMOS tube respectively with power supply phase
Even, output end of the drain terminal of first NMOS tube as the initial level circuit；
The output-stage circuit includes the second NMOS tube, third NMOS tube, first capacitor device and the second capacitor, wherein
One end of the first capacitor device and one end of second capacitor provided respectively with the first clock signal end or
Second clock signal provides end and is connected；First clock signal provides the first clock signal and the second clock that end provides
It is non-overlapping clock signal that signal, which provides the second clock signal that end provides,；
The source of second NMOS tube respectively with the output end of the front stage circuits of the output-stage circuit and described first
The other end of capacitor is connected, and the grid end of second NMOS tube is connected with the other end of second capacitor, and described second
Input terminal of the source of NMOS tube as the output-stage circuit, the drain terminal of second NMOS tube is as the output-stage circuit
Output end；
The source of the third NMOS tube is connected with the source of second NMOS tube, the grid end of the third NMOS tube with
The input terminal of output-stage circuit is connected in another charge pump circuit, the drain terminal of the third NMOS tube and second capacitor
The other end is connected.
Optionally, the charge pump circuit further includes M intergrade circuit, the initial level circuit, the M intergrade
Circuit, the output-stage circuit are sequentially connected in series, and M is the integer more than or equal to 0, and the intergrade circuit includes the 4th NMOS
Pipe, the 5th NMOS tube, third capacitor and the 4th capacitor, wherein
It is connected when the front stage circuits and/or late-class circuit of the intergrade circuit provide end with first clock signal
When, one end of one end of the third capacitor and the 4th capacitor provides end phase with the second clock signal respectively
Even, and when the front stage circuits of the intergrade circuit and/or late-class circuit are connected with second clock signal offer end,
One end of the third capacitor and one end of the 4th capacitor provide end with first clock signal respectively and are connected；
The source of 4th NMOS tube respectively with the output end of the front stage circuits of the intergrade circuit and the third
The other end of capacitor is connected, and the grid end of the 4th NMOS tube is connected with the other end of the 4th capacitor, and the described 4th
Input terminal of the source of NMOS tube as the intergrade circuit, the drain terminal of the 4th NMOS tube is as the intergrade circuit
Output end；
The source of 5th NMOS tube is connected with the source of the 4th NMOS tube, the grid end of the 5th NMOS tube with
The drain terminal of 4th NMOS tube is connected, and the drain terminal of the 5th NMOS tube is connected with the other end of the 4th capacitor.
Optionally, the quantity of the intergrade circuit is three.
Optionally, the first intergrade circuit in three intergrade circuits and third intergrade circuit respectively with it is described
First clock signal provides end and is connected, the second intergrade circuit in the output-stage circuit and three intergrade circuits point
End is not provided with the second clock signal to be connected.
Optionally, the first intergrade circuit in three intergrade circuits and third intergrade circuit respectively with it is described
Second clock signal provides end and is connected, the second intergrade circuit in the output-stage circuit and three intergrade circuits point
End is not provided with first clock signal to be connected.
Optionally, the quantity of the charge pump circuit is two groups.
Specifically, when one end of the first capacitor device of one group of charge pump circuit and institute in two groups of charge pump circuits
When stating one end of the second capacitor and providing end with first clock signal respectively and be connected, the described in another group of charge pump circuit
One end of one capacitor and one end of second capacitor provide end with first clock signal respectively and are connected；When described two
One end difference of one end of the first capacitor device of one group of charge pump circuit and second capacitor in group charge pump circuit
When providing end with the second clock signal and being connected, one end of first capacitor device described in another group of charge pump circuit and described the
One end of two capacitors provides end with the second clock signal respectively and is connected.
Specifically, the charge pump circuit is positive voltage charge pump circuit.
To solve the above-mentioned problems, the embodiment of the invention also discloses a kind of memories, including the electricity described at least one
Lotus pump.
The embodiment of the present invention includes following advantages: setting charge pump includes at least two groups charge pump circuit, charge pump circuit
Including initial level circuit and the output-stage circuit being connected with initial level circuit, wherein the first NMOS tube in initial level circuit, with
And the second NMOS tube in output-stage circuit and third NMOS tube are not connected into diode, but make as switching tube
There was only the voltage difference between the source and drain terminal of each NMOS tube with, such voltage transmission loss, the voltage difference very little, especially when
When the grid end voltage of NMOS tube is very high, which can be less than 10mv and therefore greatly improve the efficiency of charge pump.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of conventional charge pump；
Fig. 2 is a kind of structural schematic diagram of charge pump embodiment of the invention；
Fig. 3 is the schematic diagram of the first clock signal and second clock signal in a kind of charge pump embodiment of the invention；
Fig. 4 is the structural schematic diagram of another charge pump embodiment of the invention.
Specific embodiment
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing and specific real
Applying mode, the present invention is described in further detail.
Referring to Fig. 2, a kind of structural schematic diagram of charge pump embodiment of the invention is shown, which includes at least two
Group charge pump circuit 1, charge pump circuit 1 are used to for supply voltage VDD to be promoted to setting voltage value VOUT and export, charge pump electricity
Road 1 includes initial level circuit 10 and the output-stage circuit 20 that is connected with initial level circuit 10, wherein initial level circuit 10 includes the
The source and grid end of one NMOS tube N1, the first NMOS tube N1 is connected with power supply respectively, power supply output supply voltage VDD, and first
Output end of the drain terminal of NMOS tube N1 as initial level circuit 10；Output-stage circuit 20 includes the second NMOS tube N2, the 3rd NMOS
Pipe N3, first capacitor device C1 and the second capacitor C2, wherein one end of first capacitor device C1 and one end of the second capacitor C2 point
End is not provided with the first clock signal or second clock signal provides end and is connected；Referring to Fig. 3, the first clock signal provides end and provides
The first clock signal clk and second clock signal provide end provide second clock signal clkb be non-overlapping clock signal,
The amplitude of oscillation, the amplitude of oscillation of second clock signal clkb of first clock signal clk can be VDD；The source of second NMOS tube N2 is distinguished
It is connected with the other end of the output end of the front stage circuits of output-stage circuit 20 and first capacitor device C1, the grid end of the second NMOS tube N2
It is connected with the other end of the second capacitor C2, input terminal of the source of the second NMOS tube N2 as output-stage circuit 20, second
Output end of the drain terminal of NMOS tube N2 as output-stage circuit 20；The source of the source of third NMOS tube N3 and the second NMOS tube N2
It is connected, the grid end of third NMOS tube N3 is connected with the input terminal of output-stage circuit 20 in another charge pump circuit 1, third NMOS tube
The drain terminal of N3 is connected with the other end of the second capacitor C2.
In the embodiment of the present invention, the first NMOS tube N1 in initial level circuit 10 and second in output-stage circuit 20
NMOS tube N2 and third NMOS tube N3 are not connected into diode, but use as switching tube, such voltage transmission damage
Lose the voltage difference between the source and drain terminal of there was only each NMOS tube, the voltage difference very little, especially when the grid end voltage of NMOS tube
When very high, which can be less than 10mv and therefore greatly improve the efficiency of charge pump.
Optionally, in another embodiment of the present invention, charge pump circuit 1 can also include M intergrade circuit, just
Beginning grade circuit 10, M intergrade circuit, output-stage circuit 20 are sequentially connected in series, and M is the integer more than or equal to 0, intergrade circuit
It may include the 4th NMOS tube N4, the 5th NMOS tube N5, third capacitor C3 and the 4th capacitor C4, wherein when intergrade electricity
When the front stage circuits and/or late-class circuit on road are connected with the first clock signal offer end, one end and the 4th of third capacitor C3
One end of capacitor C4 respectively with second clock signal provide end be connected, and when intergrade circuit front stage circuits and/or after
When grade circuit and second clock signal offer end is connected, one end of one end of third capacitor C3 and the 4th capacitor C4 respectively with
First clock signal provides end and is connected；The source of 4th NMOS tube N4 respectively with the output end of the front stage circuits of intergrade circuit and
The other end of third capacitor C3 is connected, and the grid end of the 4th NMOS tube N4 is connected with the other end of the 4th capacitor C4, and the 4th
Input terminal of the source of NMOS tube N4 as intergrade circuit, output of the drain terminal of the 4th NMOS tube N4 as intergrade circuit
End；The source of 5th NMOS tube N5 is connected with the source of the 4th NMOS tube N4, the grid end and the 4th NMOS tube of the 5th NMOS tube N5
The drain terminal of N4 is connected, and the drain terminal of the 5th NMOS tube N5 is connected with the other end of the 4th capacitor C4.
In one embodiment of the invention, referring to Fig. 4, the quantity of intergrade circuit can be three.In Fig. 4, three
The first intergrade circuit 31 and third intergrade circuit 33 in intergrade circuit provide end with second clock signal respectively and are connected,
The second intergrade circuit 32 in output-stage circuit 20 and three intergrade circuits provides end with the first clock signal respectively and is connected.
In another embodiment of the present invention, among the first intergrade circuit 31 in three intergrade circuits and third
Grade circuit 33 can provide end with the first clock signal respectively and be connected, second in output-stage circuit 20 and three intergrade circuits
Intergrade circuit 32 can provide end with second clock signal respectively and be connected.
Optionally, referring to Fig. 2 and Fig. 4, the quantity of charge pump circuit 1 can be two groups.Wherein, when two groups of charge pump circuits
In 1 one end of the first capacitor device C1 of one group of charge pump circuit 1 and one end of the second capacitor C2 respectively with the first clock signal
When end being provided being connected, in another group of charge pump circuit 1 one end of first capacitor device C1 and one end of the second capacitor C2 respectively with
First clock signal provides end and is connected；When one end of the first capacitor device C1 of one group of charge pump circuit 1 in two groups of charge pump circuits 1
When being connected respectively with second clock signal offer end with one end of the second capacitor C2, the first electricity in another group of charge pump circuit 1
One end of container C1 and one end of the second capacitor C2 provide end with second clock signal respectively and are connected.
Specifically, charge pump circuit 1 can be positive voltage charge pump circuit.
The following are the working principles of the charge pump circuit 1 of top half in Fig. 4: when charge pump, a point voltage is almost
Equal to VDD-Vt, wherein Vt is the threshold voltage of the first NMOS tube N1.When second clock signal clkb is high, a point voltage
For VDD+ (VDD-Vt), b point voltage is also height, and due to carving at the beginning, b point voltage can be precharged to VDD-Vt, so this
When b point voltage be about VDD+ (VDD-Vt), the 4th NMOS tube N4 is connected in the first intergrade circuit 31, and charge is transferred to c from a point
Point, c point voltage is VDD+ (VDD-Vt), at this point, in the first intergrade circuit 31 at third capacitor C3 and the 4th capacitor C4
In charged state.When the first clock signal clk be it is high when, second clock signal clkb be it is low, c point voltage be 2*VDD+
(VDD-Vt), the 5th NMOS tube N5 is connected in c point voltage, and the grid end and source of the 4th NMOS tube N4 is shorted, to block the 4th
NMOS tube N4 conducting, charge can not be transferred to c point from a point, at this point, third capacitor C3 and the 4th in the first intergrade circuit 31
Capacitor C4 is in discharge condition.In above procedure, the first NMOS tube N1, the 4th NMOS tube N4 and the 5th NMOS tube N5 only conduct
Switching tube uses, voltage difference of such voltage transmission loss only between the source and drain terminal of each NMOS tube, the voltage difference very little,
To greatly improve charge transfer efficiency.Second intergrade circuit 32, third intergrade circuit 33 and output-stage circuit 20
Working principle it is similar, repeat no more below.Charge pump shown in Fig. 2 by constantly being charged and discharged to each capacitor,
Output voltage is finally made to reach setting voltage value VOUT.
It should be noted that for output-stage circuit 20, if the grid end of third NMOS tube N3 is with the second NMOS tube N2's
Drain terminal is connected, then the source voltage terminal of second NMOS tube N2 is about VOUT+Vds-2* when the first clock signal clk is low
VDD, and the grid end voltage of the second NMOS tube N2 is also about VOUT+Vds-2*VDD.At this point, if the grid of third NMOS tube N3
If end voltage is controlled by the drain terminal voltage of the second NMOS tube N2, it is likely that the drain terminal voltage for the second NMOS tube N2 occur is lower than
The case where grid end voltage of the source voltage terminal of second NMOS tube N2 and third NMOS tube N3, cause the second NMOS tube N2 that can not close
It is disconnected, then the charge that charge originally to the source of the second NMOS tube N2, will pass through the 4th of third intergrade circuit 33 the
NMOS tube N4 leaks into the drain terminal of the second NMOS tube N2, leads to the reduction of the charge efficiency of pump.
The embodiment of the present invention includes following advantages: setting charge pump includes at least two groups charge pump circuit, charge pump circuit
Including initial level circuit and the output-stage circuit being connected with initial level circuit, wherein the first NMOS tube in initial level circuit, with
And the second NMOS tube in output-stage circuit and third NMOS tube are not connected into diode, but make as switching tube
With；Or charge pump circuit includes initial level circuit, M intergrade circuit and output-stage circuit, wherein in initial level circuit
One NMOS tube, the 4th NMOS tube in the second NMOS tube and third NMOS tube and intergrade circuit in output-stage circuit and
5th NMOS tube is not connected into diode, but uses as switching tube, and such voltage transmission loss only has each NMOS
Voltage difference between the source and drain terminal of pipe, the voltage difference very little, especially when the grid end voltage of NMOS tube is very high, the voltage
Difference can be less than 10mv and therefore greatly improve the efficiency of charge pump.
In addition, the embodiment of the invention also discloses a kind of memory, including at least one above-mentioned charge pump.
The embodiment of the present invention includes following advantages: setting charge pump includes at least two groups charge pump circuit, charge pump circuit
Including initial level circuit and the output-stage circuit being connected with initial level circuit, wherein the first NMOS tube in initial level circuit, with
And the second NMOS tube in output-stage circuit and third NMOS tube are not connected into diode, but make as switching tube
With；Or charge pump circuit includes initial level circuit, M intergrade circuit and output-stage circuit, wherein in initial level circuit
One NMOS tube, the 4th NMOS tube in the second NMOS tube and third NMOS tube and intergrade circuit in output-stage circuit and
5th NMOS tube is not connected into diode, but uses as switching tube, and such voltage transmission loss only has each NMOS
Voltage difference between the source and drain terminal of pipe, the voltage difference very little, especially when the grid end voltage of NMOS tube is very high, the voltage
Difference can be less than 10mv and therefore greatly improve charge pump, the efficiency of memory.
Since memory includes charge pump, so memory embodiment is described relatively simple, related place is referring to charge
Pump the part explanation of embodiment.
All the embodiments in this specification are described in a progressive manner, the highlights of each of the examples are with
The difference of other embodiments, the same or similar parts between the embodiments can be referred to each other.
Although the preferred embodiment of the embodiment of the present invention has been described, once a person skilled in the art knows bases
This creative concept, then additional changes and modifications can be made to these embodiments.So the following claims are intended to be interpreted as
Including preferred embodiment and fall into all change and modification of range of embodiment of the invention.
Finally, it is to be noted that, herein, relational terms such as first and second and the like be used merely to by
One entity or operation are distinguished with another entity or operation, without necessarily requiring or implying these entities or operation
Between there are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant meaning
Covering non-exclusive inclusion, so that process, method, article or terminal device including a series of elements not only wrap
Those elements are included, but also including other elements that are not explicitly listed, or further includes for this process, method, article
Or the element that terminal device is intrinsic.In the absence of more restrictions, being wanted by what sentence "including a ..." limited
Element, it is not excluded that there is also other identical elements in process, method, article or the terminal device for including the element.
Above to a kind of charge pump provided by the present invention and a kind of memory, it is described in detail, it is used herein
A specific example illustrates the principle and implementation of the invention, and the above embodiments are only used to help understand
Method and its core concept of the invention；At the same time, for those skilled in the art is having according to the thought of the present invention
There will be changes in body embodiment and application range, in conclusion the content of the present specification should not be construed as to the present invention
Limitation.
Claims (8)
1. a kind of charge pump, which is characterized in that the charge pump includes at least two groups charge pump circuit, and the charge pump circuit is used
Voltage value and exported in supply voltage is promoted to setting, the charge pump circuit include initial level circuit and with the initial level
The connected output-stage circuit of circuit, wherein
The initial level circuit includes the first NMOS tube, and the source and grid end of first NMOS tube are connected with power supply respectively, institute
State output end of the drain terminal of the first NMOS tube as the initial level circuit；
The output-stage circuit includes the second NMOS tube, third NMOS tube, first capacitor device and the second capacitor, wherein
One end of the first capacitor device and one end of second capacitor provide end or second with the first clock signal respectively
Clock signal provides end and is connected；First clock signal provides the first clock signal and the second clock signal that end provides
There is provided the second clock signal that end provides is non-overlapping clock signal；
The source of second NMOS tube respectively with the output end of the front stage circuits of the output-stage circuit and the first capacitor
The other end of device is connected, and the grid end of second NMOS tube is connected with the other end of second capacitor, the 2nd NMOS
Input terminal of the source of pipe as the output-stage circuit, the drain terminal of second NMOS tube is as the defeated of the output-stage circuit
Outlet；
The source of the third NMOS tube is connected with the source of second NMOS tube, the grid end of the third NMOS tube with it is another
The input terminal of output-stage circuit is connected in charge pump circuit, and the drain terminal of the third NMOS tube is another with second capacitor
End is connected；
The charge pump circuit further includes M intergrade circuit, the initial level circuit, the M intergrade circuit, described defeated
Grade circuit is sequentially connected in series out, and M is the integer more than or equal to 0, and the intergrade circuit includes the 4th NMOS tube, the 5th NMOS
Pipe, third capacitor and the 4th capacitor, wherein
When the front stage circuits of the intergrade circuit and/or late-class circuit, which provide end with first clock signal, to be connected, institute
One end of one end and the 4th capacitor for stating third capacitor provides end with the second clock signal respectively and is connected, and
When the front stage circuits of the intergrade circuit and/or late-class circuit, which provide end with the second clock signal, to be connected, described the
One end of three capacitors and one end of the 4th capacitor provide end with first clock signal respectively and are connected；
The source of 4th NMOS tube respectively with the output end of the front stage circuits of the intergrade circuit and the third capacitor
The other end of device is connected, and the grid end of the 4th NMOS tube is connected with the other end of the 4th capacitor, the 4th NMOS
Input terminal of the source of pipe as the intergrade circuit, the drain terminal of the 4th NMOS tube is as the defeated of the intergrade circuit
Outlet；
The source of 5th NMOS tube is connected with the source of the 4th NMOS tube, the grid end of the 5th NMOS tube with it is described
The drain terminal of 4th NMOS tube is connected, and the drain terminal of the 5th NMOS tube is connected with the other end of the 4th capacitor.
2. charge pump according to claim 1, which is characterized in that the quantity of the intergrade circuit is three.
3. charge pump according to claim 2, which is characterized in that the first intergrade electricity in three intergrade circuits
Road and third intergrade circuit provide end with first clock signal respectively and are connected, the output-stage circuit and it is three described in
The second intergrade circuit in intercaste circuit provides end with the second clock signal respectively and is connected.
4. charge pump according to claim 2, which is characterized in that the first intergrade electricity in three intergrade circuits
Road and third intergrade circuit provide end with the second clock signal respectively and are connected, the output-stage circuit and it is three described in
The second intergrade circuit in intercaste circuit provides end with first clock signal respectively and is connected.
5. charge pump according to claim 1, which is characterized in that the quantity of the charge pump circuit is two groups.
6. charge pump according to claim 5, which is characterized in that
When one end of the first capacitor device of one group of charge pump circuit and second capacitor in two groups of charge pump circuits
When one end of device is connected with first clock signal offer end respectively, first capacitor device described in another group of charge pump circuit
One end and one end of second capacitor provide end with first clock signal respectively and are connected；
When one end of the first capacitor device of one group of charge pump circuit and second capacitor in two groups of charge pump circuits
When one end of device is connected with second clock signal offer end respectively, first capacitor device described in another group of charge pump circuit
One end and one end of second capacitor provide end with the second clock signal respectively and are connected.
7. charge pump according to claim 1, which is characterized in that the charge pump circuit is positive voltage charge pump circuit.
8. a kind of memory, which is characterized in that including charge pump described at least one according to claim 1 any one of -7.
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| CN201610556219.9A CN106208678B (en) | 2016-07-14 | 2016-07-14 | A kind of charge pump and memory |
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| CN201610556219.9A CN106208678B (en) | 2016-07-14 | 2016-07-14 | A kind of charge pump and memory |
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| US5982223A (en) * | 1997-06-20 | 1999-11-09 | Integrated Silicon Solution, Inc. | Charge pump system with improved programming current distribution |
| CN1825485A (en) * | 2005-02-24 | 2006-08-30 | 旺宏电子股份有限公司 | Multi-pattern multi-stage charge pump |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2864271B1 (en) * | 2003-12-19 | 2006-03-03 | Atmel Corp | HIGH EFFICIENCY, LOW COST LOAD PUMP CIRCUIT |
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| CN106208678A (en) | 2016-12-07 |
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Address after: 230601 Building 1, Pearl Plaza, Hefei Economic and Technological Development Zone, Anhui Province Patentee after: HEFEI GEYI INTEGRATED CIRCUIT Co.,Ltd. Patentee after: Zhaoyi Innovation Technology Group Co.,Ltd. Address before: 230601 Building 1, Pearl Plaza, Hefei Economic and Technological Development Zone, Anhui Province Patentee before: HEFEI GEYI INTEGRATED CIRCUIT Co.,Ltd. Patentee before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. |