CN204966057U

CN204966057U - Shift register unit and shift register

Info

Publication number: CN204966057U
Application number: CN201520780072.2U
Authority: CN
Inventors: 商广良
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2015-10-09
Filing date: 2015-10-09
Publication date: 2016-01-13
Anticipated expiration: 2025-10-09

Abstract

The utility model discloses a shift register unit and including the shift register of this shift register unit. This shift register unit includes: input module is configured as and transmits the pull -up node with the incoming signal who receives, output module is disposed the pull -up signal of pull -up node will when effective pull -up level a control signal terminal's a control signal exports the output, the coupling module, its first end is connected with the 2nd control signal terminal, its second end with pull -up nodal connection, this coupling module is disposed to be based on through the voltage coupling mode the 2nd control signal terminal's the 2nd control signal controls the pull -up signal of pull -up node. Voltage through further draw high the pull -up node when the output resets can improve the speed that the output resets.

Description

Shift register unit and shift register

Technical Field

The present invention relates to the field of displays, and more particularly to a shift register unit and a shift register including the same.

Background

Currently, in the circuit structure of the shift register unit, the output end of the shift register unit and the pull-up node are reset simultaneously by using a special output reset transistor and a node reset transistor. As shown in fig. 1, the gates of the output reset transistor T4 and the node reset transistor T2 of the shift register unit are connected to a reset input terminal, and the output terminal and the pull-up node are reset, respectively, under the control of a reset signal output from the reset input terminal. In order to reduce the reset time of the shift register unit, it is necessary to increase the area of the output reset transistor T4 so that the on voltage of the output reset transistor T4 is small. However, increasing the area of the reset transistor T4 is obviously not favorable for improving the resolution of the display device and narrowing the bezel of the display device.

A scheme of time-divisionally resetting the output terminal of the shift register unit and the pull-up node has been proposed. As shown in fig. 3, in comparison with fig. 1, the output reset transistor T4 is no longer included, the gate of the reset transistor T2 receives the reset signal, the pull-up node is at a high level when the clock signal CLK switches from a high level to a low level, the output transistor T3 remains on and resets the output terminal to the low level of the clock signal CLK. Although the output reset transistor T4 is omitted in fig. 3, the shift register unit shown in fig. 3 still cannot meet the product requirement with the further improvement of the display resolution and the further improvement of the narrow frame requirement.

Therefore, it is necessary to provide a shift register unit capable of reducing not only the area of the shift register unit but also the reset time of the output terminal of the shift register unit.

SUMMERY OF THE UTILITY MODEL

In order to solve the above technical problem, a shift register unit and a shift register including the same are proposed, which can reduce the reset time of the shift register unit without increasing the area of the shift register unit.

According to an aspect of the present invention, there is provided a shift register unit, including: an input module having a first terminal connected to the input terminal of the shift register unit for receiving an input signal therefrom and a second terminal connected to a pull-up node, the input module being configured to pass the received input signal to the pull-up node; an output module having a first terminal connected to the pull-up node, a second terminal connected to a first control signal terminal, and a third terminal connected to the output terminal of the shift register unit, the output module being configured to output a first control signal of the first control signal terminal to the output terminal when the pull-up signal at the pull-up node is at an active pull-up level; a coupling module having a first terminal connected to the second control signal terminal and a second terminal connected to the pull-up node, the coupling module being configured to control the pull-up signal at the pull-up node according to the second control signal of the second control signal terminal by voltage coupling.

According to the utility model discloses embodiment, the coupling module includes: a first terminal of the first capacitor is connected to the second control signal terminal, and a second terminal thereof is connected to the pull-up node.

According to the utility model discloses embodiment, the coupling module includes: a coupling transistor having a gate connected to the second control signal terminal and a first pole connected to the third control signal terminal; and a first capacitor having a first terminal connected to the second pole of the coupling transistor and a second terminal connected to the pull-up node.

According to another aspect of the present invention, there is provided a shift register, a plurality of cascaded shift register units as described above, wherein the input terminals of the 1 st and 2 nd stage shift register units receive an initial input signal, the input terminal of the 2j +1 st stage shift register unit is connected to the output terminal of the 2j-1 st stage shift register unit, the input terminal of the 2j +2 nd stage shift register unit is connected to the output terminal of the 2j stage shift register unit, wherein j is greater than or equal to 1; a first control signal end of the 4i +1 th stage shift register unit is connected with a first clock signal end, a second control signal end is connected with an output end of the 4i +2 th stage shift register unit, wherein i is more than or equal to 0; the first control signal end of the 4i +2 th stage shift register unit is connected with the second clock signal end, and the second control signal end is connected with the output end of the 4i +3 th stage shift register unit; the first control signal end of the 4i +3 th stage shift register unit is connected with the third clock signal end, and the second control signal end is connected with the output end of the 4i +4 th stage shift register unit; the first control signal end of the 4i +4 th stage shift register unit is connected with the fourth clock signal end, and the second control signal end is connected with the output end of the 4i +6 th stage shift register unit.

According to the embodiment of the present invention, the period of the first clock signal terminal, the second clock signal of the second clock signal terminal, the third clock signal of the third clock signal terminal, the fourth clock signal of the fourth clock signal terminal is the first period, and the second clock signal lags behind the first clock signal by 1/4 first period, the third clock signal lags behind the second clock signal by 1/4 first period, and the fourth clock signal lags behind the third clock signal by 1/4 first period.

According to the utility model discloses embodiment, the coupling module includes: a coupling transistor having a gate connected to the second control signal terminal and a first pole connected to the third control signal terminal; a first terminal of the first capacitor is connected to the second pole of the coupling transistor, and a second terminal of the first capacitor is connected to the pull-up node. The third control signal end of the 2j-1 stage shift register unit is connected with the first pulse signal end; and the third control signal end of the 2j stage shift register unit is connected with the second pulse signal end. The period of the first pulse signal at the first pulse signal terminal and the period of the second pulse signal at the second pulse signal terminal are a second period, the second pulse signal lags behind the first pulse signal by 1/2 the second period, the duty ratio of the first pulse signal and the second pulse signal is equal to or less than 1/2, and the second period is 1/2 of the first period.

According to the utility model discloses shift register unit and operating method and shift register thereof, through with output and pull-up node timesharing reset and further pull up the voltage of pull-up node when the output resets, not only can utilize output transistor to realize the resetting of shift register unit, can also improve the speed that output transistor resets to the output, thereby reduce the reset time of shift register unit, this is favorable to improving display device's resolution ratio and constriction display device's frame.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent by describing in more detail embodiments of the present invention with reference to the attached drawings. The accompanying drawings are included to provide a further understanding of the embodiments of the invention, and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the invention and not to limit the invention. In the drawings, like reference numbers generally represent like parts or steps.

Fig. 1 shows a schematic structure of a shift register unit in the prior art.

FIG. 2 shows a timing diagram of the shift register cell shown in FIG. 1;

FIG. 3 is a schematic diagram of another prior art shift register cell;

FIG. 4 shows a timing diagram of the shift register cell shown in FIG. 3;

fig. 5 shows a schematic block diagram of a shift register cell according to an embodiment of the present invention;

fig. 6A shows an example implementation of a coupling module of a shift register cell according to a first embodiment of the invention;

fig. 6B shows an example implementation of a coupling module 53 of a shift register cell according to a second embodiment of the present invention;

fig. 7A shows another schematic block diagram of a shift register cell according to an embodiment of the present invention;

fig. 7B shows another schematic block diagram of a shift register cell according to an embodiment of the present invention;

fig. 8 shows an example circuit implementation of a shift register cell according to a first embodiment of the present invention;

fig. 9 shows an operation timing chart of an example circuit of a shift register unit according to the first embodiment of the present invention;

fig. 10 shows another example circuit implementation of a shift register cell according to the first embodiment of the present invention;

fig. 11 shows yet another example circuit implementation of a shift register cell according to the first embodiment of the present invention;

fig. 12 shows a schematic block diagram of a shift register according to a first embodiment of the present invention;

fig. 13 shows an example circuit implementation of a shift register cell according to a second embodiment of the present invention;

fig. 14 shows an operation timing chart of an example circuit of a shift register unit according to a second embodiment of the present invention;

fig. 15 shows another example circuit implementation of a shift register cell according to a second embodiment of the present invention;

fig. 16 shows yet another example circuit implementation of a shift register cell according to a second embodiment of the present invention; and

fig. 17 shows a schematic block diagram of a shift register according to a second embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, exemplary embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It is obvious that the described exemplary embodiments are only some of the embodiments of the present invention, and not all of the embodiments of the present invention, and all other embodiments obtained by those skilled in the art without inventive efforts shall fall within the protective scope of the present invention.

Here, it is to be noted that, in the drawings, the same reference numerals are given to constituent parts having substantially the same or similar structures and functions, and repeated description thereof will be omitted.

As shown in fig. 1, a schematic diagram of a shift register unit in the prior art is shown. The shift register unit includes an input transistor T1, an output transistor T3, a node reset transistor T2, an output reset transistor T4, and a capacitor C.

The gate and the drain of the INPUT transistor T1 are connected to the INPUT terminal INPUT, the source of the INPUT transistor T1 is connected to the pull-up node PU, the gate of the output transistor T3 is connected to the pull-up transistor, the drain of the output transistor T3 is connected to the clock signal terminal, the source of the output transistor T3 is connected to the output terminal OUT, the gates of the output RESET transistor T4 and the node RESET transistor T2 are connected to the RESET terminal RESET, the sources of the output RESET transistor T4 and the node RESET transistor T2 are connected to the low power supply voltage terminal VSS, the drain of the output RESET transistor T4 is connected to the output terminal OUT, the drain of the node RESET transistor T2 is connected to the pull-up node PU, the first terminal of the capacitor C is connected to the pull-up node PU, and the other terminal of the capacitor C is connected to the.

Fig. 2 shows a timing diagram of the shift register cell shown in fig. 1. As shown in fig. 2, in the first phase 1, the INPUT terminal INPUT is at a high level, the INPUT transistor T1 is turned on to transmit the high level of the INPUT terminal INPUT to the pull-up node PU, and the pull-up node PU is at the first voltage V1, so that the output transistor T3 is turned on, and the output terminal OUT outputs a low level due to the clock signal of the clock signal terminal CLK being at a low level; in the second stage 2, the INPUT terminal INPUT is at a low level, the INPUT transistor T1 is turned off, the RESET terminal RESET is at a low level, the node RESET transistor T2 is turned off, the pull-up node PU continues to turn on the output transistor T3, the clock signal of the clock signal terminal CLK is at a high level, the output terminal OUT outputs a high level, and the pull-up node PU is raised from the first voltage V1 to the second voltage V2 due to the voltage coupling effect of the capacitor C; in the third stage 3, the RESET terminal RESET is at a high level, the node RESET transistor T2 and the output RESET transistor T4 are turned on, and the pull-up node PU and the output terminal OUT are respectively pulled down to a low voltage of the low power supply voltage terminal VSS.

In the operation of the shift register unit shown in fig. 1 and 2, the reset of the pull-up node PU and the reset of the output terminal OUT are implemented by the node reset transistor T2 and the output reset transistor T4, respectively, that is, the reset of the output terminal OUT is implemented by the output reset transistor T4 entirely, and in order to reduce the reset time of the output terminal OUT, the area of the output reset transistor T4 must be increased, which obviously is not favorable for the improvement of the resolution of the display device and the narrowing of the frame of the display device.

Fig. 3 shows a schematic diagram of another shift register unit in the prior art. The shift register unit includes an input transistor T1, an output transistor T3, a node reset transistor T2, and a capacitor C. The gate of the node reset transistor T2 is connected to the node reset terminal RST _ PU, and the connection modes of the input transistor T1, the output transistor T3, the node reset transistor T2 and the capacitor C are the same as those in fig. 1, and are not described again.

Fig. 4 shows a timing diagram of the shift register cell shown in fig. 3. As shown in fig. 4, the operations of the shift register unit in the first stage 1 and the second stage 2 are the same as those shown in fig. 2, and are not repeated herein; in the third stage 3, the clock signal terminal CLK is at a low level, the pull-up node PU keeps the output transistor T3 turned on, and the output terminal OUT is pulled down to the low level of the clock signal terminal CLK, where the pull-up node PU is at the first voltage V1; then, in the fourth phase 4, the node reset terminal RST _ PU is at a high level, the node reset transistor T2 is turned on, and the pull-up node PU is pulled down to a low voltage of the low power supply voltage terminal VSS.

In the operation of the shift register unit shown in fig. 3 and 4, the pull-up node PU is first kept from being reset and the output terminal OUT is simultaneously pulled down by the output transistor T3, and the pull-up node PU is controlled to be pulled down by the reset signal after the output terminal OUT is pulled down. Despite the high level at the pull-up node PU, the shift register unit described in fig. 3 still fails to meet the requirements for further improving the resolution of the display device (e.g., to UHD and above) and further narrowing the bezel of the display device.

Fig. 5 shows a schematic block diagram of a shift register cell according to an embodiment of the present invention.

The shift register unit according to the embodiment of the present invention as shown in fig. 5 includes: an input module 51, an output module 52, and a coupling module 53.

The INPUT module 51 has a first terminal connected to the INPUT terminal INPUT of the shift register unit for receiving an INPUT signal therefrom, a second terminal connected to the pull-up node PU, and is configured to pass the received INPUT signal to the pull-up node PU.

The output block 52 has a first terminal connected to the pull-up node PU, a second terminal connected to the first control signal terminal CON1, and a third terminal connected to the output terminal OUT of the shift register unit, and is configured to output the first control signal of the first control signal terminal CON1 to the output terminal OUT when the pull-up signal at the pull-up node PU is at an active pull-up level.

The coupling module 53 has a first terminal connected to the second control signal terminal CON2 and a second terminal connected to the pull-up node PU, and the coupling module 53 is configured to control the pull-up signal at the pull-up node PU according to the second control signal of the second control signal terminal CON2 by voltage coupling.

When the shift register is operated, for example, in a case where the output signal at the output terminal of the output module 52 is at a high level, the coupling module 53 raises the pull-up signal at the pull-up node from the first pull-up voltage to the second pull-up voltage through voltage coupling according to the second control signal of the second control signal terminal CON 2; and when the first control signal of the first control signal terminal CON1 transitions from a high level to a low level, the pull-up signal of the second pull-up voltage at the pull-up node causes the output module to pull down the output terminal to the low level of the first control signal.

According to the first embodiment of the present invention, the coupling module 53 is configured to utilize the second control signal of the second control signal terminal CON2 to perform voltage coupling to control the pull-up signal at the pull-up node PU. Specifically, when the second control signal of the second control signal terminal CON2 jumps from the first level to the second level, the coupling module 53 makes the voltage jump of the pull-up signal at the pull-up node PU by voltage coupling, i.e. jumps from the first coupling voltage to the second coupling voltage. For example, when the second control signal of the second control signal terminal CON2 transits from low level to high level, the coupling module 53 drives up the pull-up signal at the pull-up node PU from the voltage VA to the voltage VB through voltage coupling. Alternatively, when the second control signal of the second control signal terminal CON2 transitions from a high level to a low level, the coupling module 53 drops the pull-up signal at the pull-up node PU from the voltage VC to the voltage VD through voltage coupling.

The first control signal of the first control signal terminal CON1, the second control signal of the second control signal terminal CON2, and the output signal of the output terminal OUT are different from each other, the period of the first control signal is a first period, and the second control signal lags behind the output signal by 1/4 for the first period.

According to the embodiment of the present invention, under the condition that the output signal of the output unit OUT is at the high level, the coupling module according to the second control signal of the second control signal terminal CON2 is lifted from the first pull-up voltage to the second pull-up voltage by the pull-up signal at the pull-up node in the voltage coupling mode, and then when the first control signal of the first control signal terminal CON1 jumps from the high level to the low level, the pull-up node PU at the second pull-up voltage makes the output module will the output end is pulled down to the low level of the first control signal. When the pull-up signal at the pull-up node is at a first pull-up voltage and a second pull-up voltage, the output module outputs the first control signal to the output terminal.

Fig. 6A shows an example implementation of a coupling module 53 of a shift register cell according to a first embodiment of the present invention.

As shown in fig. 6A, the coupling module 53 includes a first capacitor C1, a first terminal of the first capacitor C1 is connected to the second control signal terminal CON2, and a second terminal is connected to the pull-up node PU.

According to the second embodiment of the present invention, the coupling module 53 further includes a third terminal, and the third terminal is connected with a third control signal terminal CON3, and the coupling module 53 is configured to: the pull-up signal at the pull-up node PU is controlled by voltage coupling using the third control signal of the third control signal terminal CON3 when the second control signal of the second control signal terminal CON2 is at an active control level. Specifically, when the second control signal of the second control signal terminal CON2 is at the active control level and when the third control signal of the third control signal terminal CON3 jumps from the first level to the second level, the coupling module 53 also jumps the voltage of the pull-up signal at the pull-up node PU by voltage coupling, i.e., jumps from the first coupling voltage to the second coupling voltage. For example, when the second control signal of the second control signal terminal CON2 is at an active control level and when the third control signal of the third control signal terminal CON3 transitions from a low level to a high level, the coupling module 53 raises the pull-up signal at the pull-up node PU from the voltage VA to the voltage VB through voltage coupling. Alternatively, when the second control signal of the second control signal terminal CON2 is at an active control level and when the third control signal of the third control signal terminal CON3 transitions from a high level to a low level, the coupling module 53 drops the pull-up signal at the pull-up node PU from the voltage VC to the voltage VD through voltage coupling.

The first control signal of the first control signal terminal CON1, the second control signal of the second control signal terminal CON2, the third control signal of the third control signal CON3, and the output signal of the output terminal OUT are different from each other. The period of the first control signal is 1/2 of the first period, the period of the third control signal is 8932 of the first period, the second control signal lags behind the output signal by 1/4 of the first period, the duty ratio of the third control signal is smaller than or equal to 1/2, and the third control signal is at an effective control level at the upper jump edge and the lower jump edge of the first control signal.

Fig. 6B shows an example implementation of a coupling module 53 of a shift register cell according to a second embodiment of the present invention.

As shown in fig. 6B, the coupling module 53 includes a coupling transistor Tc and a first capacitor C1.

The gate of the coupling transistor Tc is connected to the second control signal terminal CON2, and the first pole is connected to the third control signal terminal CON 3. A first terminal of the first capacitor C1 is connected to the second pole of the coupling transistor Tc, and a second terminal is connected to the pull-up node PU.

Alternatively, the gate of the coupling transistor Tc may be connected to the third control signal terminal CON3, and the first pole may be connected to the second control signal terminal CON 2.

Fig. 7A shows another schematic block diagram of a shift register cell according to an embodiment of the present invention.

The shift register unit according to the embodiment of the present invention shown in fig. 7A includes, in addition to the input module 51, the output module 52, and the coupling module 53 shown in fig. 5: the module 54 is reset.

The reset module 54 has a first terminal connected to the fourth control signal terminal CON4, a second terminal connected to the pull-up node PU, and a third terminal connected to the low power voltage terminal VSS, and is configured to pull down the pull-up signal at the pull-up node PU to the low power voltage of the low power voltage terminal VSS when the fourth control signal of the fourth control signal terminal CON4 is at an active control level. For example, the fourth control signal of the fourth control signal terminal CON4 lags behind the output signal of the output terminal by 3/4 first period.

Optionally, the reset unit 54 further includes a fourth terminal connected to the fifth control signal terminal CON5 and a fifth terminal connected to the output terminal OUT, and the reset unit 54 is further configured to pull down the output signal of the output terminal OUT to the low power voltage of the low power voltage terminal VSS when the fifth control signal of the fifth control signal terminal CON5 is at an active control level. For example, the fifth control signal of the fifth control signal terminal CON5 lags behind the output signal of the output terminal OUT by 1/2 first period.

Fig. 7B shows another schematic block diagram of a shift register cell according to an embodiment of the present invention.

The shift register unit according to the embodiment of the present invention shown in fig. 7B includes, in addition to the input module 51, the output module 52 and the coupling module 53 as shown in fig. 5, and the reset module 54 as shown in fig. 7A: a pull-down control module 55 and a pull-down module 56.

The pull-down control module 55 has a first terminal connected to the sixth control signal terminal CON6, a second terminal connected to the pull-up node PU, and a third terminal connected to the pull-down node PD, and is configured to: the pull-down signal at the pull-down node PD is generated at an inactive pull-down level when the pull-up signal at the pull-up node PU is at an active pull-up level, and the pull-down signal at an active pull-down level when the pull-up signal at the pull-up node PU is at an inactive pull-up level and the sixth control signal at the sixth control signal terminal CON6 is at an active control level. For example, the sixth control signal of the sixth control signal terminal CON6 lags behind the first control signal of the first control signal terminal CON1 by 3/4 for the first period.

The pull-down module 56 has a first terminal connected to the pull-down node PD, a second terminal connected to the output terminal OUT, a third terminal connected to the pull-up node PU, and a fourth terminal connected to the low supply voltage terminal VSS, and is configured to pull down the output terminal OUT and the pull-up node PU to the low supply voltage of the low supply voltage terminal VSS when a pull-down signal at the pull-down node PD is at an active pull-down level.

Optionally, the pull-down module 56 further includes a fifth terminal connected to the seventh control signal terminal CON7, and the pull-down module 56 is further configured to pull down the output terminal OUT to the low power voltage of the low power voltage terminal when the seventh control signal of the seventh control signal terminal CON7 is at an active control level. For example, the seventh control signal of the seventh control signal terminal CON7 lags behind the first control signal of the first control signal terminal CON1 by 1/2 for the first period.

Next, the operation of the shift register unit according to the first embodiment of the present invention will be described with reference to fig. 8 to 12.

Fig. 8 shows an example circuit implementation of a shift register cell according to a first embodiment of the present invention.

As shown in fig. 8, the shift register unit according to the first embodiment of the present invention includes an input module 51, an output module 52, a coupling module 53, a reset module 54, a pull-down control module 55, and a pull-down module 56.

The INPUT block 51 includes an INPUT transistor T1, a gate and a first pole of the INPUT transistor T1 connected to the INPUT, and a second pole of the INPUT transistor T1 connected to the pull-up node PU. When the INPUT signal at INPUT terminal INPUT is at an active INPUT level, INPUT transistor T1 passes the INPUT signal at INPUT terminal INPUT to pull-up node PU.

The output module 52 includes an output transistor T3 and a second capacitor C2, a gate of the output transistor T3 and a first terminal of the second capacitor C2 are connected to the pull-up node PU, a first pole of the output transistor T3 is connected to the first control signal terminal CON1, and a second pole of the output transistor T3 and a second terminal of the second capacitor C2 are connected to the output terminal OUT. When the pull-up signal at the pull-up node PU is at an active pull-up level, the output transistor T3 is turned on, outputting the first control signal of the first control signal terminal CON1 to the output terminal OUT.

The coupling module 53 includes a first capacitor C1, a first terminal of the first capacitor C1 is connected to the second control signal terminal CON2, and a second terminal of the first capacitor C1 is connected to the pull-up node PU. For example, when the second control signal of the second control signal terminal CON2 jumps from a low level to a high level, the first capacitor C1 drives up the pull-up signal at the pull-up node PU from the voltage VA to the voltage VB through voltage coupling; the second capacitor C2 drops the pull-up signal at the pull-up node PU from the voltage VC to the voltage VD by voltage coupling when the second control signal of the second control signal terminal CON2 transits from a high level to a low level.

The reset module 54 includes a node reset transistor T2, a gate of the node reset transistor T2 is connected to the fourth control signal terminal CON4, a first pole is connected to the pull-up node PU, and a second pole is connected to the low power voltage terminal VSS. When the fourth control signal at the fourth control signal terminal CON4 is at the active control level, the node reset transistor T2 is turned on, pulling down the pull-up signal at the pull-up node PU to the low power voltage of the low power voltage terminal VSS.

The pull-down control module 55 includes a first pull-down control transistor T9, a second pull-down control transistor T10, a third pull-down control transistor T7, and a fourth pull-down control transistor T8. A gate and a first pole of the first pull-down control transistor T9 are connected to a sixth control signal terminal CON6, and a second pole is connected to the pull-down control node PD _ CN; a gate of the second pull-down control transistor T10 is connected to the pull-up node PU, a first pole is connected to the pull-down control node PD _ CN, and a second pole is connected to the low power supply voltage terminal VSS; a gate of the third pull-down control transistor T7 is connected to the pull-down control node PD _ CN, a first pole is connected to the sixth control signal terminal CON6, and a second pole is connected to the pull-down node PD; the gate of the fourth pull-down control transistor T8 is connected to the pull-up node PU, the first pole is connected to the pull-down node PD, and the second pole is connected to the low power supply voltage terminal VSS.

The pull-down module 56 includes a node pull-down transistor T5 and an output pull-down transistor T6, gates of the node pull-down transistor T5 and the output pull-down transistor T6 are connected to a pull-down node PD, second poles of the node pull-down transistor T5 and the output pull-down transistor T6 are connected to a low power supply voltage terminal VSS, a first pole of the node pull-down transistor T5 is connected to a pull-up node PU, and a first pole of the output pull-down transistor T6 is connected to an output terminal OUT. When the first control signal of the fourth control signal terminal CON4 is at the active pull-down level, the node pull-down transistor T5 and the output pull-down transistor T6 are turned on to pull down the pull-up node PU and the output terminal OUT to the low power voltage of the low power voltage terminal VSS, respectively.

For example, the first control signal terminal CON1 is connected to the first clock signal terminal, the first control signal is a first clock signal, and a period of the first clock signal is a first period. The second control signal of the second control signal terminal CON2 lags behind the output signal of the output terminal OUT by 1/4 first period. The fourth control signal of the fourth control signal terminal CON4 lags behind the output signal of the output terminal by 3/4 first period. The sixth control signal of the sixth control signal terminal CON6 lags behind the first control signal of the first control signal terminal CON1 by 3/4 for the first period.

Fig. 9 shows an operation timing chart of an example circuit of a shift register unit according to the first embodiment of the present invention.

In the first phase I (INPUT phase), the INPUT terminal INPUT is at a high level, the INPUT transistor T1 is turned on to transfer the high level of the INPUT terminal INPUT to the pull-up node, and the pull-up node is at the first high voltage V1, so that the output transistor T3 is turned on, and the output terminal OUT outputs a low level due to the first control signal (i.e., the first clock signal) of the first control signal terminal CON1 (i.e., the first clock signal terminal CLK1) being at a low level. Further, in this stage, since the pull-up node PU is at a high level, the second pull-down control transistor T10 and the fourth pull-down control transistor T8 are turned on, so that the pull-down node PD is at a low level, and accordingly, both the node pull-down transistor T5 and the output pull-down transistor T6 are turned off. In addition, in this stage, the fourth control signal of the fourth control signal terminal CON4 is at a low level, and the node reset transistor T2 is turned off.

In the second phase II (the first output phase), the INPUT terminal INPUT is at a low level, the INPUT transistor T1 is turned off, the fourth control signal terminal CON4 is at a low level, the node reset transistor T2 is kept off, the pull-up node PU continues to turn on the output transistor T3, the first control signal of the first control signal terminal CON1 is at a high level, and the output terminal OUT outputs a high level, at which time the pull-up node PU is lifted from the first high voltage V1 to the second high voltage V2 due to the voltage coupling effect of the second capacitor C2. Further, in this stage, since the pull-up node PU is still at the high level, the second pull-down control transistor T10 and the fourth pull-down control transistor T8 remain turned on, the pull-down node PD is still at the low level, and accordingly, both the node pull-down transistor T5 and the output pull-down transistor T6 remain turned off.

In the third phase III (second output phase), the INPUT terminal INPUT is at a low level, the INPUT transistor T1 is kept turned off, the fourth control signal terminal CON4 is at a low level, the node reset transistor T2 is kept turned off, and the second control signal of the second control signal terminal CON2 is at a high level, and the pull-up node PU is lifted from the second high voltage V2 to the third high voltage V3 due to the voltage coupling effect of the first capacitor C1. Further, in this stage, since the pull-up node PU is still at the high level, the second pull-down control transistor T10 and the fourth pull-down control transistor T8 remain turned on, the pull-down node PD is still at the low level, and accordingly, both the node pull-down transistor T5 and the output pull-down transistor T6 remain turned off.

In the fourth phase IV (the first reset phase), the INPUT terminal INPUT is at a low level, the INPUT transistor T1 is kept off, the fourth control signal terminal is at a low level, the node reset transistor T2 is kept off, the second control signal of the second control signal terminal CON2 is still at a high level, the first control signal of the first control signal terminal CON1 jumps from a high level to a low level, the pull-up node PU is still at a high level, so that the output transistor T3 is kept on to pull down the output terminal OUT to the low level of the first control signal, and the pull-up node PU drops from the third high voltage V3 to the fourth high voltage V4 due to the voltage coupling effect of the second capacitor C2. Further, in this stage, since the pull-up node PU is still at the high level, the second pull-down control transistor T10 and the fourth pull-down control transistor T8 remain turned on, the pull-down node PD is still at the low level, and accordingly, both the node pull-down transistor T5 and the output pull-down transistor T6 remain turned off.

In the fifth phase V (the second reset phase), on the one hand, the second control signal of the second control signal terminal CON2 jumps from the high level to the low level, and the pull-up node PU drops from the fourth high voltage V4 (e.g., to the first high voltage V1) due to the voltage coupling effect of the first capacitor C1, and on the other hand, the fourth control signal of the fourth control signal terminal CON4 is at the high level, and the node reset transistor T2 is turned on, so as to pull down the pull-up node PU to the low voltage of the low power voltage terminal VSS. Further, in this stage, since the pull-up node PU is at a low level, the second pull-down control transistor T10 and the fourth pull-down control transistor T8 are both turned off, and since the sixth control signal of the sixth control signal terminal CON6 is at a high level, the first pull-down control transistor T9 and the third pull-down control transistor T7 are both turned on, so that the pull-down node PD transits from a low level to a high level, and accordingly, the node pull-down transistor T5 and the output pull-down transistor T6 are both turned on, pulling down the pull-up node PU and the output terminal OUT to a low power voltage of the low power voltage terminal VSS.

In the sixth stage VI, since the sixth control signal of the sixth control signal terminal CON6 is at a low level, the first pull-down control transistor T9 and the third pull-down control transistor T7 are both turned off, and since the pull-up node PU is at a low level, the second pull-down control transistor T10 and the fourth pull-down control transistor T8 are both kept off, the pull-down node PD is kept at a high level, and accordingly the node pull-down transistor T5 and the output pull-down transistor T6 are both turned on, so that the pull-up node PU and the output terminal OUT are pulled down to a low power voltage of the low power voltage terminal VSS.

Thereafter, during the display of one frame image, the fifth phase V and the sixth phase VI are repeated until the display of the next frame image is started, i.e., the INPUT terminal INPUT INPUTs a valid INPUT signal again.

The voltage difference between the second high voltage V2 and the first high voltage V1 is Δ V1, the voltage difference between the third high voltage V3 and the second high voltage V2 is Δ V2, and the voltage difference between the fourth high voltage V4 and the third high voltage V3 is Δ V3. The first high voltage, the second high voltage, the third high voltage, and the fourth high voltage are determined by a voltage value of an INPUT signal of the INPUT terminal INPUT, a voltage value of a first control signal of the first control signal terminal CON1, a voltage value of a second control signal of the second control signal terminal CON2, the first capacitor C1, the second capacitor C2, and a circuit parasitic capacitance.

As shown in fig. 9, when the output terminal OUT starts to be pulled down, the pull-up signal at the pull-up node PU is at the third high voltage V3, which is higher than the second high voltage V2 as shown in fig. 2 and 4, V3. Therefore, according to the utility model discloses the shift register of first embodiment not only can utilize output transistor T3 to realize the reset or the drop-down of output OUT, can also reduce the reset time of output OUT through the pull-up signal of further lifting pull-up node PU department, is favorable to the improvement of display device resolution ratio and the constriction of display device frame.

Fig. 10 shows another example circuit implementation of a shift register cell according to the first embodiment of the present invention.

As shown in fig. 10, the reset module 54 further includes an output reset transistor T4, a gate of the output reset transistor T4 is connected to the fifth control signal terminal CON5, a first pole is connected to the output terminal OUT, and a second pole is connected to the low power voltage terminal VSS. For example, the fifth control signal of the fifth control signal terminal CON5 lags behind the output signal of the output terminal OUT by 1/2 first period.

In the fourth phase IV, the fifth control signal of the fifth control signal terminal CON5 is at a high level, the output reset transistor T4 is turned on, and the output terminal OUT is pulled down to the low power voltage of the low power voltage terminal VSS.

The driving capability of the output terminal OUT can be improved by adding the output reset transistor T4, and the output terminal OUT can be pulled down to the low power supply voltage of the low power supply voltage terminal VSS more quickly by the cooperation of the output transistor T3 and the output reset transistor T4.

Fig. 11 shows yet another example circuit implementation of a shift register cell according to the first embodiment of the present invention.

As shown in fig. 11, the pull-down module 56 further includes a clock pull-down transistor T11, wherein a gate of the clock pull-down transistor T11 is connected to the seventh control signal terminal CON7, a first pole is connected to the output terminal OUT, and a second pole is connected to the low power voltage terminal VSS. For example, the seventh control signal of the seventh control signal terminal CON7 lags behind the first clock signal by 1/2 first period.

In the fourth phase IV, the seventh control signal of the seventh control signal terminal CON7 is at a high level, the clock pull-down transistor T11 is turned on, and the output terminal OUT is pulled down to the low power voltage of the low power voltage terminal VSS.

The driving capability of the output terminal OUT can be improved by adding the clock pull-down transistor T11, and the output terminal OUT can be pulled down to the low power supply voltage of the low power supply voltage terminal VSS more quickly by the cooperation of the output transistor T3 and the clock pull-down transistor T11.

Fig. 12 shows a schematic block diagram of a shift register according to a first embodiment of the present invention.

As shown in fig. 12, the shift register according to the first embodiment of the present invention includes a plurality of cascaded shift register units, and each shift register unit may be as shown in fig. 8.

The shift register according to the first embodiment of the present invention is connected to the start input signal terminal STV, the first clock signal terminal CLK1, the second clock signal terminal CLK2, the third clock signal terminal CLK1B and the fourth clock signal terminal CLK 2B. The periods of the first clock signal terminal CLK1, the second clock signal of the second clock signal terminal CLK2, the third clock signal of the third clock signal terminal CLK1B, and the fourth clock signal of the fourth clock signal terminal CLK2B are first periods, and the second clock signal lags the first clock signal by 1/4 first periods, the third clock signal lags the second clock signal by 1/4 first periods, and the fourth clock signal lags the third clock signal by 1/4 first periods.

The INPUT ends INPUT of the 1 st and 2 nd stage shift register units are connected with an initial INPUT signal end STV to receive an initial INPUT signal, the INPUT ends of the 2j +1 st stage shift register units are connected with the output ends of the 2j-1 st stage shift register units, and the INPUT ends of the 2j +2 nd stage shift register units are connected with the output ends of the 2j stage shift register units, wherein j is more than or equal to 1.

The first control signal end of the 4i +1 th stage shift register unit is connected with the first clock signal end CLK1, the second control signal end is connected with the output end of the 4i +2 th stage shift register unit, the fourth control signal end is connected with the output end of the 4i +4 th stage shift register unit, and the sixth control signal end is connected with the fourth clock signal end CLK2B, wherein i is greater than or equal to 0.

The first control signal end of the 4i +2 th stage shift register unit is connected with the second clock signal end CLK2, the second control signal end is connected with the output end of the 4i +3 th stage shift register unit, the fourth control signal end is connected with the output end of the 4i +5 th stage shift register unit, and the sixth control signal end is connected with the first clock signal end CLK 1.

The first control signal end of the 4i +3 th stage shift register unit is connected with the third clock signal end CLK1B, the second control signal end is connected with the output end of the 4i +4 th stage shift register unit, the fourth control signal end is connected with the output end of the 4i +6 th stage shift register unit, and the sixth control signal end is connected with the second clock signal end CLK 2.

The first control signal end of the 4i +4 th stage shift register unit is connected with the fourth clock signal end CLK2B, the second control signal end is connected with the output end of the 4i +6 th stage shift register unit, the fourth control signal end is connected with the output end of the 4i +7 th stage shift register unit, and the sixth control signal end is connected with the third clock signal end CLK 1B.

In addition, in the case where each shift register unit is the shift register unit shown in fig. 10, the fifth control signal terminal of the 2j-1 st stage shift register unit is connected to the output terminal of the 2j +1 st stage shift register unit, and the fifth control signal terminal of the 2j stage shift register unit is connected to the output terminal of the 2j +2 nd stage shift register unit, where j is greater than or equal to 1.

In addition, in the case where each shift register unit is the shift register unit shown in fig. 11, the seventh control signal terminal of the 4i +1 th stage shift register unit is connected to the third clock signal terminal CLK1B, the seventh control signal terminal of the 4i +2 th stage shift register unit is connected to the fourth clock signal terminal CLK2B, the seventh control signal terminal of the 4i +3 th stage shift register unit is connected to the first clock signal terminal CLK1, and the seventh control signal terminal of the 4i +1 th stage shift register unit is connected to the second clock signal terminal CLK2, where i is greater than or equal to 0.

Referring back to fig. 9, an output signal GL1 of the first stage shift register unit, an output signal GL2 of the second stage shift register unit, an output signal GL3 of the third stage shift register unit, and an output signal GL4 of the fourth stage shift register unit are also shown.

Next, the operation of the shift register unit according to the second embodiment of the present invention will be described with reference to fig. 13 to 17.

Fig. 13 shows an example circuit implementation of a shift register cell according to a second embodiment of the present invention.

As shown in fig. 13, the shift register unit according to the first embodiment of the present invention includes an input module 51, an output module 52, a coupling module 53, a reset module 54, a pull-down control module 55, and a pull-down module 56.

The circuit structures of the input module 51, the output module 52, the reset module 54, the pull-down control module 55 and the pull-down module 56 in fig. 13 are the same as the circuit structures of the input module 51, the output module 52, the reset module 54, the pull-down control module 55 and the pull-down module 56 in fig. 8, and are not described herein again.

As shown in fig. 13, the coupling module 53 includes a coupling transistor Tc and a second capacitor C1.

According to the second embodiment of the present invention, in fig. 13, for example, the first control signal terminal CON1 is connected to the first clock signal terminal CLK1, the first control signal is a first clock signal, and the period of the first clock signal is a first period. The second control signal of the second control signal terminal CON2 lags behind the output signal of the output terminal OUT by 1/4 first period. The third control signal of the third control signal terminal CON3 is a pulse signal, the period of the pulse signal is the second period, the second period is 1/2 of the first period, the duty ratio of the pulse signal is 1/2 or less, and the third control signal is at an active control level at both the rising edge and the falling edge of the first control signal. The fourth control signal of the fourth control signal terminal CON4 lags behind the output signal of the output terminal by 3/4 first period. The sixth control signal of the sixth control signal terminal CON6 lags behind the first control signal of the first control signal terminal CON1 by 3/4 for the first period.

Fig. 14 shows an operation timing chart of an example circuit of a shift register unit according to a second embodiment of the present invention.

Two control signals of the third control signal terminal CON3 are shown in fig. 14, and only the control signals CON3/CK _ CP1 are utilized in the following description of the shift register unit shown in fig. 13, and the other control signal CON3/CK _ CP2 is used for the shift register unit of the previous or next stage of the shift register unit currently described.

In the first phase I (input phase), the second control signal of the second control signal terminal CON2 is at low level, and the coupling transistor Tc is turned off. The rest of the operations in the first stage I are the same as those in the first stage I shown in fig. 9, and are not described again here. In this first phase I, the pull-up node is at the first high voltage V1.

In the second phase II (the first output phase), the second control signal of the second control signal terminal CON2 is still at the low level, and the coupling transistor Tc is kept turned off. The remaining operations in the second stage II are the same as those in the first stage I shown in fig. 9, and are not described again here. In the second phase II, the output terminal OUT outputs a high level, and the pull-up node PU is lifted from the first high voltage V1 to the second high voltage V2 due to the voltage coupling effect of the second capacitor C2.

In the third stage III (the second output stage), the second control signal of the second control signal terminal CON2 is at a high level, the coupling transistor Tc is turned on, and the third control signal terminal CON3 is at a low level, at which time the voltage of the pull-up node PU is maintained at the second high voltage V2. The remaining operations in the third stage III are the same as those in the third stage III shown in fig. 9, and are not described again here.

In the fourth phase IV (the third output phase), the second control signal of the second control signal terminal CON2 is at a high level, the coupling transistor Tc is turned on, and the third control signal terminal CON3 transitions from a low level to a high level, at which time the voltage of the pull-up node PU is raised from the second high voltage V2 to the third high voltage V3. The remaining operations in the fourth stage IV are the same as those in the third stage III shown in fig. 9, and are not described again here.

In the fifth phase V (the first reset phase), the second control signal of the second control signal terminal CON2 is still at the high level, the coupling transistor Tc is kept turned on, the third control signal terminal CON3 is still at the high level, the first control signal of the first control signal terminal CON1 jumps from the high level to the low level, the pull-up node PU is still at the high level, so that the output transistor T3 is kept turned on to pull down the output terminal OUT to the low level of the first control signal, and the pull-up node PU drops from the third high voltage V3 to the fourth high voltage V4 due to the voltage coupling effect of the second capacitor C2. The remaining operations in the fifth stage V are the same as those in the fourth stage IV shown in fig. 9, and are not described again here. In the fifth phase V, the pull-up node PU is at the fourth high voltage V4, and the output transistor T3 is turned on to pull down the output terminal OUT to the low level of the first control signal. The fourth high voltage V4 is clearly higher than the first high voltage V1. Therefore, the pull-up node PU at the fourth high voltage V4 enables the output transistor T3 to reset the output terminal OUT faster than the pull-up signal at the pull-up node PU of the 3 rd stage shown in fig. 4, reducing the reset time of the output terminal OUT.

In the sixth phase VI (the second reset phase), the second control signal of the second control signal terminal CON2 keeps at the high level, the coupling transistor Tc keeps conducting, and the third control signal terminal CON3 makes a transition from the high level to the low level, so that the pull-up node PU drops from the fourth high voltage V4 to the fifth high voltage V5 due to the voltage coupling effect of the first capacitor C1. The remaining operations in the sixth stage VI are the same as those in the fourth stage IV shown in fig. 9, and are not described again here. In the sixth stage VI, the pull-up node PU is at the fifth high voltage V5, and the output transistor T3 is turned on to pull down the output terminal OUT to the low level of the first control signal.

In the seventh stage VII (the third reset stage), the second control signal of the second control signal terminal CON2 is at a low level, and the coupling transistor Tc is turned off. The remaining operations in the seventh stage VII are the same as those in the fifth stage V shown in fig. 9, and are not described again here. In the seventh stage VII, the pull-up node PU is at a low level and the pull-down node PD is at a high level.

In the eighth stage VIII, the second control signal of the second control signal terminal CON2 is at a low level, and the coupling transistor Tc is kept turned off. The remaining operations in the eighth stage VIII are the same as those in the sixth stage VI shown in fig. 9, and are not described again here. In the eighth stage VIII, the pull-up node PU is kept at the low level, and the pull-down node PD is kept at the high level.

Thereafter, during the display of one frame image, the seventh stage VII and the eighth stage viiih are repeated until the display of the next frame image is started, i.e., the INPUT terminal INPUT INPUTs a valid INPUT signal again.

The voltage difference between the second high voltage V2 and the first high voltage V1 is Δ V1, the voltage difference between the third high voltage V3 and the second high voltage V2 is Δ V2, the voltage difference between the third high voltage V3 and the fourth high voltage V4 is Δ V3, and the voltage difference between the fourth high voltage V4 and the fifth high voltage V5 is Δ V4. The first high voltage V1, the second high voltage V2, the third high voltage V3, the fourth high voltage V4, and the fifth high voltage V5 are determined by a voltage value of an INPUT signal at the INPUT terminal INPUT, a voltage value of a first control signal at the first control signal terminal CON1, a voltage value of a third control signal at the third control signal terminal CON3, the first capacitor C1, the second capacitor C2, and a circuit parasitic capacitance.

As shown in fig. 14, when the output terminal OUT starts to be pulled down, the pull-up signal at the pull-up node PU is at the third high voltage V3, which is higher than the second high voltage V2 as shown in fig. 2 and 4, V3. Therefore, according to the utility model discloses the shift register of second embodiment not only can utilize output transistor T3 to realize the reset or the drop-down of output OUT, can also reduce the reset time of output OUT through the pull-up signal of further lifting pull-up node PU department, is favorable to the improvement of display device resolution ratio and the constriction of display device frame.

Fig. 15 shows another example circuit implementation of a shift register cell according to a second embodiment of the present invention.

As shown in fig. 15, the reset module 54 further includes an output reset transistor T4. The output reset transistor T4 is connected in the same manner as shown in fig. 11, and will not be described again.

In the fifth and sixth stages V and VI, the fifth control signal of the fifth control signal terminal CON5 is at a high level, the output reset transistor T4 is turned on, and the output terminal OUT is pulled down to the low power voltage of the low power voltage terminal VSS.

Fig. 16 shows yet another example circuit implementation of a shift register cell according to a second embodiment of the present invention.

As shown in FIG. 16, the pull-down module 56 also includes a clock pull-down transistor T11. The clock pull-down transistor T11 is connected in the same manner as shown in fig. 11, and will not be described again.

In the fifth and sixth stages V and VI, the seventh control signal of the seventh control signal terminal CON7 is at a high level, the clock pull-down transistor T11 is turned on, and the output terminal OUT is pulled down to the low power voltage of the low power voltage terminal VSS.

As shown in fig. 17, a shift register according to the second embodiment of the present invention includes a plurality of cascaded shift register units, and each shift register unit may be as shown in fig. 13.

The shift register according to the first embodiment of the present invention is connected to the start input signal terminal STV, the first clock signal terminal CLK1, the second clock signal terminal CLK2, the third clock signal terminal CLK1B, the fourth clock signal terminal CLK2B, the first pulse signal terminal CK _ CP1, and the second pulse signal terminal CK _ CP 2. The periods of the first clock signal terminal CLK1, the second clock signal of the second clock signal terminal CLK2, the third clock signal of the third clock signal terminal CLK1B, and the fourth clock signal of the fourth clock signal terminal CLK2B are first periods, and the second clock signal lags the first clock signal by 1/4 first periods, the third clock signal lags the second clock signal by 1/4 first periods, and the fourth clock signal lags the third clock signal by 1/4 first periods. The period of the first pulse signal terminal CK _ CP1 and the period of the second pulse signal terminal CK _ CP2 are a second period, and the second pulse signal lags behind the first pulse signal by 1/2 for the second period, the duty ratio of the first pulse signal and the second pulse signal is equal to or less than 1/2, and the second period is 1/2 of the first period.

The first control signal end of the 4i +1 th stage shift register unit is connected with the first clock signal end CLK1, the second control signal end is connected with the output end of the 4i +2 th stage shift register unit, the third control signal end is connected with the first pulse signal end, the fourth control signal end is connected with the output end of the 4i +4 th stage shift register unit, the sixth control signal end is connected with the fourth clock signal end CLK2B, wherein i is greater than or equal to 0.

The first control signal end of the 4i +2 th stage shift register unit is connected with the second clock signal end CLK2, the second control signal end is connected with the output end of the 4i +3 th stage shift register unit, the third control signal end is connected with the second pulse signal end, the fourth control signal end is connected with the output end of the 4i +5 th stage shift register unit, and the sixth control signal end is connected with the first clock signal end CLK 1.

The first control signal end of the 4i +3 th stage shift register unit is connected with the third clock signal end CLK1B, the second control signal end is connected with the output end of the 4i +4 th stage shift register unit, the third control signal end is connected with the first pulse signal end, the fourth control signal end is connected with the output end of the 4i +6 th stage shift register unit, and the sixth control signal end is connected with the second clock signal end CLK 2.

The first control signal end of the 4i +4 th stage shift register unit is connected with the fourth clock signal end CLK2B, the second control signal end is connected with the output end of the 4i +6 th stage shift register unit, the third control signal end is connected with the second pulse signal end, the fourth control signal end is connected with the output end of the 4i +7 th stage shift register unit, and the sixth control signal end is connected with the third clock signal end CLK 1B.

In addition, in the case where each shift register unit is the shift register unit shown in fig. 15, the fifth control signal terminal of the 2j-1 st stage shift register unit is connected to the output terminal of the 2j +1 st stage shift register unit, and the fifth control signal terminal of the 2j stage shift register unit is connected to the output terminal of the 2j +2 nd stage shift register unit, where j is greater than or equal to 1.

In addition, in the case where each shift register unit is the shift register unit shown in fig. 16, the seventh control signal terminal of the 4i +1 th stage shift register unit is connected to the third clock signal terminal CLK1B, the seventh control signal terminal of the 4i +2 th stage shift register unit is connected to the fourth clock signal terminal CLK2B, the seventh control signal terminal of the 4i +3 th stage shift register unit is connected to the first clock signal terminal CLK1, and the seventh control signal terminal of the 4i +1 th stage shift register unit is connected to the second clock signal terminal CLK2, where i is greater than or equal to 0.

Alternatively, each of the transistors may be an N-type thin film transistor, the first electrode may be a drain, the second electrode may be a source, the active control level, the active pull-up level, and the active pull-down level are all high levels, and the inactive control level, the inactive pull-up level, and the inactive pull-down level are all low levels.

Alternatively, each of the transistors may be a P-type thin film transistor, the first electrode may be a source electrode, the second electrode may be a drain electrode, the active control level, the active pull-up level, and the active pull-down level may be low, and the inactive control level, the inactive pull-up level, and the inactive pull-down level may be high.

Alternatively, each of the transistors described above may be any combination of P-type and N-type thin film transistors.

Various embodiments of the present invention have been described in detail above. However, those skilled in the art should understand that they can make various modifications, combinations or sub-combinations of the embodiments without departing from the principle and spirit of the invention, and that such modifications are intended to fall within the scope of the invention.

Claims

1. A shift register cell comprising:

an input module having a first terminal connected to the input terminal of the shift register unit for receiving an input signal therefrom and a second terminal connected to a pull-up node, the input module being configured to pass the received input signal to the pull-up node;

an output module having a first terminal connected to the pull-up node, a second terminal connected to a first control signal terminal, and a third terminal connected to the output terminal of the shift register unit, the output module being configured to output a first control signal of the first control signal terminal to the output terminal when the pull-up signal at the pull-up node is at an active pull-up level;

a coupling module having a first terminal connected to the second control signal terminal and a second terminal connected to the pull-up node, the coupling module being configured to control the pull-up signal at the pull-up node according to the second control signal of the second control signal terminal by voltage coupling.

2. The shift register cell of claim 1, wherein the coupling module is configured to control a pull-up signal at the pull-up node using a second control signal of the second control signal terminal for voltage coupling,

wherein the coupling module transitions a pull-up signal at the pull-up node from a first coupling voltage to a second coupling voltage through voltage coupling when a second control signal at the second control signal terminal transitions from a first level to a second level,

wherein the period of the first control signal is a first period, and the second control signal lags 1/4 the output signal of the output terminal of the shift register unit by the first period.

3. The shift register cell of claim 2, wherein the coupling module comprises:

a first terminal of the first capacitor is connected to the second control signal terminal, and a second terminal thereof is connected to the pull-up node.

4. The shift register cell of claim 1, wherein a third terminal of the coupling module is connected to a third control signal terminal, and the coupling module is configured to: a pull-up signal at the pull-up node is controlled by voltage coupling using a third control signal of the third control signal terminal when a second control signal of the second control signal terminal is at an active control level,

wherein the coupling module transitions a pull-up signal at the pull-up node from a first coupling voltage to a second coupling voltage through voltage coupling when a second control signal at the second control signal terminal is at an active control level and when a third control signal at the third control signal terminal transitions from a first level to a second level,

wherein the period of the first control signal is a first period, and the second control signal lags 1/4 the output signal of the output terminal of the shift register unit by the first period; the period of the third control signal is 1/2 of the first period, the duty ratio of the third control signal is equal to or less than 1/2, and the third control signal is at an active control level at the upper and lower jumping edges of the first control signal.

5. The shift register cell of claim 4, wherein the coupling module comprises:

a coupling transistor having a gate connected to the second control signal terminal and a first pole connected to the third control signal terminal;

a first terminal of the first capacitor is connected to the second pole of the coupling transistor, and a second terminal of the first capacitor is connected to the pull-up node.

6. The shift register cell of one of claims 1-5, further comprising:

a reset module having a first terminal connected to the fourth control signal terminal, a second terminal connected to the pull-up node, and a third terminal connected to the low supply voltage terminal, and configured to pull down the pull-up signal at the pull-up node to the low supply voltage of the low supply voltage terminal when the fourth control signal at the fourth control signal terminal is at an active control level,

wherein a period of the first control signal is a first period,

the fourth control signal lags 3/4 the output signal at the output of the shift register cell by the first period.

7. The shift register cell of claim 6, wherein the reset block has a fourth terminal connected to a fifth control signal terminal, a fifth terminal connected to the output terminal, and is further configured to pull down the output signal of the output terminal to the low supply voltage of the low supply voltage terminal when a fifth control signal of the fifth control signal terminal is at an active control level,

wherein the fifth control signal lags 1/2 the output signal at the output of the shift register cell by a first period.

8. The shift register cell of claim 6, further comprising:

a pull-down control module having a first terminal connected to the sixth control signal terminal, a second terminal connected to the pull-up node, and a third terminal connected to the pull-down node, the pull-down control module being configured to: a pull-down signal generated at the pull-down node is at an inactive pull-down level when the pull-up signal at the pull-up node is at an active pull-up level, and a pull-down signal generated at the pull-down node is at an active pull-down level when the pull-up signal at the pull-up node is at an inactive pull-up level and when a sixth control signal at the sixth control signal terminal is at an active control level;

a pull-down module having a first terminal connected to a pull-down node, a second terminal connected to the output terminal, a third terminal connected to the pull-up node, and a fourth terminal connected to a low supply voltage terminal, the pull-down module configured to pull-down the output terminal and the pull-up node to a low supply voltage of the low supply voltage terminal when a pull-down signal at the pull-down node is at an active pull-down level,

wherein the sixth control signal lags 3/4 the first control signal by a first period.

9. The shift register cell of claim 8, wherein a fifth terminal of the pull-down module is connected with a seventh control signal terminal, and the pull-down module is further configured to pull down the output terminal to a low supply voltage of the low supply voltage terminal when a seventh control signal of the seventh control signal terminal is at an active control level,

wherein the seventh control signal lags 1/2 the first control signal by a first period.

10. The shift register cell of claim 1,

the input module comprises an input transistor, the grid electrode and the first electrode of the input transistor are connected with the input end, and the second electrode of the input transistor is connected with the pull-up node; and

the output module comprises an output transistor and a second capacitor, the grid electrode of the output transistor and the first end of the second capacitor are connected with the pull-up node, the first pole of the output transistor is connected with the first control signal end, and the second pole of the output transistor and the second end of the second capacitor are connected with the output end.

11. The shift register cell of claim 7,

the reset module includes a node reset transistor and an output reset transistor,

the grid electrode of the node reset transistor is connected with the fourth control signal end, the first pole of the node reset transistor is connected with the pull-up node, and the second pole of the node reset transistor is connected with the low power supply voltage end;

and the grid electrode of the output reset transistor is connected with the fifth control signal end, the first pole of the output reset transistor is connected with the output end, and the second pole of the output reset transistor is connected with the low power supply voltage end.

12. The shift register cell of claim 9, wherein the pull-down control module comprises a first pull-down control transistor, a second pull-down control transistor, a third pull-down control transistor, and a fourth pull-down control transistor; the pull-down module comprises a node pull-down transistor and an output pull-down transistor; wherein,

the grid and the first pole of the first pull-down control transistor are connected with the sixth control signal end, and the second pole of the first pull-down control transistor is connected with the pull-down control node;

the grid electrode of the second pull-down control transistor is connected with the pull-up node, the first pole of the second pull-down control transistor is connected with the pull-down control node, and the second pole of the second pull-down control transistor is connected with the low power supply voltage end;

the grid electrode of the third pull-down control transistor is connected with the pull-down control node, the first pole of the third pull-down control transistor is connected with the sixth control signal end, and the second pole of the third pull-down control transistor is connected with the pull-down node;

a grid electrode of the fourth pull-down control transistor is connected with the pull-up node, a first pole of the fourth pull-down control transistor is connected with the pull-down node, and a second pole of the fourth pull-down control transistor is connected with the low power supply voltage terminal VSS;

the grid electrodes of the node pull-down transistor and the output pull-down transistor are connected with a pull-down node, the second pole of the node pull-down transistor is connected with the low power voltage end, the first pole of the node pull-down transistor is connected with a pull-up node, and the first pole of the output pull-down transistor is connected with the output end.

13. A shift register comprising a plurality of cascaded shift register cells according to claim 1,

the input ends of the 1 st and 2 nd stage shift register units receive initial input signals, the input end of the 2j +1 st stage shift register unit is connected with the output end of the 2j-1 st stage shift register unit, the input end of the 2j +2 nd stage shift register unit is connected with the output end of the 2j stage shift register unit, wherein j is more than or equal to 1;

the first control signal end of the 4i +1 th stage shift register unit is connected with the first clock signal end, the second control signal end is connected with the output end of the 4i +2 th stage shift register unit, wherein, i is more than or equal to 0,

the first control signal end of the 4i +2 th stage shift register unit is connected with the second clock signal end, the second control signal end is connected with the output end of the 4i +3 th stage shift register unit,

the first control signal end of the 4i +3 th stage shift register unit is connected with the third clock signal end, the second control signal end is connected with the output end of the 4i +4 th stage shift register unit,

the first control signal end of the 4i +4 th stage shift register unit is connected with the fourth clock signal end, the second control signal end is connected with the output end of the 4i +6 th stage shift register unit,

the period of the first clock signal at the first clock signal terminal, the second clock signal at the second clock signal terminal, the third clock signal at the third clock signal terminal, and the fourth clock signal at the fourth clock signal terminal is the first period, and the second clock signal lags behind the first clock signal by 1/4 the first period, the third clock signal lags behind the second clock signal by 1/4 the first period, and the fourth clock signal lags behind the third clock signal by 1/4 the first period.

14. The shift register of claim 13, wherein the coupling module comprises: a first terminal of the first capacitor is connected to the second control signal terminal, and a second terminal thereof is connected to the pull-up node.

15. The shift register of claim 13, wherein the coupling module comprises: a coupling transistor having a gate connected to the second control signal terminal and a first pole connected to the third control signal terminal; a first capacitor having a first terminal connected to the second pole of the coupling transistor and a second terminal connected to the pull-up node,

the third control signal end of the 2j-1 stage shift register unit is connected with the first pulse signal end; the third control signal terminal of the 2j stage shift register unit is connected with the second pulse signal terminal,

the period of the first pulse signal at the first pulse signal end and the period of the second pulse signal at the second pulse signal end are a second period, the second pulse signal lags behind the first pulse signal by 1/2 the second period, the duty ratio of the first pulse signal and the duty ratio of the second pulse signal are the same and are less than or equal to 1/2, and the second period is 1/2 of the first period.

16. The shift register of claim 13, wherein each shift register cell further comprises: a reset module configured to pull down the pull-up signal at the pull-up node to a low supply voltage of a low supply voltage terminal when a fourth control signal of a fourth control signal terminal is at an active control level,

the fourth control signal end of the 4i +1 th stage shift register unit is connected with the output end of the 4i +4 th stage shift register unit; the fourth control signal end of the 4i +2 th stage shift register unit is connected with the output end of the 4i +5 th stage shift register unit; the fourth control signal end of the 4i +3 th stage shift register unit is connected with the output end of the 4i +6 th stage shift register unit; and the fourth control signal end of the 4i +4 th stage shift register unit is connected with the output end of the 4i +7 th stage shift register unit.

17. The shift register of claim 13, wherein each shift register cell further comprises:

a pull-down control module configured to: a pull-down signal generated at the pull-down node is at a non-active pull-down level when the pull-up signal at the pull-up node is at an active pull-up level, and a pull-down signal generated at the pull-down node is at an active pull-down level when the pull-up signal at the pull-up node is at a non-active pull-up level and when a sixth control signal at a sixth control signal terminal is at an active control level;

a pull-down module configured to pull down the output terminal and the pull-up node to a low supply voltage of a low supply voltage terminal when a pull-down signal at the pull-down node is at an active pull-down level

The sixth control signal end of the 4i +1 th stage shift register unit is connected with the fourth clock signal end; the sixth control signal end of the 4i +2 th stage shift register unit is connected with the first clock signal end; the sixth control signal end of the 4i +3 th stage shift register unit is connected with the second clock signal end; and the sixth control signal end of the 4i +4 th stage shift register unit is connected with the third clock signal end.