USRE46266E1 - Charge pump circuit - Google Patents
Charge pump circuit Download PDFInfo
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- USRE46266E1 USRE46266E1 US14/025,518 US201314025518A USRE46266E US RE46266 E1 USRE46266 E1 US RE46266E1 US 201314025518 A US201314025518 A US 201314025518A US RE46266 E USRE46266 E US RE46266E
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
Definitions
- the present invention generally relates to a charge pump circuit. More specifically, the present invention relates to a charge pump circuit that improves power efficiency.
- LSI large-scale integrated circuits
- semiconductor memory devices have required multiple internal power voltages such as 3V, 5V, and 10V.
- the LSI circuit requires a high voltage. Therefore, a charge pump circuit is used in order to boost a single external power voltage to generate a plurality of voltages.
- the charge pump circuits are mainly classified into a parallel type, a serial type, and a serial-parallel type.
- Japanese Unexamined Patent Application, First Publication, No. JP-A-2008-161014 discloses a serial-type charge pump circuit.
- a charge pump circuit may include, but is not limited to, a first plurality of capacitors, and a first precharge circuit.
- the first plurality of capacitors are connected in parallel to each other.
- the first plurality of capacitors receive clock signals to perform sequentially pumping operations which generate a first higher voltage from a power voltage supplied.
- the first precharge circuit precharges a first predetermined number of capacitors in the first plurality of capacitors at the power voltage. The first predetermined number is greater than one.
- FIG. 1A is a circuit diagram illustrating the configuration of a two-staged charge pump circuit in accordance with a first preferred embodiment of the present invention
- FIG. 1B is a circuit diagram illustrating the configuration of an n-staged charge pump circuit in accordance with a modified embodiment of the present invention
- FIG. 2 is a timing chart illustrating operations of the charge pump circuit of FIG. 1A ;
- FIG. 3A is a circuit diagram illustrating the precharge of switches of the charge pump circuit of FIG. 1A in a time period Tpre 1 ;
- FIG. 3B is a circuit diagram illustrating the precharge of switches of the charge pump circuit of FIG. 1A in a time period Tpre 2 ;
- FIG. 3C is a circuit diagram illustrating the discharge of the charge pump circuit of FIG. 1A in a time period Tdis;
- FIG. 4 is a circuit diagram illustrating the configuration of a charge pump circuit in accordance with a second preferred embodiment of the present invention.
- FIG. 5 is a timing chart illustrating operations of the charge pump circuit of FIG. 4 ;
- FIG. 6 is a circuit diagram illustrating the configuration of a charge pump circuit in accordance with the related art.
- the charge pump circuit shown in FIG. 6 is a parallel-type two-stage charge pump circuit that drives capacitors (capacitive elements C 1 and C 2 ) in parallel to generate a high voltage.
- a switch SWd 1 is turned into electrically conductive state (ON state) and switches SWc 1 and SWc 2 are turned into electrically non-conductive state (OFF) to precharge (charge) a capacitive element C 1 with the power voltage VDD.
- the switches SWd 1 and SWc 2 are both turned into electrically non-conductive state (OFF) and the switch SWc 1 is turned into electrically conductive state (ON state) to boost the voltage of the capacitive element C 1 using a clock signal and a buffer circuit 11 .
- a capacitive element C 2 is charged with the boosted voltage of the capacitive element C 1 to perform charge pumping from the capacitive element C 1 to the capacitive element C 2 .
- the switch SWc 1 is turned into electrically non-conductive state (OFF) and the switch SWc 2 is turned into electrically conductive state (ON state) to boost the voltage charged to the capacitive element C 2 by the buffer circuit 12 .
- a current is output from an output terminal OUT. In the case of a parallel-type charge pump circuit having two or more stages, this operation is repeatedly performed from an input stage to an output stage.
- the switch that pumps the voltage of the capacitive element C 1 to generate a high voltage has low current efficiency, the voltage output from the capacitive element C 1 through the switch SWc 1 , that is, the voltage charging the capacitive element C 2 , is low.
- a precharge path that precharges the capacitive element C 1 with the power voltage VDD is provided only for the capacitive element C 1 .
- the precharge path including the switch SWc 1 is a high voltage generation precharge path and has low current efficiency (there is a large voltage drop). It is difficult to precharge the capacitive element C 2 with high efficiency.
- a charge pump circuit may include, but is not limited to, a first plurality of capacitors, and a first precharge circuit.
- the first plurality of capacitors are connected in parallel to each other.
- the first plurality of capacitors receive clock signals to perform sequentially pumping operations which generate a first higher voltage from a power voltage supplied.
- the first precharge circuit precharges a first predetermined number of capacitors in the first plurality of capacitors at the power voltage. The first predetermined number is greater than one.
- a charge pump circuit may include, but is not limited to, a first charge pump circuit, a second charge pump circuit, and a third charge pump circuit.
- the first charge pump circuit may include, but is not limited to, a first plurality of capacitors that are connected in parallel to each other.
- the first plurality of capacitors receives clock signals to perform sequentially pumping operations which generate a first higher voltage from a power voltage supplied.
- the second charge pump circuit may include, but is not limited to, a second plurality of capacitors that are connected in parallel to each other.
- the second plurality of capacitors receive clock signals to perform sequentially pumping operations which generate a second higher voltage from the power voltage.
- the third charge pump circuit connects in series a first final stage capacitor on the final stage of the first plurality of capacitors to a second final stage capacitor on the final stage of the second plurality of capacitors.
- At least one of the first and second charge pump circuits may include, but is not limited to, a precharge circuit that precharges a predetermined number of capacitors at the power voltage.
- the predetermined number of capacitors are included in the at least one of the first and second charge pump circuits.
- the first predetermined number is greater than one.
- a charge pump circuit may include, but is not limited to, a first switch connected between a first power line and a first node, a first capacitor connected between the first node and a first clock supply node, a second switch connected between the first node and a second node, a third switch connected between the first power line and the second node, a second capacitor connected between the second node and a second clock supply node, and a fourth switch connected between the second node and a third node.
- the charge pump circuit includes the precharge path that precharges a predetermined one or more capacitors with the power voltage.
- the predetermined one or more capacitors are included in the capacitors of the charge pump circuit.
- the precharge path precharges, with the power voltage, the first capacitor on the first stage and the second capacitor on the second or later stage.
- the precharge path precharges the predetermined one or more capacitors from the power voltage without through any switch which is used for pumping the capacitors.
- This circuit configuration allows a highly efficient current supply to the predetermined one or more capacitors from the power supply.
- the capacitors have already been precharged by the precharge path before pumping operations.
- the precharged capacitors are thus pumped from a pumping-start voltage level which is higher than the normal pumping-start voltage level of the charge pump circuit of the related art.
- the precharged capacitors can be pumped at a higher efficiency.
- the highly efficient pumping can easily generate a larger output voltage.
- the precharge path can improve the charge pump circuit in the ability of current supply for precharging and pumping the capacitors.
- FIGS. 1A and 1B are diagrams illustrating the structure of charge pump circuits according to a first embodiment of the invention.
- a charge pump circuit 1 shown in FIG. 1A is an example of a parallel-type two-stage charge pump circuit
- a charge pump circuit 1 ′ shown in FIG. 1B is an example of a parallel-type n-stage charge pump circuit.
- the two-stage charge pump circuit 1 shown in FIG. 1A includes two voltage boosting capacitive elements C 1 and C 2 , which are a plurality of capacitive elements, buffer circuits 11 and 12 , and four switches SWc 1 , SWc 2 , SWd 1 , and SWd 2 .
- the switches SWc 1 , SWc 2 , SWd 1 , and SWd 2 are semiconductor switches (N-chMOS transistor switches) composed of N-chMOS (N channel MOS) transistors.
- the capacitive element C 1 and the capacitive element C 2 have the same capacitance.
- the capacitive element C 1 performs as a first capacitor on the first stage of the plural stages.
- the first capacitor C 1 is subjected to a first boosting.
- the first boosting is first one of the two boostings for all the capacitors C 1 and C 2 on all the stages, for example, the two stages.
- the first precharge path precharges the first capacitor C 1 on the first stage at the power voltage.
- the capacitive element C 2 performs as a second capacitor on the second stage that follows to the first stage on which the capacitor C 1 is provided.
- the second capacitor C 2 is subjected to a second boosting which is later than the first boosting for the capacitor C 1 .
- the second boosting is second one of the two boostings.
- the second precharge path precharges the second capacitor C 2 on the second stage at the power voltage.
- the first precharge path precharges the first capacitor C 1 on the first stage at the power voltage by the first boosting.
- the first boosting is first one of the three or more boostings for all the capacitors on all the stages, for example, the three or more stages.
- a second precharge path precharges a second capacitor on a follower stage at the power voltage.
- the follower stage is a second or later stage.
- the second capacitor is thus provided on the follower stage that is included in the other stages than the first stage.
- the later precharge paths sequentially precharge other capacitors than the first capacitors.
- the other capacitors than the first capacitors are provided on other stages that sequentially follow to the first capacitor.
- the charge pump circuit 1 further includes a clock generating unit 3 that generates clock signals CLK 1 and CLK 2 .
- the clock generating unit 3 receives a power voltage VDD and a ground voltage VSS and outputs the clock signals CLK 1 and CLK 2 having an “H” level (high level) equal to the voltage level of the power voltage VDD.
- the waveforms of the clocks CLK 1 and CLK 2 are shown in FIG. 2 .
- a node Na which is one end of the capacitive element C 1 , is connected to the power voltage VDD of an external power supply through the switch SWd 1 , and the other end of the capacitive element C 1 is connected to an output terminal of the buffer circuit 11 .
- the clock signal CLK 1 is input to an input terminal of the buffer circuit 11 .
- the node Na of the capacitive element C 1 is connected to one end (node Nb) of the capacitive element C 2 through the switch SWc 1 .
- the other end of the capacitive element C 2 is connected to an output terminal of the buffer circuit 12 .
- the clock signal CLK 2 is input to an input terminal of the buffer circuit 12 .
- the node Nb is connected to the power voltage VDD of the external power supply through the switch SWd 2 .
- the node Nb is connected to an output terminal OUT through the switch SWc 2 .
- the charge pump circuit 1 is a parallel-type two-stage charge pump circuit, and includes a precharge path that simultaneously charges the capacitive elements C 1 and C 2 with the power voltage VDD.
- the precharge path includes a first precharge path 41 including the switch SWd 1 that charges the capacitive element C 1 with the power voltage VDD and a second precharge path 42 including the switch SWd 2 that charges the capacitive element C 2 with the power voltage VDD.
- FIG. 2 is a timing chart illustrating the operation of the charge pump circuit shown in FIG. 1A .
- three operation periods that is, an initial precharge period Tpre 1 (from a time t 1 to a time t 2 ), the next precharge period Tpre 2 (from a time t 3 to a time t 4 ), and a discharge period Tdis (from a time t 5 to a time t 6 ) are repeated to perform a voltage boosting operation.
- the initial precharge period Tpre 1 a stage in which precharging is performed with the power voltage VDD is referred to as the initial precharge period Tpre 1
- a stage in which pumping is performed the rear-stage capacitive element is precharged with a boosted voltage output during pumping
- the next precharge period Tpre 2 a stage in which pumping is performed.
- the term ‘precharge’ includes ‘a case in which the capacitive element is charged with the power voltage VDD’ and ‘a case in which the capacitive element is charged with the boosted voltage output from the front-stage capacitive element during pumping’. Therefore, when it is necessary to clearly discriminate between the two cases, the former case is referred to as ‘precharge with the power voltage VDD’ and the latter case is referred to as ‘precharge by pumping’.
- the timing chart shown in FIG. 2 shows the waveform of the voltage of the node Na of the capacitive element C 1 and the waveform of the voltage of the node Nb of the capacitive element C 2 .
- FIG. 2 also shows the electrically conductive/non-conductive states (ON/OFF states) of the switch SWc 2 .
- a voltage (VDD+VPP) and the power voltage VDD shown on the right side of FIG. 2 indicate the voltage levels of the signals applied to the gate of the switch SWc 2 in order to turn the switch SWc 2 into electrically conductive/non-conductive states (ON/OFF states). That is, the voltage (VDD+VPP) is applied to the gate of the switch SWc 2 in order to turn on the switch SWc 2 , and the power voltage VDD is applied to the gate of the switch SWc 2 in order to turn the switch SWc 2 into electrically non-conductive state (OFF state).
- the switch SWc 2 is composed of an N-chMOS transistor that connects the node Nb of the capacitive element C 2 and the output terminal OUT.
- FIG. 2 shows the voltage levels used to turn the N-chMOS switches SWd 2 , SWc 1 and SWd 1 into electrically conductive/non-conductive states (ON/OFF states).
- VSS indicates the ground voltage.
- FIG. 2 shows the electrically conductive/non-conductive states (ON/OFF states) of the switch SWd 2 .
- FIG. 2 shows the electrically conductive/non-conductive states (ON/OFF states) of the switch SWc 1 .
- FIG. 2 shows the electrically conductive/non-conductive states (ON/OFF states) of the switch SWd 1 .
- FIG. 2 shows the waveform of the clock signal CLK 1 .
- FIG. 2 shows the voltage waveform of the clock signal CLK 2 .
- FIG. 3A shows the electrically conductive/non-conductive states (ON/OFF states) of the switches during the initial precharge period Tpre 1 defined from the time t 1 to the time t 2 .
- the switch SWd 1 is turned into electrically conductive state (ON state), and the node Na of the first-stage capacitive element C 1 is precharged with the power voltage VDD.
- the switch SWd 2 is turned into electrically conductive state (ON state) and the node Nb of the second-stage capacitive element C 2 is precharged with the power voltage VDD.
- These states are represented by the waveforms of the voltages of the nodes Na and Nb during the initial precharge period Tpre 1 defined from the time t 1 to the time t 2 in FIG. 2 , and the nodes Na and Nb are precharged with the power voltage VDD.
- the capacitive elements C 1 and C 2 used to boost the voltage are precharged with the power voltage VDD by the corresponding precharge paths (the switch SWd 1 and the switch SWd 2 ). In this way, the capacitive elements C 1 and C 2 are charged by the corresponding precharge paths. Therefore, it is possible to charge the capacitive elements C 1 and C 2 with the power voltage VDD.
- the charge pump circuit according to this embodiment it is possible to charge the second-stage capacitive element C 2 similar to the first-stage capacitive element C 1 with the power voltage VDD during the initial precharge period Tpre 1 , as compared to the charge pump circuit according to the related art shown in FIG. 6 . That is, in the charge pump circuit according to this embodiment, it is possible to charge the capacitive elements C 1 and C 2 while improving current supply efficiency.
- the charge pumping when charge pumping is performed from the first-stage capacitive element C 1 to the second-stage capacitive element C 2 , the charge pumping can start with the potential of the capacitive element C 2 higher than that in the charge pump circuit according to the related art shown in FIG. 6 . As a result, it is possible to improve pumping efficiency.
- the switch SWc 2 is turned into electrically non-conductive state (OFF state)
- the switch SWd 2 is turned into electrically non-conductive state (OFF state)
- the switch SWc 1 is turned into electrically conductive state (ON state)
- the switch SWd 1 is turned into electrically non-conductive state (OFF state).
- FIG. 3B shows the electrically conductive/non-conductive states (ON/OFF states) of the switches during the next precharge period Tpre 2 defined from the time t 3 to the time t 4 .
- the output of the buffer circuit 11 is at an “H” level, that is, the level of the power voltage VDD. Therefore, as shown in the waveform of the voltage of the node Na in FIG. 2 , at the time t 3 , the voltage of the node Na is increased to a voltage obtained by adding the charge voltage (the level of the power voltage VDD) of the capacitive element C 1 and the output voltage (the level of the power voltage VDD) of the buffer circuit 11 , that is, to a value close to a voltage that is two times the power voltage VDD.
- the switch SWc 1 is turned into electrically non-conductive state (OFF state) at the time t 4 , the node Na and the node Nb are disconnected from each other, and a voltage Vpre charged by the capacitive element C 1 remains at the node Nb of the capacitive element C 2 , wherein the voltage Vpre in the waveform of the voltage of the node Nb is shown in FIG. 2 .
- the precharge voltage Vpre of the capacitive element C 2 is higher than the power voltage VDD by a voltage level charged by the capacitive element C 1 . In this way, charge pumping from the capacitive element C 1 to the capacitive element C 2 is completed.
- Vpre VDD ⁇ (C2+2 ⁇ C1)/(C1+C2).
- the precharge voltage Vpre is higher than the power voltage VDD.
- the discharge period Tdis starts at the time t 5 .
- FIG. 3C shows the electrically conductive/non-conductive states (ON/OFF states) of the switches during the discharge period Tdis defined from the time t 5 to the time t 6 .
- the output of the buffer circuit 12 is at an “H” level, that is, the level of the power voltage VDD. Therefore, as shown in the waveform Nb of the voltage of the node Nb in FIG. 2 , the voltage of the node Nb is increased to the voltage VPP which is obtained by adding the charge voltage Vpre of the capacitive element C 2 and the output voltage (the level of the power voltage VDD) of the buffer circuit 12 at the time t 5 .
- the voltage VPP is output to the output terminal OUT through the switch SWc 2 .
- the switch SWd 1 is turned into electrically conductive state (ON state), and the node Na of the capacitive element C 1 is charged with the power voltage VDD.
- the switch SWc 2 is turned into electrically non-conductive state (OFF state) and the discharge period Tdis ends. Thereafter, the operation is repeatedly performed from the initial precharge period Tpre 1 .
- the charge pump circuit includes two precharge paths (the switch SWd 1 a and the switch SWd 2 ) that precharge the capacitive element C 1 and the capacitive element C 2 with the power voltage VDD during the initial precharge period Tpre 1 .
- the capacitive element C 2 when the precharge operation starts, the capacitive element C 2 is precharged with the power voltage VDD of the power supply by the precharge path including the switch SWd 2 . Since the precharge path directly precharges the capacitive element with the power voltage of the power supply, it has a high current efficiency. Then, charge pumping from the capacitive element C 1 to the capacitive element C 2 is performed by a high voltage generation precharge path including the switch SWc 1 .
- the capacitive element C 2 is precharged with the power voltage VDD by the precharge path with high current efficiency using the power supply VDD and the switch SWd 2 .
- charge pumping is performed by the capacitive element C 1 and the switch SWc 1 .
- the pumping operation can start with the voltage level of the power voltage VDD charged by the precharge operation as the potential of the capacitive element C 2 . Therefore, the current efficiency of pumping to the capacitive element C 2 is improved.
- the potential pumped to the capacitive element C 2 is higher than that in the related art. In this way, it is possible to improve the current supply capability of the capacitive element C 2 to the rear stage.
- the switch SWd 1 is turned into electrically conductive state (ON state). However, during the discharge period Tdis, the switch SWd 1 may be turned into electrically conductive state (ON state) to precharge the capacitive element C 1 with the power voltage VDD. Therefore, during the initial precharge period Tpre 1 , the switch SWd 1 may be turned into electrically non-conductive state (OFF state).
- the capacitive element C 1 and the capacitive element C 2 have the same capacitance, but the invention is not limited thereto.
- the capacitive element C 1 and the capacitive element C 2 may have different capacitances. Even when the capacitive element C 1 and the capacitive element C 2 have different capacitances, the charge pump circuit 1 may be operated in the same way as that when the capacitive elements have the same capacitance. In this case, the capacitive element C 2 is boosted by the capacitive element C 1 . Therefore, it is preferable that the capacitance of the capacitive element C 1 be more than that of the capacitive element C 2 .
- the parallel-type two-stage charge pump circuit 1 shown in FIG. 1A is given as an example, but the invention is not limited thereto.
- the n-stage (n ⁇ 2) charge pump circuit 1 ′ may be provided.
- the charge pump circuit 1 ′ shown in FIG. 1B differs from the two-stage charge pump circuit 1 shown in FIG. 1A in that it further includes capacitive elements C 3 , . . . , Cn, buffer circuits 13 , . . . , 1 n, and switches SWd 3 , . . . , SWdn and the clock generating unit 3 is replaced with a clock generating unit 3 A that generates clock signals CLK 1 , CLK 2 , CLK 3 , . . . , CLKn.
- a precharge path 14 including switch SWd 3 , . . . , SWdn may be omitted, and only the first-stage precharge path (switch SWd 1 ) and the second-stage precharge path (switch SWd 2 ) may be provided.
- a precharge path including an arbitrarily selected capacitive element may be provided in addition to the precharge paths including the first-stage capacitive element C 1 and the second-stage capacitive element C 2 .
- the charge pump circuit 1 ′ during each initial precharge period, the first-stage capacitive element C 1 and the second-stage capacitive element C 2 are precharged with the power voltage VDD. In this way, it is possible to obtain the same effects as those in the charge pump circuit 1 shown in FIG. 1A .
- the charge voltage of the capacitive elements C 3 , . . . , Cn is equal to or higher than the power voltage VDD. In this case, it is not necessary to use the precharge path.
- the power supply is turned into electrically conductive state (ON state) and the charge voltage levels of the capacitive elements C 3 , . . . , Cn are lower than the power voltage VDD, it is possible to perform a precharge operation with the power voltage VDD. In this way, it is possible to improve the rising characteristics of an output voltage when the power supply is turned into electrically conductive state (ON state).
- the charge pump circuit 1 or 1 ′ sequentially applies the clock signals CLK 1 , CLK 2 , CLK 3 , . . . , CLKn to a plurality of capacitive elements C 1 , C 2 , . . . , Cn that are connected in parallel to each other to perform a pumping operation, thereby generating a voltage higher than the supplied power voltage VDD.
- the charge pump circuit 1 or 1 ′ includes the precharge paths (the switches SWd 1 and SWd 2 ) that precharge a plurality of capacitive elements such as the capacitive elements C 1 and C 2 among the capacitive elements C 1 , C 2 , . . . , Cn with the power voltage VDD.
- the charge pump circuit 1 or 1 ′ during a precharge operation, it is possible to charge each of the capacitive elements C 1 and C 2 with the power voltage VDD. That is, in the charge pump circuit according to this embodiment, it is possible to precharge each capacitive element with the power voltage VDD without using the switch for pumping. Therefore, it is possible to perform a charge operation while improving the supply efficiency of current to the capacitive elements C 1 and C 2 .
- the pumping operation can start with a capacitive element with a higher potential than that in the charge pump circuit according to the related art. Therefore, it is possible to improve pumping efficiency.
- the charge pump circuit 1 ′ includes the first precharge path (switch SWd 1 ) that precharges the first-stage capacitive element C 1 among the capacitive elements with the power voltage VDD and the second precharge path (switch SWd 2 ) that charges any one of the other capacitive elements C 2 , C 3 , . . . , Cn with the power voltage VDD when the precharge operation starts.
- the charge pump circuits 1 and 1 ′ according to the first embodiment shown in FIGS. 1A and 1B are examples of the parallel-type charge pump circuit. However, in a second embodiment, an example of a serial-parallel-type charge pump circuit will be described.
- FIG. 4 is a diagram illustrating the structure of the charge pump circuit according to the second embodiment of the invention.
- a charge pump circuit 2 shown in FIG. 4 is a serial-parallel type and includes a plurality of parallel-type charge pump units 21 and 22 and a serial-type charge pump unit 23 that connects the output voltages of the charge pump units 21 and 22 in series to each other and outputs the voltage. That is, the serial-parallel-type charge pump circuit 2 according to the second embodiment is characterized in that the parallel-type charge pump units 21 and 22 are composed of the charge pump circuit 1 or 1 ′ according to the first embodiment. Therefore, in the serial-parallel-type charge pump circuit 2 , it is possible to obtain the same effects as those in the first embodiment.
- the parallel-type charge pump units 21 and 22 have the same structure as the charge pump circuit 1 shown in FIG. 1 . Therefore, in the parallel-type charge pump circuits 21 and 22 , a description of the same components as those in the charge pump circuit 1 shown in FIG. 1 will not be repeated.
- the serial-type charge pump unit 23 includes capacitive elements C 2 and C 2 ′, a buffer circuit 12 , a switch SWc 2 , which is an N-chMOS transistor, and a switch SWt′, which is a P-chMOS transistor.
- a switch SWt′ which is a P-chMOS transistor
- the switch SWt which is an N-chMOS transistor
- the capacitive element C 1 performs as a first capacitor on the first stage of the plural stages.
- the first capacitor C 1 is subjected to a first boosting.
- the first boosting is first one of the two boostings for all the capacitors C 1 and C 2 on all the stages, for example, the two stages.
- the first precharge path precharges the first capacitor C 1 on the first stage at the power voltage.
- the capacitive element C 2 performs as a second capacitor on the second stage that follows to the first stage on which the capacitor C 1 is provided.
- the second capacitor C 2 is subjected to a second boosting which is later than the first boosting for the capacitor C 1 .
- the second boosting is second one of the two boostings.
- the second precharge path precharges the second capacitor C 2 on the second stage at the power voltage.
- the capacitive element C 1 ′ performs as a third capacitor on the third stage of the plural stages.
- the third capacitor C 1 ′ is subjected to a first boosting.
- the first boosting is first one of the two boostings for all the capacitors C 1 ′ and C 2 ′ on all the stages, for example, the two stages.
- the third precharge path precharges the third capacitor C 1 ′ on the third stage at the power voltage.
- the capacitive element C 2 ′ performs as a fourth capacitor on the fourth stage that follows to the third stage on which the capacitor C 1 ′ is provided.
- the second capacitor C 2 ′ is subjected to a second boosting which is later than the first boosting for the capacitor C 1 ′.
- the second boosting is second one of the two boostings.
- the fourth precharge path precharges the second capacitor C 2 ′ on the second stage at the power voltage.
- the first precharge path precharges the first capacitor C 1 on the first stage at the power voltage by the first boosting.
- the first boosting is first one of the three or more boostings for all the capacitors on all the stages, for example, the three or more stages in the charge pump unit 21 .
- a second precharge path precharges a second capacitor on a follower stage at the power voltage in the charge pump unit 21 .
- the follower stage is a second or later stage in the charge pump unit 21 .
- the second capacitor is thus provided on the follower stage that is included in the other stages than the first stage in the charge pump unit 21 .
- the later precharge paths sequentially precharge other capacitors than the first capacitors in the charge pump unit 21 .
- the other capacitors than the first capacitors are provided on other stages that sequentially follow to the first capacitor in the charge pump unit 21 .
- the third precharge path precharges the third capacitor C 1 ′ on the third stage at the power voltage by the first boosting.
- the first boosting is first one of the three or more boostings for all the capacitors on all the stages, for example, the three or more stages in the charge pump unit 22 .
- a fourth precharge path precharges a fourth capacitor on a follower stage at the power voltage.
- the follower stage is a later stage than the third stage in the charge pump unit 22 .
- the fourth capacitor is thus provided on the follower stage that is included in the other stages than the first stage in the charge pump unit 22 .
- the later precharge paths sequentially precharge other capacitors than the third capacitors in the charge pump unit 22 .
- the other capacitors than the third capacitors are provided on other stages that sequentially follow to the third capacitor in the charge pump unit 22 .
- one terminal (node Nc) of the capacitive element C 2 ′ and one terminal (node Nb 1 ) of the capacitive element C 2 are connected to each other by the switch SWt′.
- the other terminal of the capacitive element C 2 ′ is connected to an output terminal of the buffer circuit 12 .
- the clock signal CLK 2 is input to the input terminal of the buffer circuit 12 .
- the other terminal (node Nb) of the capacitive element C 2 is connected to the output terminal OUT through the switch SWc 2 .
- FIG. 5 is a timing chart illustrating the operation of the charge pump circuit shown in FIG. 4 .
- three operation periods that is, an initial precharge period Tpre 1 defined from a time t 1 to a time t 2 , the next precharge period Tpre 2 defined from a time t 3 to a time t 4 , and a discharge period Tdis defined from a time t 5 to a time t 6 are repeated to perform a voltage boosting operation.
- the timing chart of FIG. 5 shows the waveforms of the voltage of a node Na of the capacitive element C 1 , the voltage of the node Nb of the capacitive element C 2 , the voltage of a node Na 1 of the capacitive element C 1 ′, and the voltage of a node Nc of the capacitive element C 2 ′.
- the levels of the voltage signals are shown in the right side of FIG. 5 .
- VDD indicates a power voltage
- VSS indicates a ground voltage.
- FIG. 5 shows the electrically conductive/non-conductive states (ON/OFF states) of the switch SWd 2 and the switch SWd 2 ′ during each operation period.
- a voltage 2VDD (2 ⁇ VDD) and the power voltage VDD shown on the right side of FIG. 5 indicate the voltage levels of the signals applied to the gates in order to turn the switches SWd 2 and SWd 2 ′ into electrically conductive/non-conductive states (ON/OFF states).
- the voltage levels of the signals applied to the gates are the same as those in the timing chart shown in FIG. 2 .
- FIG. 5 shows the voltage levels of the signals applied to the gates in order to turn the switches, which are N-chMOS transistors, into electrically conductive/non-conductive states (ON/OFF states).
- FIG. 5 shows the electrically conductive/non-conductive states (ON/OFF states) of the switch SWc 1 and the switch SWc 1 ′ during each operation period.
- FIG. 5 shows the electrically conductive/non-conductive states (ON/OFF states) of the switch SWc 2 .
- FIG. 5 also shows the electrically conductive/non-conductive states (ON/OFF states) of the switch SWd 1 and the switch SWd 1 ′.
- FIG. 5 also shows the electrically conductive/non-conductive states (ON/OFF states) of the switch SWt.
- the switch SWt′ is turned into electrically non-conductive state (OFF state) when the switch SWt is turned into electrically conductive state (ON state) and is turned into electrically conductive state (ON state) when the switch SWt is turned into electrically non-conductive state (OFF state).
- FIG. 5 shows the waveform of the clock signal CLK 2 .
- FIG. 5 shows the waveform of the clock signal CLK 1 .
- the clock signal CLK 2 shown in FIG. 5 is at an “H” level during the discharge period Tdis defined from the time t 5 to the time t 6 .
- the clock signal CLK 1 shown in FIG. 5 is at an “H” level during the next precharge period Tpre 2 defined from the time t 3 to the time t 4 .
- the switch SWd 2 , the switch SWd 2 ′, the switch SWd 1 , the switch SWd 1 ′, and the switch SWt are turned into electrically conductive state (ON state), and the switch SWc 1 , the switch SWc 1 ′, and the switch SWc 2 are turned into electrically non-conductive state (OFF state).
- the switch SWd 1 Since the switch SWd 1 is turned into electrically conductive state (ON state) during the initial precharge period Tpre 1 defined from the time t 1 to the time t 2 , the node Na of the capacitive element C 1 is precharged with the power voltage VDD. Since the switch SWd 2 and the switch SWt are also turned into electrically conductive state (ON state), the node Nb of the capacitive element C 2 is also precharged with the power voltage VDD. The node Nb takes the peak voltage which is given by 2Vpre+VDD at t 5 . For the time period Tdis from t 5 to t 6 , the node Nb keeps the voltage VPP. After t 6 , the node Nb drops to the voltage VDD.
- the switch SWd 1 ′ is turned into electrically conductive state (ON state) during the initial precharge period Tpre 1 defined from the time t 1 to the time t 2 , the node Na 1 of the capacitive element C 1 ′ is precharged with the power voltage VDD.
- the switch SWd 2 ′ is also turned into electrically conductive state (ON state)
- the node Nc of the capacitive element C 2 ′ is also precharged with the power voltage VDD.
- the node Nc takes the peak voltage which is given by Vpre+VDD at t 5 .
- the node Nc keeps the voltage (VPP+VDD)/2. After t 6 , the node Nc drops to the voltage VDD.
- This state is maintained during the initial precharge period Tpre 1 defined from the time t 1 to the time t 2 in FIG. 5 .
- the levels of the voltages of the node Na, the node Nb, the node Na 1 , and the node Nc are substantially equal to the level of the power voltage VDD.
- the switch SWd 2 , the switch SWd 2 ′, the switch SWc 2 , the switch SWd 1 , and the switch SWd 1 ′ are turned into electrically non-conductive state (OFF state).
- the switch SWc 1 , the switch SWc 1 ′, and the switch SWt are turned into electrically conductive state (ON state), and the switch SWt′ is turned into electrically non-conductive state (OFF state).
- the clock signal CLK 1 is at an “H” level.
- the clock signal CLK 1 is at an “H” level (high level), and the output of the buffer circuit 11 is at an “H” level, that is, the level of the power voltage VDD. Therefore, as shown in a waveform Na in FIG. 5 , the voltage of the node Na of the capacitive element C 1 is increased to a value close to a voltage (which is two times the power voltage VDD) obtained by adding the precharge voltage (the level of the power voltage VDD) of the capacitive element C 1 and the output voltage (the level of the power voltage VDD) of the buffer circuit 11 at the time t 3 .
- Vpre VDD ⁇ (C2+2 ⁇ C1)/(C1+C2).
- the precharge voltage Vpre is higher than the power voltage VDD.
- the clock signal CLK 1 is at an “H” level (high level), and the output of the buffer circuit 11 ′ is at an “H” level, that is, the level of the power voltage VDD. Therefore, as shown in the waveform Na 1 in FIG. 5 , the node Na 1 of the capacitive element C 1 ′ is increased to a value close to a voltage (which is two times the power voltage VDD) obtained by adding the charge voltage (the level of the power voltage VDD) of the capacitive element C 1 ′ and the output voltage (the level of the power voltage VDD) of the buffer circuit 11 ′ at the time t 3 .
- the switch SWc 1 is turned into electrically non-conductive state (OFF state) at the time t 4 , the node Na and the node Nb are disconnected from each other, and the voltage Vpre charged by the capacitive element C 1 remains at the node Nb of the capacitive element C 2 .
- the voltage Vpre of the capacitive element C 2 is higher than the power voltage VDD by a voltage level charged by the capacitive element C 1 . In this way, charge pumping from the capacitive element C 1 to the capacitive element C 2 is completed.
- the switch SWc 1 ′ is turned into electrically non-conductive state (OFF state) at the time t 4 , the node Na 1 and the node Nc are disconnected from each other, and the voltage Vpre charged by the capacitive element C 1 ′ remains at the node Nc of the capacitive element C 2 ′.
- the voltage Vpre of the capacitive element C 2 ′ is higher than the power voltage VDD by a voltage level charged by the capacitive element C 1 ′. In this way, charge pumping from the capacitive element C 1 ′ to the capacitive element C 2 ′ is completed.
- the discharge period Tdis starts at the time t 5 .
- the switch SWd 2 , the switch SWd 2 ′, the switch SWc 1 , the switch SWc 1 ′, and the switch SWt are turned into electrically non-conductive state (OFF state), and the switch SWc 2 , the switch SWd 1 , the switch SWd 1 ′, and the switch SWt′ are turned into electrically conductive state (ON state).
- the clock signal CLK 2 is at an “H” level.
- the clock signal CLK 2 is at an “H” level (high level), and the output of the buffer circuit 12 is at an “H” level, that is, the level of the power voltage VDD. Therefore, as shown in the waveform Nc in ( 1 ) of FIG. 5 , the node Nc of the capacitive element C 2 ′ is increased to a voltage (Vpre+VDD) obtained by adding the precharge voltage Vpre of the capacitive element C 2 ′ and the output voltage (the level of the power voltage VDD) of the buffer circuit 12 after the time t 5 .
- the voltage VPP is output to the output terminal OUT through the switch SWc 2 .
- the switch SWd 1 and the switch SWd 1 ′ are turned into electrically conductive state (ON state), and the node Na of the capacitive element C 1 and the node Na 1 of the capacitive element C 1 ′ are charged with the power voltage VDD.
- the discharge period Tdis ends. Thereafter, the initial precharge period Tpre 1 , the next precharge period Tpre 2 , and the discharge period Tdis are repeated.
- the charge pump circuit 2 includes four precharge paths (the switches SWd 1 , SWd 1 ′, SWd 2 , and SWd 2 ′) that precharge the capacitive element C 1 , the capacitive element C 1 ′, the capacitive element C 2 , and the capacitive element C 2 ′ with the power voltage VDD during the initial precharge period Tpre 1 .
- the capacitive elements C 2 and C 2 ′ are precharged with the power voltage VDD by the precharge paths including the switches SWd 2 and SWd 2 ′, respectively. Since the precharge paths directly charge the capacitive elements with the power voltage of the power supply, they have high current efficiency. Thereafter, charge pumping from the capacitive element C 1 to the capacitive element C 2 and charge pumping from the capacitive element C 1 ′ to the capacitive element C 2 ′ are performed by the high voltage generation precharge paths including the switches SWc 1 and SWc 1 ′ according to the related art.
- the capacitive elements C 2 and C 2 ′ are directly precharged with the power voltage VDD by the precharge paths including the switches SWd 2 and SWd 2 ′, precharge efficiency is improved. Therefore, it is possible to increase a precharge potential and improve current supply capability, as compared to the structure in which the precharge paths including the switches SWd 2 and SWd 2 ′ are not used.
- the charge pump circuit 2 includes: a first charge pump unit 21 that sequentially applies clock signals to a plurality of first capacitive elements C 1 and C 2 which are connected in parallel to each other to perform a pumping operation, thereby generating a voltage higher than the supplied power voltage VDD; and a second charge pump unit 22 that sequentially applies clock signals to a plurality of second capacitive elements C 1 ′ and C 2 ′ which are connected in parallel to each other to perform a pumping operation, thereby generating a voltage higher than the power voltage VDD.
- the charge pump circuit 2 further includes a third charge pump unit 23 that serially connects the rear-stage capacitive element C 2 of the plurality of first capacitive elements C 1 and C 2 and the rear-stage capacitive element C 2 ′ of the plurality of second capacitive elements C 1 ′ and C 2 ′ to generate a boosted output voltage.
- the first charge pump unit 21 includes precharge paths (the switches SWd 1 and SWd 2 ) that precharge a plurality of the capacitive elements C 1 and C 2 which are determined in advance among the respective capacitive elements C 1 and C 2 of the first charge pump unit 21 with the power voltage VDD
- the second charge pump unit 22 includes precharge paths (the switches SWd 1 ′, SWd 2 ′) that precharge a plurality of the capacitive elements C 1 and C 2 which are determined in advance among the respective capacitive elements C 1 ′ and C 2 ′ of the second charge pump unit 22 with the power voltage VDD.
- the parallel-type charge pump units 21 and 22 can precharge the capacitive elements C 2 and C 2 ′ with high efficiency, similar to the first embodiment.
- the third charge pump unit 23 can increase an output voltage and improve current supply capability.
- the charge pump circuit 2 shown in FIG. 4 that includes two parallel-type charge pump units 21 and 22 and one serial-type charge pump unit 23 is given as an example of the serial-parallel-type charge pump circuit, but the invention is not limited thereto.
- the charge pump circuit may include three or more parallel-type charge pump units and one serial-type charge pump unit that serially connects the output voltages of the plurality of parallel-type charge pump units and pumps the voltage.
- each of the parallel-type charge pump units 21 and 22 is not limited to the two-stage structure using two capacitive elements.
- n-stage charge pump units including n (n ⁇ 2) capacitive elements C 1 , C 2 , C 3 , . . . , Cn may be used.
- At least one-stage charge pump unit among the n-stage charge pump units may have the same structure as that in the first embodiment. In this case, it is possible to obtain the same effects as those in the first embodiment from the stage having the same structure as that in the first embodiment.
- the charge pump circuit shown in FIG. 1A, 1B , or 4 may be used for a circuit that generates a voltage which is higher than a power voltage supplied from the outside to, for example, a semiconductor memory device and is applied to the word line.
- the positive voltage is generated with the precharge voltage VDD.
- the above embodiments can be applied to other case where the negative voltage is generated with the precharge voltage VSS or the ground voltage.
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Abstract
Description
Vpre=VDD×(C2+2×C1)/(C1+C2).
Vpre=VDD×(C2+2×C1)/(C1+C2).
Claims (23)
Priority Applications (1)
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US14/025,518 USRE46266E1 (en) | 2008-11-13 | 2013-09-12 | Charge pump circuit |
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JP2008291068A JP2010119226A (en) | 2008-11-13 | 2008-11-13 | Charge pump circuit |
JP2008-291068 | 2008-11-13 | ||
US12/616,498 US8018270B2 (en) | 2008-11-13 | 2009-11-11 | Charge pump circuit |
US14/025,518 USRE46266E1 (en) | 2008-11-13 | 2013-09-12 | Charge pump circuit |
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US12/616,498 Reissue US8018270B2 (en) | 2008-11-13 | 2009-11-11 | Charge pump circuit |
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USRE46266E1 true USRE46266E1 (en) | 2017-01-03 |
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US12/616,498 Ceased US8018270B2 (en) | 2008-11-13 | 2009-11-11 | Charge pump circuit |
US14/025,518 Active 2029-12-24 USRE46266E1 (en) | 2008-11-13 | 2013-09-12 | Charge pump circuit |
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Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2010130781A (en) * | 2008-11-27 | 2010-06-10 | Elpida Memory Inc | Charge pump circuit and semiconductor memory equipped with it |
TWI442685B (en) | 2011-04-15 | 2014-06-21 | Univ Nat Chiao Tung | Charge pump device |
JP2013207455A (en) * | 2012-03-28 | 2013-10-07 | Elpida Memory Inc | Semiconductor device |
US9753559B2 (en) * | 2012-10-19 | 2017-09-05 | Texas Instruments Incorporated | Feedback integrator current source, transistor, and resistor coupled to input |
EP2973970A4 (en) * | 2013-03-15 | 2017-03-29 | Wispry, Inc. | Charge pump systems and methods |
US8619445B1 (en) | 2013-03-15 | 2013-12-31 | Arctic Sand Technologies, Inc. | Protection of switched capacitor power converter |
US8724353B1 (en) | 2013-03-15 | 2014-05-13 | Arctic Sand Technologies, Inc. | Efficient gate drivers for switched capacitor converters |
US10680512B2 (en) * | 2017-07-19 | 2020-06-09 | Infineon Technologies Austria Ag | Switched-capacitor converters with capacitor pre-charging |
US10224803B1 (en) | 2017-12-20 | 2019-03-05 | Infineon Technologies Austria Ag | Switched capacitor converter with compensation inductor |
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US5140182A (en) * | 1989-06-09 | 1992-08-18 | Texas Instruments Incorporated | Plural stage voltage booster circuit with efficient electric charge transfer between successive stages |
US5969988A (en) * | 1993-08-17 | 1999-10-19 | Kabushiki Kaisha Toshiba | Voltage multiplier circuit and nonvolatile semiconductor memory device having voltage multiplier |
US5978283A (en) * | 1998-07-02 | 1999-11-02 | Aplus Flash Technology, Inc. | Charge pump circuits |
US6137344A (en) * | 1997-10-01 | 2000-10-24 | Nec Corporation | High speed charge pump circuit having field effect transistors possessing an improved charge transfer efficiency |
US6459328B1 (en) * | 1999-11-11 | 2002-10-01 | Nec Corporation | High speed voltage boosting circuit |
US6972973B2 (en) * | 2003-01-09 | 2005-12-06 | Denso Corporation | Voltage booster having noise reducing structure |
JP2008161014A (en) | 2006-12-26 | 2008-07-10 | Elpida Memory Inc | Boosting charge-pump circuit |
US20080205134A1 (en) * | 2007-02-01 | 2008-08-28 | Kenta Kato | Charge pump to supply voltage bands |
-
2008
- 2008-11-13 JP JP2008291068A patent/JP2010119226A/en active Pending
-
2009
- 2009-11-11 US US12/616,498 patent/US8018270B2/en not_active Ceased
-
2013
- 2013-09-12 US US14/025,518 patent/USRE46266E1/en active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
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US5140182A (en) * | 1989-06-09 | 1992-08-18 | Texas Instruments Incorporated | Plural stage voltage booster circuit with efficient electric charge transfer between successive stages |
US5969988A (en) * | 1993-08-17 | 1999-10-19 | Kabushiki Kaisha Toshiba | Voltage multiplier circuit and nonvolatile semiconductor memory device having voltage multiplier |
US6137344A (en) * | 1997-10-01 | 2000-10-24 | Nec Corporation | High speed charge pump circuit having field effect transistors possessing an improved charge transfer efficiency |
US5978283A (en) * | 1998-07-02 | 1999-11-02 | Aplus Flash Technology, Inc. | Charge pump circuits |
US6459328B1 (en) * | 1999-11-11 | 2002-10-01 | Nec Corporation | High speed voltage boosting circuit |
US6972973B2 (en) * | 2003-01-09 | 2005-12-06 | Denso Corporation | Voltage booster having noise reducing structure |
JP2008161014A (en) | 2006-12-26 | 2008-07-10 | Elpida Memory Inc | Boosting charge-pump circuit |
US20080205134A1 (en) * | 2007-02-01 | 2008-08-28 | Kenta Kato | Charge pump to supply voltage bands |
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US8018270B2 (en) | 2011-09-13 |
US20100117719A1 (en) | 2010-05-13 |
JP2010119226A (en) | 2010-05-27 |
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