CN106206707A - 半导体装置 - Google Patents
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- CN106206707A CN106206707A CN201510296856.2A CN201510296856A CN106206707A CN 106206707 A CN106206707 A CN 106206707A CN 201510296856 A CN201510296856 A CN 201510296856A CN 106206707 A CN106206707 A CN 106206707A
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Abstract
根据一个实施方式，半导体装置包括：第1半导体层，设置在基板上；第2半导体层，设置在第1半导体层上，包含n型杂质；第3半导体层，设置在第2半导体层上，电阻比第2半导体层大；第4半导体层，设置在第3半导体层上，包含氮化物半导体；以及第5半导体层，设置在第4半导体层上，包含带隙比第4半导体层大的氮化物半导体。
Description
相关申请的交叉引用
本申请基于2015年01月21日提出的在先日本专利申请第2015－009569号并要求享受其优先权利益，并且通过引用在此包含其内容的全部。
技术领域
在此说明的实施方式整体上涉及半导体装置。
背景技术
开关电源、变换器等电路中使用开关元件、二极管等功率半导体元件，对于该功率半导体元件，要求高耐压以及低导通电阻。耐压与导通电阻之间存在由元件材料决定的权衡(trade off)关系，但通过将氮化物半导体或碳化硅(SiC)等宽带隙半导体作为元件材料来使用，与硅相比能够改善由材料决定的权衡关系，能够实现高耐压化以及低导通电阻化。
使用了GaN或AlGaN等氮化物半导体的元件具有优异的材料特性，因此能够实现高性能的功率半导体元件。特别在具有AlGaN/GaN的异质构造的HEMT(High Electron Mobility Transistor)中，由于在AlGaN层与GaN层的界面产生由极化带来的高浓度的二维电子气，因此能够实现低导通电阻。
发明内容
实施方式提供在被施加了高电压的情况下也能够抑制绝缘击穿的半导体装置。
根据一个实施方式，半导体装置具备：第1半导体层，设置在基板上；第2半导体层，设置在所述第1半导体层上，包含n型杂质；第3半导体层，设置在所述第2半导体层上，电阻比所述第2半导体层大；第4半导体层，设置在所述第3半导体层上，包含氮化物半导体；以及第5半导体层，设置在所述第4半导体层上，包含带隙比所述第4半导体层大的氮化物半导体。
根据上述结构的半导体装置，能够提供在被施加了高电压的情况下也能够抑制绝缘击穿的半导体装置。
附图说明
图1是实施方式的半导体装置的截面图。
图2是说明实施方式的半导体装置的动作的示意图。
具体实施方式
以下，参照附图对实施方式进行说明。其中，附图是示意性的或者是概念性的，各附图的尺寸以及比率等不一定必须与现实的结构相同。以下所示的一些实施方式例示了用于将本发明的技术思想具体化的装置以及方法，本发明的技术思想并不通过构成部件的形状、构造、配置等来确定。另外，以下的说明中，对于具有相同功能以及结构的要素附加相同的附图标记，并仅在必要时进行重复说明。
图1是实施方式的半导体装置1的截面图。半导体装置1是使用作为化合物的氮化物半导体的氮化物半导体装置。此外，半导体装置1是场效应晶体管(FET)，具体而言是高电子迁移率晶体管(HEMT：HighElectron Mobility Transistor)。
基板10由例如以(111)面为主面的硅(Si)基板构成。作为基板10，可以使用碳化硅(SiC)、氮化镓(GaN)、磷化镓(GaP)、磷化铟(InP)、砷化镓(GaAs)或蓝宝石(Al2O3)等。此外，作为基板10，也可以使用包含绝缘层的基板。例如，作为基板10，可以使用SOI(SiliconOn Insulator)基板。
缓冲层(第1半导体层)11设置在基板10上。缓冲层11具有对因形成在缓冲层11上的氮化物半导体层的晶格常数与基板10的晶格常数不同而产生的畸变进行缓和、并且对形成在缓冲层11上的氮化物半导体层的结晶性进行控制的功能。缓冲层11例如由AlXGa1－XN(0≤X≤1)构成。
缓冲层11也可以将组分比不同的多个AlXGa1－XN层叠而构成。在将缓冲层11以层叠构造构成的情况下，对层叠构造的组分比进行调整，以使该层叠构造所包含的多个层的晶格常数从夹着缓冲层11的上下层之中的下层的晶格常数向上层的晶格常数变化。本实施方式中，如图1所示，缓冲层11例如由AlGaN层11A和非掺杂GaN层11B的层叠构造构成。非掺杂是指有意地不掺杂杂质，例如，在制造过程等中进入的程度的杂质量是非掺杂的范畴。GaN层11B的厚度例如为1μm左右。
中间层(第2半导体层)12设置在缓冲层11上。中间层12为低电阻层，并且作为横向的电流路径发挥功能。中间层12例如由掺杂有n型杂质的AlXInYGa1－(X+Y)N(0≤X＜1、0≤Y＜1、0≤X+Y＜1)构成。作为n型杂质，使用硅(Si)或锌(Zn)等。本实施方式中，中间层12由掺杂有n型杂质的GaN(n－GaN)或掺杂有n型杂质的AlGaN(n－AlGaN)构成。通过在中间层12中掺杂n型杂质，中间层12的电阻变小。由此，中间层12能够作为横向的电流路径来发挥功能。
另外，中间层12也可以由掺杂有p型杂质的AlXInYGa1－(X+Y)N(0≤X＜1、0≤Y＜1、0≤X+Y＜1)构成。作为p型杂质，使用镁(Mg)等。但是，作为p型杂质的镁(Mg)与作为n型杂质的硅(Si)相比容易扩散。因此，在p型杂质扩散至后述的沟道层14的情况下，沟道层14的结晶性会恶化。因此，中间层12优选掺杂n型杂质而形成。
此外，GaN类材料中的p型杂质的活性率较低，因此基于p型杂质的载流子浓度仅为约5×1016cm－3左右。另一方面，若为n型杂质，则能够使载流子浓度为约1×1019cm－3左右。
通过在中间层12中掺杂n型杂质，中间层12的结晶性恶化。因此，中间层12优选在实现上述的功能的同时形成得更薄。本实施方式中，中间层12的厚度例如为50nm左右。此外，中间层12的厚度被设定为比后述的高电阻层13的厚度小。
中间层12的载流子浓度被设定为1×1016cm－3以上且小于1×1019cm－ 3。若中间层12的载流子浓度小于1×1016cm－3，则中间层12的电阻不会足够小。半导体的导电率(电阻率的倒数)成比例于载流子浓度与迁移率之积。由此，导致流过中间层12的泄漏电流变小。此外，若中间层12的载流子浓度为1×1019cm－3以上，则中间层12的结晶性会恶化，比中间层12更靠上方的层的结晶性也会恶化。结果，半导体装置1的电特性恶化。
进而，中间层12优选在氮化物半导体中掺杂铟(In)来形成。通过掺杂(In)，能够减小中间层12的带隙。由此，能够进一步减小中间层12的电阻。
高电阻层(第3半导体层)13设置在中间层12上。高电阻层13具有提高半导体装置1的耐压的功能，主要提高漏极电极17以及基板10间的耐压。即，通过设置高电阻层13，与高电阻层13的电阻相应的电压被施加到高电阻层13，因此能够与该电压量相应地提高耐压。高电阻层13由掺杂有碳(C)的AlXInYGa1－(X+Y)N(0≤X＜1、0≤Y＜1、0≤X+Y＜1)构成。本实施方式中，高电阻层13例如由掺杂有碳(C)的GaN(C－GaN)构成。高电阻层13的厚度例如为2μm左右。高电阻层13的电阻根据对半导体装置1而言优选的耐压而被适当设定。此外，高电阻层13的电阻被设定为比中间层12的电阻大。
另外，若在中间层12上层叠沟道层(第4半导体层)14，则中间层12的杂质会向沟道层14扩散。通过在中间层12与沟道层14之间插入高电阻层13，能够抑制中间层12的杂质向沟道层14扩散。由此，能够抑制沟道层14的结晶性恶化，因此能够抑制沟道层14的迁移率下降。
沟道层14设置在高电阻层13上。沟道层14是形成晶体管的沟道(电流路径)的层。沟道层14由AlXInYGa1－(X+Y)N(0≤X＜1、0≤Y＜1、0≤X+Y＜1)构成。沟道层14是非掺杂层，并且由结晶性良好的(高品质的)氮化物半导体构成。本实施方式中，沟道层14由非掺杂GaN(也称为本征GaN)构成。沟道层14的厚度例如为1μm左右。
阻挡层(第5半导体层)15设置在沟道层14上。阻挡层15由AlXInYGa1－(X+Y)N(0≤X＜1、0≤Y＜1、0≤X+Y＜1)构成。阻挡层15由带隙比沟道层14的带隙大的氮化物半导体构成。本实施方式中，阻挡层15例如由非掺杂AlGaN构成。作为阻挡层15的AlGaN层中的Al的组分比例如为0.2左右。阻挡层15的厚度例如为30nm左右。
另外，构成半导体装置1的多个半导体层例如通过使用MOCVD(Metal Organic Chemical Vapor Deposition)法的外延生长而被依次形成。即，构成半导体装置1的多个半导体层由外延层构成。
在阻挡层15上设有相互离开的源极电极16以及漏极电极17。进而，在阻挡层15上且在源极电极16以及漏极电极17之间，与源极电极16以及漏极电极17离开地设有栅极电极18。
栅极电极18与阻挡层15进行肖特基接合。即，栅极电极18构成为包含与阻挡层15进行肖特基接合的材料。图1所示的半导体装置1为肖特基势垒型HEMT。作为栅极电极18，例如使用Au/Ni的层叠构造。“/”的左侧表示上层，右侧表示下层。另外，半导体装置1不限定于肖特基势垒型HEMT，也可以是在阻挡层15与栅极电极18之间存在栅极绝缘膜的MIS(Metal Insulator Semiconductor)型HEMT。
源极电极16与阻挡层15进行欧姆接触。同样，漏极电极17与阻挡层15进行欧姆接触。即，源极电极16以及漏极电极17分别构成为包含与阻挡层15进行欧姆接触的材料。作为源极电极16以及漏极电极17，例如使用Al/Ti的层叠构造。
在沟道层14与阻挡层15的异质结构造中，阻挡层15的晶格常数比沟道层14的晶格常数小，因此阻挡层15发生畸变。通过由该畸变带来的压电效应，在阻挡层15内产生压电极化，在沟道层14中的与阻挡层15的界面附近产生二维电子气(2DEG：two-dimensional electron gas)。该二维电子气成为源极电极16以及漏极电极17间的沟道。并且，通过由栅极电极18与阻挡层15的接合而产生的肖特基势垒，能够实现漏极电流的控制。
(动作)
接着，对如上述那样构成的半导体装置1的动作进行说明。图2是说明半导体装置1的动作的示意图。
半导体装置1例如为常通型。半导体装置1例如被用作开关元件，漏极电极17上有时被施加200V～600V左右的高电压。对半导体装置1施加的电压越高，半导体装置1中产生的泄漏电流即流过漏极电极17以及基板10之间的泄漏电流、以及流过漏极电极17以及源极电极16之间的泄漏电流越大。
半导体装置1导通时，例如被施加栅极电压Vg＝0V、源极电压Vs＝0V、漏极电压Vd＝200V。此时，在漏极电极17以及源极电极16之间，经由在沟道层14形成的沟道而流过漏极电流。
在半导体装置1截止时，例如被施加栅极电压Vg＝－15V、源极电压Vs＝0V、漏极电压Vd＝200V。此时，在漏极电极17以及源极电极16之间，经由中间层12而流过泄漏电流。
图2的表示泄漏电流的虚线概念性地表示泄漏电流的路径，并不限于如图2那样流过泄漏电流。若漏极电极17上被施加高电压，则从漏极电极17朝向基板10产生电场，并且从漏极电极17朝向源极电极16产生电场。并且，与从漏极电极17扩散的电场相应地产生泄漏电流，在泄漏电流的路径达到中间层12的情况下，从其位置经由中间层12向源极电极16流过泄漏电流。
由此，能够抑制因施加到漏极电极17的高电压而半导体装置1绝缘击穿(breakdown)。特别是，高电阻层13由于电阻较大，所以高电阻层13上被施加较高的电场，高电阻层13容易被绝缘击穿。此外，若高电阻层13中流过泄漏电流，则由于高电阻层13内的结晶缺陷而高电阻层13容易被绝缘击穿。但是，通过经由中间层12而流过泄漏电流，能够抑制高电阻层13绝缘击穿。
另外，在漏极电极17上被施加高电压的情况下，在半导体装置1导通时也能够使得经由中间层12而在漏极电极17以及源极电极16之间流过泄漏电流。因此，在半导体装置1导通时，能够抑制半导体装置1绝缘击穿。
(效果)
如以上详细叙述的那样，在本实施方式中，在缓冲层11与高电阻层13之间，还设置由掺杂有n型杂质的AlXInYGa1－(X+Y)N(0≤X＜1、0≤Y＜1、0≤X+Y＜1)构成的中间层12。该中间层12在漏极电极17被施加了高电压的情况下，作为横向的电流路径来发挥功能。
因而，根据本实施方式，在漏极电极17被施加了高电压的情况下，也能够抑制半导体装置1绝缘击穿。即，能够实现可增大针对绝缘击穿的临界电压的半导体装置1。
本申请说明书中，“层叠”除了相互相接而重叠的情况以外，还包括在中间插入其他层而重叠的情况。此外，“设置在…上”，除了直接相接而设置的情况以外，该包括在中间插入其他层而设置的情况。
说明了本发明的一些实施方式，但这些实施方式是作为例来提示的，并没有要限定发明的范围。这些新的实施方式能够以其他多种形态实施，在不脱离发明的主旨的范围内能够进行各种省略、替换、变更。这些实施方式及其变形包含于发明的范围及主旨，并且包含于权利要求书所记载的发明及其等价范围。
Claims (7)
1.一种半导体装置，其特征在于，具备：
第1半导体层，设置在基板上；
第2半导体层，设置在所述第1半导体层上，包含n型杂质；
第3半导体层，设置在所述第2半导体层上，电阻比所述第2半导体层大；
第4半导体层，设置在所述第3半导体层上，包含氮化物半导体；以及
第5半导体层，设置在所述第4半导体层上，包含带隙比所述第4半导体层大的氮化物半导体。
2.如权利要求1所述的半导体装置，其特征在于，
所述第2半导体层的载流子浓度为1×1016cm－3以上且小于1×1019cm－3。
3.如权利要求1或2所述的半导体装置，其特征在于，
所述第2半导体层包含由AlXInYGa1－(X+Y)N构成的材料，其中，0≤X＜1，0≤Y＜1，0≤X+Y＜1。
4.如权利要求1或2所述的半导体装置，其特征在于，
所述第2半导体层包含与所述第1半导体层相同的半导体材料。
5.如权利要求1或2所述的半导体装置，其特征在于，
所述第1半导体层包含由AlXGa1－XN构成的材料，其中，0≤X≤1。
6.如权利要求1或2所述的半导体装置，其特征在于，
所述第3半导体层包含含有碳的氮化物半导体。
7.如权利要求1或2所述的半导体装置，其特征在于，
所述第2半导体层的厚度比所述第3半导体层的厚度小。
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| US20020094002A1 (en) * | 1999-07-16 | 2002-07-18 | Hiroshi Amano | Nitride semiconductor layer structure and a nitride semiconductor laser incorporating a portion of same |
| WO2005074019A1 (ja) * | 2004-01-28 | 2005-08-11 | Sanken Electric Co., Ltd. | 半導体装置 |
| CN102623498A (zh) * | 2011-01-26 | 2012-08-01 | 株式会社东芝 | 半导体元件 |
| CN103155124A (zh) * | 2010-11-19 | 2013-06-12 | 松下电器产业株式会社 | 氮化物半导体装置 |
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| US7326971B2 (en) * | 2005-06-08 | 2008-02-05 | Cree, Inc. | Gallium nitride based high-electron mobility devices |
| JP6151487B2 (ja) | 2012-07-10 | 2017-06-21 | 富士通株式会社 | 化合物半導体装置及びその製造方法 |
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| US20020094002A1 (en) * | 1999-07-16 | 2002-07-18 | Hiroshi Amano | Nitride semiconductor layer structure and a nitride semiconductor laser incorporating a portion of same |
| WO2005074019A1 (ja) * | 2004-01-28 | 2005-08-11 | Sanken Electric Co., Ltd. | 半導体装置 |
| CN103155124A (zh) * | 2010-11-19 | 2013-06-12 | 松下电器产业株式会社 | 氮化物半导体装置 |
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