CN106201944A - A kind of method realizing I2C and the conversion of MDIO communication interface protocol - Google Patents
A kind of method realizing I2C and the conversion of MDIO communication interface protocol Download PDFInfo
- Publication number
- CN106201944A CN106201944A CN201610480916.0A CN201610480916A CN106201944A CN 106201944 A CN106201944 A CN 106201944A CN 201610480916 A CN201610480916 A CN 201610480916A CN 106201944 A CN106201944 A CN 106201944A
- Authority
- CN
- China
- Prior art keywords
- mdio
- address
- depositor
- data
- byte
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Communication Control (AREA)
Abstract
The invention discloses a kind of method realizing I2C and the conversion of MDIO communication interface protocol, the method is for reformulating I2C communication frame structure so that it is meets MDIO register access, thus realizes conversion in real time；Or, internal register based on SFP module, use the reserved access interface that MDIO is provided from address or depositor, main frame realized the access of MDIO data by depositor.The method achieve the protocol conversion that in IEEE802.3 standard, the 45th chapter MDIO communication mode communicates with tradition I2C, be conveniently used for the module product design of more than 10G band PHY, directly continue to use the I2C interface of original module, effectively reduce product design costs.
Description
Technical field
The present invention relates to a kind of method that communication protocol is mutually changed and docked, specifically one realize I2C and MDIO lead to
The method of letter interface protocol conversion, belongs to technical field of electronic devices.
Background technology
It is said that in general, the PHY chip of ethernet communication, the most all support that MDIO interface is to realize the visit of internal register
Ask.Current high speed switch equipment is widely used SFP interface module to carry out data transmission.SFP module there is one
RJ45Copper electrical interface module, is all integrated with a PHY chip inside it.The management communication interface standard that SFP module is external
Being I2C, the externally management communication interface of PHY chip is MDIO, and both can not directly dock.
System equipment the most all can not directly access PHY internal register, but come real by the MCU of SFP inside modules
The configuration of existing function.But due to system debug and the needs of monitoring in real time, system equipment is required to directly post PHY inside
Storage is read out and revises.
Currently for the PHY chip of below 1000M speed, MDIO communication agreement meets the 22nd chapter rule of IEEE802.3ae
Fixed, its access mode is as shown in Figure 1.Wherein, PHYAD is the physical address of product, is typically determined by hardware pins；REGAD
It is register address, only five bit, the most be up to 32 depositors.Due to internal register negligible amounts, so can be direct
Realized by the addressing space of I2C 256 byte.Generally use the I2C of 0xAC from address, thus reach with SFP's
I2C communication interface pattern is compatible.
For 10Gbpc and above application, IEEE802.3ae standard changes for MDIO communication interface standard, fixed
Justice is at the 45th chapter, as shown in Figures 2 and 3.Wherein, PRTAD refers to the physical address of product, is generally determined by hardware pins；
DEVAD refers to device address, supports 32 kinds of different types of depositors.Each Device Address is to there being 65536
Depositor (Regsiter), so there being special communication frame (Frame) to be configured register address (Address).
In view of the situation, just have no idea to use one of I2C from address to realize the direct access of PHY depositor.But, 10G
The SFP module of BASE_T must use this kind of PHY chip, it is also desirable to support the access of PHY chip depositor.Accordingly, it would be desirable to
A kind of I2C interface changing the mechanism to MDIO interface, thus realize the depositor by I2C interface accessing PHY.
Summary of the invention
The problem existed for above-mentioned prior art, the present invention provides one to realize I2C and MDIO communication interface protocol turns
The method changed, the method is changed the mechanism by being formed between MDIO and I2C of more than 10G PHY chip, thus is realized physics even
Connect.
The present invention is achieved through the following technical solutions above-mentioned purpose: one realizes I2C and MDIO communication interface protocol turns
The method changed, the method is for reformulating I2C communication frame structure so that it is meets MDIO register access, thus realizes turning in real time
Change；Or, internal register based on SFP module, use the reserved access interface that MDIO is provided from address or depositor,
Realized the access of MDIO data by depositor by main frame.
Further, I2C communication frame structure is reformulated described in so that it is meet MDIO register access and comprise the steps:
1) depositor is carried out write operation: after I2C main frame sends initial signal, send from address+write, receive
After machine ack signal, send Device Address, receive after machine ACK, retransmit two bytes
RegisterAddress, most-significant byte, front, retransmits the data needing to write this depositor, and most-significant byte, front, finally send and terminates
Signal；
2) depositor is read: after I2C main frame sends initial signal, sends from address (+write, receipts
To after machine ack signal, send Device Address, receive after machine ACK, retransmit two bytes
RegisterAddress, most-significant byte, front, then sends end signal；
3) read data: after I2C main frame sends initial signal, send from address+reading, receive after machine ack signal,
Reading a byte from I2C bus, this byte is to read the most-significant byte of data, and main frame sends ack signal, then proceedes to read
One byte, this byte is to read the least-significant byte of data, and main frame sends NACK signal, represents that reading is complete, finally sends and terminates letter
Number.
Described step 3) in, between twice communication of reading, need to stop enough time delays, in order to I2C completes from machine
The acquisition of MDIO data.
Internal register based on SFP module, uses the reserved access interface providing MDIO from address or depositor,
The access being realized MDIO data by depositor by main frame comprises the steps:
1) depositor is carried out write operation:
Step1., DEVAD to be visited is set:
By the Byte 0x70 of DEVAD value write I2C A2 Page,
Step2., Register Address to be visited is set:
16bit Register Address value is respectively written into Byte 0x71 and 0x72 of I2C A2 Page,
MSB writes 0x71, LSB and writes 0x72,
Step3., 16bit numerical value Write Data to be write is set
16bit Write Data value is respectively written into Byte 0x73 and 0x74 of I2C A2 Page,
MSB writes 0x73, LSB and writes 0x74,
Step4. write Command order
By the Byte 0x6E of value 0x01 write I2C A2 Page,
Step5. Wait Order is waited to perform
Step6. result of query execution
Read the Byte 0x6F of A2 Page,
If state is Busy, then repeat Step5 and Step6,
If state is Fail, then it represents that order performs failure,
If state is Complete, then it represents that order runs succeeded.
2) depositor is read:
Step1., DEVAD to be visited is set:
By the Byte 0x70 of DEVAD value write I2C A2 Page,
Step2., Register Address to be visited is set:
16bit Register Address value is respectively written into Byte 0x71 and 0x72 of I2C A2 Page
MSB writes 0x71, LSB and writes 0x72,
Step3. write Command order
By the Byte 0x6E of value 0x02 write I2C A2 Page,
Step4. Wait Order is waited to perform
Step5. result of query execution
Read the Byte 0x6F of A2 Page,
If state is Busy, then repeat Step4 and Step5
If state is Fail, then it represents that order performs failure,
If state is Complete, then it represents that order runs succeeded, and continues executing with Step6
Step6. data are read
Read A2 Page Byte0x75 and 0x76,0x75 be MSB, 0x76 be LSB,
This 16bit value is reading result.
The invention has the beneficial effects as follows: the method achieve the 45th chapter MDIO communication mode and biography in IEEE802.3 standard
The protocol conversion of system I2C communication, is conveniently used for the module product design of more than 10G band PHY, directly continues to use the I2C of original module
Interface, effectively reduces product design costs.
Wherein, the advantage of first kind of way (method directly revising I2C communication frame structure) is to change in real time, and efficiency is more
Height, and need not additionally take the internal register space of module.However, to ensure that certain real-time index, to process
The execution speed of device has certain requirement；The advantage of the second way (providing the mode of MDIO visit order) is, owing to being
Directly utilize the reservation register of module, so main frame need not make any amendment on communication mode, simultaneously to inside modules
Processor requirement is the highest, and wrong display, error handling mechanism is more perfect.
Accompanying drawing explanation
Fig. 1 is the PHY chip access mode schematic diagram of below the 1000M speed that prior art exists；
Fig. 2 be prior art exist 10G bpc and use above in MDIO communication interface standard schematic diagram；
Fig. 3 is 32 kinds of different types of depositor schematic diagrams in prior art；
Fig. 4 is the physical connection schematic diagram of more than 10G PHY chip functional realiey in the present invention.
Detailed description of the invention
Below in conjunction with embodiments of the invention, the technical scheme in the embodiment of the present invention is clearly and completely retouched
State, it is clear that described embodiment is only a part of embodiment of the present invention rather than whole embodiments.Based on the present invention
In embodiment, the every other enforcement that those of ordinary skill in the art are obtained under not making creative work premise
Example, broadly falls into the scope of protection of the invention.
As shown in Figure 4: a kind of method realizing I2C and the conversion of MDIO communication interface protocol, the method is for reformulating I2C
Communication frame structure so that it is meet MDIO register access, thus realize conversion in real time；Or, inside based on SFP module is deposited
Device, uses the reserved access interface providing MDIO from address or depositor, main frame realizes MDIO data by depositor
Access.
Embodiment one, the method directly revising I2C communication frame structure:
Principle position works out the data form of I2C communication again so that it is meet the needs of MDIO register access.Frame structure is such as
Under:
1) depositor is carried out write operation:
After I2C main frame sends initial signal, send from address (7bit)+write (W, 1bit signal is 0), receive from machine
After ack signal, (wherein bit7-bit5 is 0, and bit4-bit0 is 5bit Device to send Device Address (DEVAD)
Address), receiving after machine ACK, retransmit the Register Address of two bytes (16bit), most-significant byte (MSB) exists
Before, then retransmiting and need to write the data of this depositor (16bit Write Data), most-significant byte (MSB), front, finally sends
End signal (STOP).As shown in Table 1.
Table one: register write operation flow table
2) depositor is read:
First read operation to be write register address in two steps:
After I2C main frame sends initial signal, send from address (7bit)+write (W, 1bit signal is 0), receive from machine
After ack signal, (wherein bit7-bit5 is 0, and bit4-bit0 is 5bitDevice to send Device Address (DEVAD)
Address), receiving after machine ACK, retransmit the Register Address of two bytes (16bit), most-significant byte (MSB) exists
Before, then send end signal (STOP).As shown in Table 2.
Table two: write register address flow table during reading
Then data are read:
After I2C main frame sends initial signal, send from address (7bit)+reading (R, 1bit signal is 1), receive from machine
After ack signal, then reading a byte from I2C bus, this byte is to read most-significant byte (the Read Data of data
MSB), main frame sends ack signal, then proceedes to read a byte, and this byte is to read least-significant byte (the Read Data of data
LSB), main frame sends NACK signal, represents that reading is complete, finally sends end signal (STOP).As shown in Table 3.
Table three: reading data flow journey table
It should be noted that between twice communication read, it is necessary to reserved enough time delays, in order to I2C is complete from machine
Become the acquisition of MDIO data.
Embodiment two, it is provided that the mode of MDIO visit order:
Principle is on the basis of the internal register of SFP module, uses reserved providing from address or depositor
The access interface of MDIO, is realized the access of MDIO data by main frame by the configuration of these depositors.
Table four: depositor table
Table five: the explanation table of command register (Command)
Table six: the explanation table of status register (Status)
| Status value | Title | State description |
| 0x00 | Idel/Complete | Idle/order runs succeeded |
| 0xFF | Fail | Order performs failure |
| 0xBB | Busy | During order performs, command execution results please be wait |
By table four to table six, as reference, thus it is best understood from providing the mode of MDIO visit order:
1) depositor is carried out write operation:
Step1., DEVAD to be visited is set:
Byte 0x70 by DEVAD value write I2C A2 Page.
Step2., Register Address to be visited is set:
16bit Register Address value is respectively written into Byte 0x71 and 0x72. of I2C A2 Page
MSB writes 0x71, LSB and writes 0x72.
Step3., 16bit numerical value Write Data to be write is set
16bit Write Data value is respectively written into Byte 0x73 and 0x74. of I2C A2 Page
MSB writes 0x73, LSB and writes 0x74.
Step4. write Command order
Byte 0x6E by value 0x01 write I2C A2 Page.
Step5. Wait Order is waited to perform
Step6. result of query execution
Read the Byte 0x6F of A2 Page,
If state is Busy, then repeat Step5 and Step6.
If state is Fail, then it represents that order performs failure.
If state is Complete, then it represents that order runs succeeded.
2) depositor is read:
Step1., DEVAD to be visited is set:
Byte 0x70 by DEVAD value write I2C A2 Page.
Step2., Register Address to be visited is set:
16bit Register Address value is respectively written into Byte 0x71 and 0x72. of I2C A2 Page
MSB writes 0x71, LSB and writes 0x72.
Step3. write Command order
Byte 0x6E by value 0x02 write I2C A2 Page.
Step4. Wait Order is waited to perform
Step5. result of query execution
Read the Byte 0x6F of A2 Page,
If state is Busy, then repeat Step4 and Step5.
If state is Fail, then it represents that order performs failure.
If state is Complete, then it represents that order runs succeeded, and continues executing with Step6.
Step6. data are read
Read A2 Page Byte0x75 and 0x76,0x75 be MSB, 0x76 be LSB.
This 16bit value is reading result.
Embodiment provided above is the better embodiment of the present invention, is only used for the convenient explanation present invention, not to this
Bright make any pro forma restriction, any art has usually intellectual, if without departing from the carried skill of the present invention
In the range of art feature, utilize the Equivalent embodiments that the done local of disclosed technology contents is changed or modified, and
Without departing from the technical characteristic content of the present invention, all still fall within the range of the technology of the present invention feature.
Claims (4)
1. the method realizing I2C and the conversion of MDIO communication interface protocol, it is characterised in that: the method is for reformulating I2C
Communication frame structure so that it is meet MDIO register access, thus realize conversion in real time；Or, inside based on SFP module is deposited
Device, uses the reserved access interface providing MDIO from address or depositor, main frame realizes MDIO data by depositor
Access.
A kind of method realizing I2C and the conversion of MDIO communication interface protocol the most according to claim 1, it is characterised in that
Described reformulate I2C communication frame structure so that it is meet MDIO register access and comprise the steps:
1) depositor is carried out write operation: after I2C main frame sends initial signal, send from address+write, receive from machine
After ack signal, send Device Address, receive after machine ACK, retransmit the Register of two bytes
Address, most-significant byte, front, retransmits the data needing to write this depositor, and most-significant byte, front, finally sends end signal；
2) depositor is read: after I2C main frame sends initial signal, sends from address+write, receive from machine
After ack signal, send Device Address, receive after machine ACK, retransmit the Register of two bytes
Address, most-significant byte, front, then sends end signal；
3) read data: after I2C main frame sends initial signal, send from address+reading, receive after machine ack signal, from
Reading a byte in I2C bus, this byte is to read the most-significant byte of data, and main frame sends ack signal, then proceedes to read one
Individual byte, this byte is to read the least-significant byte of data, and main frame sends NACK signal, represents that reading is complete, finally sends and terminates letter
Number.
A kind of method realizing I2C and the conversion of MDIO communication interface protocol the most according to claim 2, it is characterised in that
Described step 3) in, between twice communication of reading, need to stop enough time delays, in order to I2C completes MDIO data from machine
Obtain.
A kind of method realizing I2C and the conversion of MDIO communication interface protocol the most according to claim 1, it is characterised in that
Internal register based on SFP module, uses the reserved access interface providing MDIO from address or depositor, main frame leads to
Cross depositor to realize the access of MDIO data and comprise the steps:
1) depositor is carried out write operation:
Step1., DEVAD to be visited is set,
Step2., Register Address to be visited is set,
Step3., 16bit numerical value Write Data to be write is set,
Step4. write Command order,
Step5. Wait Order is waited to perform,
Step6. result of query execution,
If state is Busy, then repeat Step5 and Step6,
If state is Fail, then it represents that order performs failure,
If state is Complete, then it represents that order runs succeeded；
2) depositor is read:
Step1., DEVAD to be visited is set,
Step2., Register Address to be visited is set,
Step3. write Command order,
Step4. Wait Order is waited to perform,
Step5. result of query execution,
If state is Busy, then repeat Step4 and Step5,
If state is Fail, then it represents that order performs failure,
If state is Complete, then it represents that order runs succeeded, and continues executing with Step6,
Step6. data are read.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610480916.0A CN106201944A (en) | 2016-06-27 | 2016-06-27 | A kind of method realizing I2C and the conversion of MDIO communication interface protocol |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610480916.0A CN106201944A (en) | 2016-06-27 | 2016-06-27 | A kind of method realizing I2C and the conversion of MDIO communication interface protocol |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106201944A true CN106201944A (en) | 2016-12-07 |
Family
ID=57461217
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610480916.0A Pending CN106201944A (en) | 2016-06-27 | 2016-06-27 | A kind of method realizing I2C and the conversion of MDIO communication interface protocol |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106201944A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109683960A (en) * | 2018-12-21 | 2019-04-26 | 深圳市源拓光电技术有限公司 | A kind of register configuration method and its electrical port module of electrical port module |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060069831A1 (en) * | 2004-09-29 | 2006-03-30 | Mitsubishi Denki Kabushi Kaisha | I2C bus controlling method |
| CN100416536C (en) * | 2006-11-09 | 2008-09-03 | 中兴通讯股份有限公司 | Bulk memory accessing method for I2C controller in 10-site addressing mode |
| CN103226533A (en) * | 2013-03-29 | 2013-07-31 | 福建星网锐捷通讯股份有限公司 | Device for extending MDIO (management data input/output) interface through parallel buses and realizing method thereof |
| CN103677671A (en) * | 2013-12-12 | 2014-03-26 | 青岛海信宽带多媒体技术有限公司 | Data reading-writing method and system of electrical port module |
-
2016
- 2016-06-27 CN CN201610480916.0A patent/CN106201944A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060069831A1 (en) * | 2004-09-29 | 2006-03-30 | Mitsubishi Denki Kabushi Kaisha | I2C bus controlling method |
| CN100416536C (en) * | 2006-11-09 | 2008-09-03 | 中兴通讯股份有限公司 | Bulk memory accessing method for I2C controller in 10-site addressing mode |
| CN103226533A (en) * | 2013-03-29 | 2013-07-31 | 福建星网锐捷通讯股份有限公司 | Device for extending MDIO (management data input/output) interface through parallel buses and realizing method thereof |
| CN103677671A (en) * | 2013-12-12 | 2014-03-26 | 青岛海信宽带多媒体技术有限公司 | Data reading-writing method and system of electrical port module |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109683960A (en) * | 2018-12-21 | 2019-04-26 | 深圳市源拓光电技术有限公司 | A kind of register configuration method and its electrical port module of electrical port module |
| CN109683960B (en) * | 2018-12-21 | 2021-03-30 | 深圳市源拓光电技术有限公司 | Register configuration method of electric port module and electric port module thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105549552B (en) | CAN bus expansion system and method based on Linux | |
| CN203812236U (en) | Data exchange system based on processor and field programmable gate array | |
| CN208188815U (en) | BMC module system | |
| CN104714907B (en) | A kind of pci bus is converted to ISA and APB bus design methods | |
| CN100480923C (en) | Controller soft realizing method from I2C bus | |
| CN104484301A (en) | FPGA-based (Field Programmable Gate Array-based) IO (Input/Output) bus device with automatic recognition function | |
| CN108566324B (en) | System and method based on isolated dual Ethernet and dual CAN communication | |
| CN204256732U (en) | The high-speed data transmission apparatus of Based PC I-Express interface | |
| CN106201944A (en) | A kind of method realizing I2C and the conversion of MDIO communication interface protocol | |
| CN107643993A (en) | Bus conversion interface, the method for work of bus conversion interface and communication equipment | |
| CN110708324A (en) | Method and system for realizing point-to-point communication between FPGA (field programmable Gate array) board cards | |
| CN103425434A (en) | Multichannel RAM (random-access memory) reading/writing circuit and method | |
| CN107391332A (en) | A kind of storage system and debugging system | |
| CN104050121A (en) | Double-receiving double-emitting programmable ARINC 429 communication interface chip | |
| CN101309257A (en) | Single board communication method and system based on internal integrated circuit bus | |
| CN113783584B (en) | Isolated single-wire serial communication device and method | |
| CN111930649B (en) | Multi-channel CAN communication board card and communication method | |
| CN201828970U (en) | Train operation data recorder based on CAN (Controller Area Network) interface | |
| CN205485338U (en) | Intelligence electronic stopwatch | |
| CN207543130U (en) | A kind of gateway system | |
| CN210377460U (en) | CPU single Data line and double DDR internal memory connecting structure | |
| CN103365804B (en) | A kind of read-write control device for chip BU-65170 | |
| CN114168519A (en) | Working robot control system based on serial bus communication technology | |
| CN206421379U (en) | PCIE terminal device boards based on PCH | |
| CN203287889U (en) | Control device of SD/MMC card and IIC slave device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20161207 |
|
| RJ01 | Rejection of invention patent application after publication |