CN206421379U - PCIE terminal device boards based on PCH - Google Patents
PCIE terminal device boards based on PCH Download PDFInfo
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- CN206421379U CN206421379U CN201720131788.9U CN201720131788U CN206421379U CN 206421379 U CN206421379 U CN 206421379U CN 201720131788 U CN201720131788 U CN 201720131788U CN 206421379 U CN206421379 U CN 206421379U
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- pch
- golden finger
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- 230000005540 biological transmission Effects 0.000 abstract description 6
- 238000005516 engineering process Methods 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
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- 230000001360 synchronised effect Effects 0.000 description 1
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Abstract
The utility model discloses the PCIE terminal device boards based on PCH, belong to board, the technical problems to be solved in the utility model is：How just can guarantee that with larger data transmission capabilities, realize the high-speed transfer of network signal.The technical scheme used for：PCIE terminal device boards based on PCH, the board is configured with PCH, golden finger, QSFP connectors, FLASH chip and clock oscillator；PCH is the PCH for Purley platforms LBG series；Clock oscillator is used to provide feedback clock to PCH LBG chips；PCH connects golden finger, QSFP connectors and FLASH chip respectively.PCIE3.0 X16 expansion interfaces and PCIE3.0 X8 expansion interfaces are configured with golden finger, PCH LBG chips are connected with the PCIE3.0 X16 expansion interfaces and PCIE3.0 X8 expansion interfaces of golden finger respectively by PCIE3.0 X16 buses and PCIE3.0 X8 buses.
Description
Technical field
The utility model is related to a kind of board, the PCIE terminal device boards specifically based on PCH.
Background technology
At present, in traditional computer card design, traditional PCH（English full name Platform Controller
Hub, is the integrated south bridge of an intel company）Interacted with CPU by DMI（English full name Direct Media
InterfaceI, is that intel companies develop bus for connecting mainboard north and south bridge）, all it is logical between processor and PCH chips
Cross what DMI buses were directly connected to.And DMI uses point-to-point connected mode, clock frequency is 100MHz, is connection mainboard
The bus of north and south bridge, DMI can realize each 1GB/s of uplink and downlink data transmission rate, i.e., the largest data transfer amount to CPU can
To export the network signal of gigabit.
However, with the rapidly growth of data volume, traditional DMI buses connection uses the connection of single channel or two-way more,
The connected mode can not meet the demand that market increases to high-speed data.And in traditional circuit design, generally in PCH
On only devise one group of DMI bus and be connected with processor, it is impossible to be connected while realizing multiprocessor with PCH.
It is " a kind of to support multiloop loop system is arbitrarily handled to start and High redundancy that patent is CN 205050131 U, entitled
Circuit ", the mode that the DMI circuits that the circuit draws processor are directly connected to PCH is devised a kind of based on PCLE
The logic circuit of Switch chips, realizes the DMI circuits of each processor and PCH share and access in multiloop loop system, can
The DMI buses on existing PCH are overcome there was only one group, multiple physical locations and system can not be connected and can not start and superfluous by solving
Remaining defect problem.But, there is a problem in that：1st, the volume of transmitted data of DMI buses is low, it is impossible to the transmission number of a large amount of high speeds
According to；2nd, processor live load is high, it is impossible to the utilization PCH of freedom and flexibility function.
Therefore, how just can guarantee that with larger data transmission capabilities, realize the high-speed transfer of network signal, Yi Jishi
The problem of existing PCH flexible utilization is in the urgent need to address at present.
The content of the invention
Technical assignment of the present utility model is that deficiency is there is provided the PCIE terminal device boards based on PCH for more than, to solve
Certainly the volume of transmitted data of DMI buses is low, it is impossible to which the transmission data and processor live load of a large amount of high speeds are high, it is impossible to freely spirit
The problem of utilization PCH living function.
Technical assignment of the present utility model realizes in the following manner,
PCIE terminal device boards based on PCH（Endpoint terminals）, the board include PCH, golden finger (Gold
Finger), QSFP connectors（English full name Quad Small Form-factor Pluggable, four-way SFP interfaces are passed
Defeated speed has reached 40Gbps）, FLASH chip（English name is Flash Memory, and it belongs to one kind of memory devices）With
Clock oscillator（OSC is Oscillator abbreviation, means oscillator, crystal oscillator is a kind of energy conversion device -- by direct current
The AC energy with certain frequency can be converted to）；PCH is for Purley platforms LBG（Lewiburg）The PCH of series；When
Clock oscillator is used to provide feedback clock to PCH LBG chips；PCH connects golden finger, QSFP connectors and FLASH cores respectively
Piece.
PCIE3.0 X16 expansion interfaces and PCIE3.0 X8 expansion interfaces, PCH LBG are configured with described golden finger
Chip by PCIE3.0 X16 buses and PCIE3.0 X8 buses respectively with the PCIE3.0 X16 expansion interfaces of golden finger and
PCIE3.0 X8 expansion interfaces are connected.
QSFP connectors pass through 4*SFI buses（SFI points are receiving terminal and transmitting terminal, are point-to-point communications, receive direction,
Rising edge clock is set to be located at the centre position of data valid window；Sending direction, sends out clock along unidirectional data of aliging
Edge）It is connected with PCH.
FLASH chip passes through spi bus (Serial Peripheral Interface- Serial Peripheral Interface (SPI)s, total linear system
System is a kind of synchronous serial Peripheral Interface, and it can make MCU be communicated with exchanging letter in a serial fashion with various ancillary equipment
Breath）It is connected with PCH.
Described golden finger is PCIE X24 golden fingers.
The nominal frequency of described clock oscillator is 48M, 25M and 33K.
PCIE terminal devices board of the present utility model based on PCH compared to the prior art, with advantages below：
1st, the LBG chips on the utility model board and one group of PCIE3.0 X16 on the CPU golden finger for interacting use
Expansion interface and one group of optional PCIE3.0 X8 expansion interface, PCH are conducive to a large amount of, the height of information as CPU EP equipment
Speed transmission, the utilization PCH of freedom and flexibility function；
2nd, the utility model is using PCH as network interface card, and with internal 10G networks, 10G networks can export 10,000,000,000 network
Signal, information output quantity is big；
3rd, the QAT that the board has Intel quickly assists technology, and the technology can lighten the burden to processor, PCH is had pressure
Contracting, is encrypted, the function such as public keys；
4th, FLASH chip reads PCH data；
5th, QSFP connectors can connect interchanger, realize the purpose of data between hosts exchange；
6th, the board structure is reasonable in design, simple in construction, small volume, easy to use, has good value for applications.
Brief description of the drawings
The utility model is further illustrated below in conjunction with the accompanying drawings.
Accompanying drawing 1 is the structured flowchart of the PCIE terminal device boards based on PCH；
Embodiment
With reference to Figure of description and specific embodiment the PCIE terminal devices board of the present utility model based on PCH is made with
Under explain.
Embodiment 1：
PCIE terminal device boards based on PCH, the board is configured with PCH, golden finger, QSFP connectors, FLASH chip
And clock oscillator；PCH is the PCH for Purley platforms LBG series；Clock oscillator is used to provide PCH LBG chips
Feedback clock；PCH connects golden finger, QSFP connectors and FLASH chip respectively；PCIE3.0 X16 expansions are configured with golden finger
Interface and PCIE3.0 X8 expansion interfaces are opened up, PCH LBG chips pass through PCIE3.0 X16 buses and PCIE3.0 X8 buses point
It is not connected with the PCIE3.0 X16 expansion interfaces and PCIE3.0 X8 expansion interfaces of golden finger, golden finger is the golden hands of PCIE X24
Refer to；QSFP connectors are connected by 4*SFI buses with PCH；FLASH chip is connected by spi bus with PCH.
The nominal frequency of clock oscillator is 48M, 25M and 33K, and the frequency of oscillation that clock oscillator work is produced is PCH
LBG chips provide 100M feedback clock, realize the output of information.FLASH chip is connected by spi bus with PCH, is read
PCH is used as storage firmware during EP.QSFP connectors are connected by 4*SFI buses with PCH, realize the exchange of data between hosts.
By embodiment above, the those skilled in the art can readily realize the utility model.But
It is it should be appreciated that the utility model is not limited to above-mentioned embodiment.It is described on the basis of disclosed embodiment
Those skilled in the art can be combined different technical characteristics, so as to realize different technical schemes.
It is the known technology of those skilled in the art in addition to the technical characteristic described in specification.
Claims (6)
1. the PCIE terminal device boards based on PCH, it is characterised in that PCH, golden finger, QSFP connections are configured with the board
Device, FLASH chip and clock oscillator；PCH is the PCH for Purley platforms LBG series；Clock oscillator is used for PCH
LBG chips provide feedback clock；PCH connects golden finger, QSFP connectors and FLASH chip respectively.
2. the PCIE terminal device boards according to claim 1 based on PCH, it is characterised in that be configured with golden finger
PCIE3.0 X16 expansion interfaces and PCIE3.0 X8 expansion interfaces, PCH LBG chips by PCIE3.0 X16 buses and
PCIE3.0 X8 buses are connected with the PCIE3.0 X16 expansion interfaces and PCIE3.0 X8 expansion interfaces of golden finger respectively.
3. the PCIE terminal device boards according to claim 1 based on PCH, it is characterised in that QSFP connectors pass through 4*
SFI buses are connected with PCH.
4. the PCIE terminal device boards according to claim 1 based on PCH, it is characterised in that FLASH chip passes through SPI
Bus is connected with PCH.
5. the PCIE terminal device boards according to claim 1 based on PCH, it is characterised in that golden finger is PCIE X24
Golden finger.
6. the PCIE terminal device boards according to claim 1 based on PCH, it is characterised in that clock oscillator it is nominal
Frequency is 48M, 25M and 33K.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720131788.9U CN206421379U (en) | 2017-02-14 | 2017-02-14 | PCIE terminal device boards based on PCH |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720131788.9U CN206421379U (en) | 2017-02-14 | 2017-02-14 | PCIE terminal device boards based on PCH |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206421379U true CN206421379U (en) | 2017-08-18 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720131788.9U Active CN206421379U (en) | 2017-02-14 | 2017-02-14 | PCIE terminal device boards based on PCH |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108847947A (en) * | 2018-05-25 | 2018-11-20 | 郑州云海信息技术有限公司 | A kind of network interface card for supporting multiple network transmission rate |
-
2017
- 2017-02-14 CN CN201720131788.9U patent/CN206421379U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108847947A (en) * | 2018-05-25 | 2018-11-20 | 郑州云海信息技术有限公司 | A kind of network interface card for supporting multiple network transmission rate |
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