CN106199374A - Universal test platform and test method thereof - Google Patents
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- CN106199374A CN106199374A CN201510230525.9A CN201510230525A CN106199374A CN 106199374 A CN106199374 A CN 106199374A CN 201510230525 A CN201510230525 A CN 201510230525A CN 106199374 A CN106199374 A CN 106199374A
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- 238000012360 testing method Methods 0.000 title claims abstract description 101
- 238000010998 test method Methods 0.000 title claims abstract description 12
- 230000015654 memory Effects 0.000 claims abstract description 31
- 238000012544 monitoring process Methods 0.000 claims description 49
- 238000012545 processing Methods 0.000 claims description 15
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- 102000054766 genetic haplotypes Human genes 0.000 claims description 9
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- 241001269238 Data Species 0.000 description 6
- 238000006073 displacement reaction Methods 0.000 description 4
- 238000004804 winding Methods 0.000 description 4
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- PRPINYUDVPFIRX-UHFFFAOYSA-N 1-naphthaleneacetic acid Chemical compound C1=CC=C2C(CC(=O)O)=CC=CC2=C1 PRPINYUDVPFIRX-UHFFFAOYSA-N 0.000 description 1
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Abstract
The invention provides a universal test platform and a test method thereof, which comprise a host, a control board, a field-editable logic gate array board, a plurality of second connection ports, a plurality of socket boards and a plurality of NAND flash memories plugged into the socket boards. The control board is electrically connected to the host and has a plurality of first connection ports. The second connection ports are arranged on two opposite sides of the on-site editable logic gate array board in pairs, wherein each second connection port on one side of the on-site editable logic gate array board is electrically connected to the corresponding first connection port, and the two third connection ports of each socket board are electrically connected to any two adjacent second connection ports on the other side of the on-site editable logic gate array board. In addition, a testing method of the universal testing platform is provided. The universal test platform and the test method thereof provided by the invention can be used for testing controllers of different models, and are beneficial to improving the test efficiency of the controllers.
Description
Technical field
The invention relates to a kind of test platform and method of testing thereof, and general in particular to one
Type test platform and method of testing thereof.
Background technology
When current chip manufacturer tests before dispatching from the factory a certain class chip, can be special by building
Test circuit realize, but in R&D work simultaneously need to use many chip blocks tester come
Saying, it is the most loaded down with trivial details to build the method that special test circuit carries out chip detection one by one, and efficiency is the lowest, because of
This be badly in need of a kind of easy and simple to handle, the test device of the testing efficiency of chip can be improved.
Summary of the invention
The present invention provides a kind of universal test platform and method of testing thereof, can be used for testing different model
Controller, is favorably improved the testing efficiency of controller.
The present invention proposes a kind of universal test platform, including main frame, panel, field-programmable logic
Gate array strake, multiple second Port, multiple socket and multiple NAND quick-flash memory.Control
Plate is electrically connected to main frame, and has controller and at least one more than haplotype data synchronization of rate dynamic random is deposited
Access to memory and multiple first Port.Field-programmable logic gate array plate has processing unit.This
A little second Ports are arranged in pairs in the opposite sides of field-programmable logic gate array plate, and are positioned at scene
Each second Port of the wherein side of Programmadle logic gate array strake is electrically connected to corresponding first even
Connect port.Each socket has two the 3rd Ports, and electrical by corresponding aforementioned two the 3rd Ports
It is connected to be positioned at the wantonly two second adjacent Ports of the opposite side of field-programmable logic gate array plate.This
A little NAND quick-flash memory are plugged to these sockets respectively.
In one embodiment of this invention, above-mentioned panel also has the first adapter, and main frame is by the
A connector is electrically connected to panel.
In one embodiment of this invention, the first above-mentioned Port include multiple first test Port with
And the first signal acquisition Port.Second Port includes multiple second test Port and two second letters
Number obtain Port.First test Port and the wherein side being positioned at field-programmable logic gate array plate
Second test Port be correspondingly arranged, and the first signal acquisition Port be positioned at field-programmable logic
The secondary signal of the wherein side of gate array strake obtains Port and is correspondingly arranged.
In one embodiment of this invention, the first above-mentioned signal acquisition Port and more than at least one haplotype datas
Synchronization of rate dynamic random access memory is electrically connected with.
In one embodiment of this invention, the first above-mentioned Port also includes the first monitoring Port, the
Two Ports also include two second monitoring Ports.First monitors Port and is positioned at field-programmable logic
Second monitoring Port of the wherein side of gate array strake is correspondingly arranged.
In one embodiment of this invention, above-mentioned universal test platform also includes monitoring module, electrically
It is connected to be positioned at the second monitoring Port of the opposite side of field-programmable logic gate array plate, and passes through position
The second monitoring Port and the first monitoring in the wherein side of field-programmable logic gate array plate connect
Port and with panel be electrically connected with.
The present invention proposes the method for testing of a kind of universal test platform, comprises the following steps: provide multiple
Socket.Multiple NAND quick-flash memory are electrically connected to these sockets.It is electrically connected with these to insert
Seat board and field-programmable logic gate array plate.It is electrically connected with field-programmable logic gate array plate and control
Plate.It is electrically connected with panel and main frame.Main frame is utilized to send indication signal to panel.Pass through panel
On controller indication signal is converted to control signal.Control signal is write field-programmable gate
The processing unit of array board, and by processing unit by control signal dispensing to each socket, with test
These NAND quick-flash memory on each socket.
The present invention proposes the method for testing of a kind of universal test platform, further comprising the steps of.Electrically connect
Connect monitoring module and field-programmable logic gate array plate, and utilize processing unit control signal to be carried out point
Analysis, and the analysis result of control signal is shown in monitoring module.
The present invention proposes the method for testing of a kind of universal test platform, further comprising the steps of: to make each
The test result of the NAND quick-flash memory on socket is shown in monitoring module, be shown in monitoring
The analysis result of the control signal of module is compared.
Based on above-mentioned, the modular universal test platform of the present invention and method of testing thereof can make tester
Controller to be tested is electrically connected on panel, and by NAND quick-flash memory electricity to be tested
Property be connected on socket, and be electrically connected with panel and socket by field-programmable logic gate array plate
Plate, to test respectively the NAND quick-flash memory multiple to be tested on multiple sockets.Phase
The line configuring of correspondence need to be designed one by one for the controller of different model compared with existing test device, and
For controller and NAND quick-flash memory are arranged at the Technical Architecture of same circuit board, this enforcement
The modular universal test platform of example and method of testing thereof can be effectively improved the testing efficiency of controller,
And testing cost is greatly reduced.
For the features described above of the present invention and advantage can be become apparent, special embodiment below, and coordinate
Accompanying drawing is described in detail below.
Accompanying drawing explanation
Fig. 1 is the block chart of the test platform of one embodiment of the invention；
Fig. 2 is the part-structure side view of the test platform of Fig. 1；
Fig. 3 is the top view of the panel of Fig. 2；
Fig. 4 is the top view of the field-programmable logic gate array plate of Fig. 2；
Fig. 5 is the top view of the socket of Fig. 2；
Fig. 6 is the flow chart of the method for testing of the test platform of Fig. 1.
Description of reference numerals:
10,20: winding displacement；
100: universal test platform；
110: main frame；
120: panel；
121: controller；
122: many haplotype datas synchronization of rate dynamic random access memory；
123: the first Ports；
123a: the first test Port；
123b: the first signal acquisition Port；
123c: the first monitoring Port；
124: the first adapters；
130: field-programmable logic gate array plate；
131: processing unit；
140,141: the second Port；
140a, 141a: the second test Port；
140b, 141b: secondary signal obtains Port；
140c, 141c: the second monitoring Port；
150: socket；
151: the three Ports；
152: inserted area；
160:NAND flash memory；
170: monitoring module；
S1～S10: step.
Detailed description of the invention
Fig. 1 is the block chart of the test platform of one embodiment of the invention.Fig. 2 is the test platform of Fig. 1
Part-structure side view.Fig. 3 is the top view of the panel of Fig. 2, represents for clarity and is easy to explanation,
Fig. 2 schematically illustrates one of them socket being electrically connected to field-programmable logic gate array plate 130
150, and the secondary signal acquisition Port blocked by the second monitoring Port 141c is indicated with dotted line
141b.Refer to Fig. 1 to Fig. 3, in the present embodiment, universal test platform 100 include main frame 110,
Panel 120, field-programmable logic gate array plate 130, multiple second Port 140 and 141, many
Individual socket 150 and multiple NAND quick-flash memory 160, wherein main frame 110 can be desktop
Brain or notebook computer, and the first adapter 124 of panel 120, example can be connected to by winding displacement 10
Such as SATA or PCIe EBI.
Specifically, can to have controller haplotype data synchronization of rate more than 121, two dynamic for panel 120
Random access memory (DDRx SDRAM) 122 and multiple first Port 123, its middle controller
121 e.g. SSD controller, and respectively with many haplotype datas synchronization of rate dynamic random access memory
122, the first Port 123 and the first adapter 124 are electrically connected with.Therefore, main frame 110 can pass through
First adapter 124 is electrically connected to controller 121, deposits carrying out NAND Flash with controller 121
The control of reservoir 160 and access.On the other hand, many haplotype datas synchronization of rate dynamic random access memory
122 e.g. double data speed synchronous dynamic RAM, triples are dynamic according to synchronization of rate
Random access memory, quad data rate Synchronous Dynamic Random Access Memory or the data of higher multiple
Synchronization of rate dynamic random access memory, this is not any limitation as by the present invention.
Fig. 4 is the top view of the field-programmable logic gate array plate of Fig. 2.Refer to Fig. 2 to Fig. 4,
Field-programmable logic gate array plate 130 can be as the connection matchmaker of panel 120 with these sockets 150
Be situated between, be wherein arranged in pairs in field-programmable logic gate array plate 130 opposite sides these second even
Connect port 140 with 141 i.e. as its main connection interface.Specifically, the first Port 123 can wrap
Include multiple first test Port 123a and the first signal acquisition Port 123b, and the second Port
140 can include that multiple second test Port 140a and secondary signal obtain Port 140b, Qi Zhong
One test Port 123a and the second test Port 140a is correspondingly arranged, and the first signal acquisition connects
Port 123b and secondary signal obtain Port 140b and are correspondingly arranged.
Similarly, the second Port 141 may also comprise multiple second test Port 141a and the second letter
Number obtaining Port 141b, wherein the second test Port 140a with 141a is arranged in pairs and can compile in scene
Collect the opposite sides of logic gate array plate 130, and secondary signal acquisition Port 140b with 141b is paired
It is arranged at the opposite sides of field-programmable logic gate array plate 130.Herein, field-programmable gate
In array board 130, each second test Port 140a of this side of Control-oriented plate 120 can be plugged to
The first corresponding test Port 123a, and each secondary signal obtains Port 140b and can be plugged to correspondence
The first signal acquisition Port 123b, to be electrically connected with field-programmable logic gate array plate 130 and control
Making sheet 120.In unshowned embodiment, it is possible to connected by winding displacement or other suitable connecting lines
Each second test Port 140a with corresponding first test Port 123a and connect each second
Signal acquisition Port 140b and the first corresponding signal acquisition Port 123b, the present invention is to this not
It is any limitation as.
Fig. 5 is the top view of the socket of Fig. 2.Refer to Fig. 1, Fig. 2 and Fig. 5, each socket
150 can have two the 3rd Ports 151 and a multiple inserted area (or claiming socket) 152, wherein these
NAND quick-flash memory 160 is plugged on these inserted area 152, and each socket 150 respectively
NAND quick-flash memory 160 is all positioned at the same side of the 3rd Port 151.Owing to NAND Flash is deposited
The inserted area (or claiming socket) 152 that reservoir 160 is assembled on socket 150 the most pluggablely, therefore
After the tested end of NAND quick-flash memory 160, it can be easily from inserted area (or claiming socket) 152
Pull out, it is not necessary to tip-off there will not be the problem of colloid residual and produces, therefore can prevent damaging NAND Flash and deposit
The structure of reservoir 160.Specifically, each socket 150 is by two corresponding the 3rd Ports
Wantonly the two of 151 these sides being plugged to panel 120 dorsad in field-programmable logic gate array plate 130
Adjacent second test Port 141a so that controller 121 can by the first test Port 123a,
Second test Port 140a Yu 141a and the 3rd Port 151 are electrically connected to each socket 150
On NAND quick-flash memory 160.Further, the control signal that controller 121 is sent can be by the
One test Port 123a and the second test Port 140a is sent to field-programmable logic gate array plate
Processing unit 131 on 130, to carry out signal analysis.
On the other hand, the first signal acquisition Port 123b can with each many haplotype datas synchronization of rate dynamically with
Machine access memorizer 122 is electrically connected with, and uses each many haplotype datas synchronization of rate dynamic randon access of acquisition
The clock signal of memorizer 122.In the present embodiment, the first Port 123 also includes that the first monitoring is even
Meeting port 123c, the second Port 140 also includes second arranged corresponding to the first monitoring Port 123c
Monitoring Port 140c, similarly, the second Port 141 also includes corresponding to the second monitoring Port 140c
And the second monitoring Port 141c arranged.Due to the first monitoring Port 123c and field-programmable logic
In gate array strake 130, the second monitoring Port 140c of Control-oriented plate 120 is correspondingly arranged, and is therefore inciting somebody to action
After second monitoring Port 140c is plugged to the first monitoring Port 123c, the first monitoring Port 123c
The second monitoring Port 141c can be electrically connected to by the second monitoring Port 140c, and by second
Monitoring Port 141c is electrically connected to monitoring module 170.Herein, the second monitoring Port 141c and prison
Electric connection between control module 170 e.g. passes through winding displacement 20 to reach.In other words, controller
121 are sent to the control signal of the processing unit 131 on field-programmable logic gate array plate 130 through dividing
After analysis, its analysis result can be sent to monitoring module 170 by the second monitoring Port 141c and show
Thereon.Additionally, the control signal that sent of controller 121 also can transcription to processing unit 131, then
By processing unit 131 quickly move through the second test Port 141a dispensing to each socket 150 (as
Shown in Fig. 1 Yu Fig. 2), so that the NAND quick-flash memory 160 on each socket 150 is surveyed
Examination.Test result after testing NAND quick-flash memory 160 can first be back to field-programmable
Logic gate array plate 130, then be sent to monitoring module 170 by the second monitoring Port 141c and show
Thereon.Therefore, tester can simultaneously observe, at monitoring module 170, the control that controller 121 is sent
The analysis result of signal processed and the test result of NAND quick-flash memory 160, in order to compare
And analyze the accuracy of firmware design, or carry out when necessary except wrong action.
In short, the design of modular universal test platform 100, tester can be made to be tested
Controller 121 is electrically connected on panel 120, and by NAND quick-flash memory 160 to be tested
It is electrically connected on socket 150, and is electrically connected with control by field-programmable logic gate array plate 130
Making sheet 120 and socket 150, with to the NAND Flash multiple to be tested on multiple sockets 150
Memorizer 160 is tested respectively.Need to be for the controller of different model compared to existing test device
Design the line configuring of correspondence one by one, and controller and NAND quick-flash memory are arranged at same electricity
For the Technical Architecture of road plate, the modular universal test platform 100 of the present embodiment can be effectively improved
The testing efficiency of controller 121, and testing cost is greatly reduced.
Fig. 6 is the flow chart of the method for testing of the test platform of Fig. 1.Refer to Fig. 6 and coordinate above-mentioned attached
Figure, the method for testing of universal test platform 100 need to first carry out step S1 and S2, it is provided that socket 150,
And multiple NAND quick-flash memory 160 are respectively and electrically connected to socket 150.Then, walk
Rapid S3, is electrically connected with socket 150 and field-programmable logic gate array plate 130.Then, walk
Rapid S4, is electrically connected with field-programmable logic gate array plate 130 and panel 120.Then, walk
Rapid S5, is electrically connected with panel 120 and main frame 110.Then, carry out step S6, be electrically connected with monitoring
Module 170 and field-programmable logic gate array plate 130.Then, carry out step S7, utilize main frame 110
Send indication signal to the controller 121 of panel 120, and by controller 121, indication signal is turned
It is changed to control signal.Then, carry out step S8, control signal is write field-programmable logic gate array
The processing unit 131 of plate 130, and by processing unit 131, control signal is sent to each socket
150, to test the NAND quick-flash memory 160 on each socket 150.Carrying out step S8
Meanwhile, carry out step S9, utilize processing unit 131 that control signal is analyzed, and by control signal
Analysis result be shown in monitoring module 170.Finally, in step slo, each socket 150 is made
On the test result of NAND quick-flash memory 160 be shown in monitoring module 170, be shown in prison
The analysis result of the control signal of control module 170 is compared.
In sum, modular universal test platform and the method for testing thereof of the present invention can make tester
Controller to be tested is electrically connected on panel, and by NAND quick-flash memory electricity to be tested
Property be connected on socket, and be electrically connected with panel and socket by field-programmable logic gate array plate
Plate, to test respectively the NAND quick-flash memory multiple to be tested on multiple sockets.Phase
The line configuring of correspondence need to be designed one by one for the controller of different model compared with existing test device, and
For controller and NAND quick-flash memory are arranged at the Technical Architecture of same circuit board, this enforcement
The modular universal test platform of example and method of testing thereof can be effectively improved the testing efficiency of controller,
And testing cost is greatly reduced.
Last it is noted that various embodiments above is only in order to illustrate technical scheme, rather than right
It limits；Although the present invention being described in detail with reference to foregoing embodiments, this area common
Skilled artisans appreciate that the technical scheme described in foregoing embodiments still can be modified by it,
Or the most some or all of technical characteristic is carried out equivalent；And these amendments or replacement, and
The essence not making appropriate technical solution departs from the scope of various embodiments of the present invention technical scheme.
Claims (9)
1. a universal test platform, it is characterised in that including:
Main frame；
Panel, is electrically connected to described main frame, and described panel has controller and more than at least one times
Data rate synchronous dynamic random access memory and multiple first Port；
Field-programmable logic gate array plate, has processing unit；
Multiple second Ports, are arranged in pairs in the opposite sides of described field-programmable logic gate array plate,
And each described second Port being positioned at the wherein side of described field-programmable logic gate array plate electrically connects
It is connected to described first Port of correspondence；And
Multiple sockets, have two the 3rd Ports, and each described socket is by corresponding described two the 3rd
Port is electrically connected to be positioned at the wantonly two adjacent of the opposite side of described field-programmable logic gate array plate
Those second Ports；And
Multiple NAND quick-flash memory, are plugged to those sockets respectively.
Universal test platform the most according to claim 1, it is characterised in that described panel is also
Having the first adapter, described main frame is electrically connected to described panel by described first adapter.
Universal test platform the most according to claim 1, it is characterised in that those first connections
Port includes multiple first test Port and the first signal acquisition Port, and those second Ports include
Multiple second test Ports and two secondary signals obtain Port, those first test Port and positions
Those the second test Port correspondences in the wherein side of described field-programmable logic gate array plate set
Put, and described first signal acquisition Port be positioned at described field-programmable logic gate array plate wherein
The described secondary signal of side obtains Port and is correspondingly arranged.
Universal test platform the most according to claim 3, it is characterised in that described first signal
Obtain Port to be electrically connected with described at least one more than haplotype data synchronization of rate dynamic random access memory.
Universal test platform the most according to claim 3, it is characterised in that those first connections
Port also includes the first monitoring Port, and those second Ports also include two second monitoring Ports, described
First monitoring Port and described the second of the wherein side being positioned at described field-programmable logic gate array plate
Monitoring Port is correspondingly arranged.
Universal test platform the most according to claim 5, it is characterised in that also include:
Monitoring module, is electrically connected to be positioned at the institute of the opposite side of described field-programmable logic gate array plate
State the second monitoring Port, and by being positioned at the wherein side of described field-programmable logic gate array plate
Described second monitoring Port and described first monitors Port and is electrically connected with described panel.
7. the method for testing of a universal test platform, it is characterised in that including:
Multiple socket is provided；
Multiple NAND quick-flash memory are respectively and electrically connected to those sockets；
It is electrically connected with those sockets and field-programmable logic gate array plate；
It is electrically connected with described field-programmable logic gate array plate and panel；
It is electrically connected with described panel and described main frame；
Described main frame is utilized to send indication signal to described panel；
By the controller on described panel, described indication signal is converted to control signal；And
Described control signal is write the processing unit of described field-programmable logic gate array plate, and passes through
Described control signal is sent to each described socket by described processing unit, to test on each described socket
Those NAND quick-flash memory.
The method of testing of universal test platform the most according to claim 7, it is characterised in that also
Including:
It is electrically connected with monitoring module and described field-programmable logic gate array plate, and utilizes described process single
Described control signal is analyzed by unit, and the analysis result of described control signal is shown in described monitoring
Module.
The method of testing of universal test platform the most according to claim 8, it is characterised in that also
Including:
The test result making those NAND quick-flash memory on each described socket is shown in described monitoring
Module, compares with the analysis result with the control signal being shown in described monitoring module.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW104105859A TWI510798B (en) | 2015-02-24 | 2015-02-24 | Universal test platform and test method thereof |
| TW104105859 | 2015-02-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106199374A true CN106199374A (en) | 2016-12-07 |
Family
ID=55407752
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510230525.9A Pending CN106199374A (en) | 2015-02-24 | 2015-05-08 | Universal test platform and test method thereof |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP6033913B2 (en) |
| CN (1) | CN106199374A (en) |
| TW (1) | TWI510798B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI510798B (en) * | 2015-02-24 | 2015-12-01 | Powertech Technology Inc | Universal test platform and test method thereof |
| CN109323716B (en) * | 2018-11-01 | 2023-12-29 | 上海电气集团自动化工程有限公司 | Detection and debugging device for serial absolute encoder of servo driving system |
| CN112509631A (en) * | 2020-12-25 | 2021-03-16 | 东莞记忆存储科技有限公司 | Batch testing system and method for quality of storage particles, computer equipment and storage medium |
| US11698408B2 (en) | 2021-08-26 | 2023-07-11 | Western Digital Technologies, Inc. | Testing apparatus for data storage devices |
| US11828793B2 (en) | 2021-08-26 | 2023-11-28 | Western Digital Technologies, Inc. | Testing apparatus for temperature testing of electronic devices |
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| JPH08146080A (en) * | 1994-11-28 | 1996-06-07 | Sumitomo Electric Ind Ltd | Burn-in board |
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| TW200828325A (en) * | 2006-12-18 | 2008-07-01 | Golden Emperor Internat Ltd | System and method for testing memories |
| CN102201267A (en) * | 2010-03-26 | 2011-09-28 | 上海摩波彼克半导体有限公司 | Platform system for realizing circuit verification of Nandflash flash memory controller based on FPGA (Field Programmable Gate Array) and method thereof |
| TWI469151B (en) * | 2011-08-26 | 2015-01-11 | Powertech Technology Inc | Testing interface board specially for dram memory packages |
| CN102332311B (en) * | 2011-10-18 | 2013-10-02 | 中国航天科技集团公司第五研究院第五一〇研究所 | FPGA (Field Programmable Gate Array)-based single event effect test method for NAND FLASH device |
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2015
- 2015-02-24 TW TW104105859A patent/TWI510798B/en not_active IP Right Cessation
- 2015-04-24 JP JP2015088847A patent/JP6033913B2/en not_active Expired - Fee Related
- 2015-05-08 CN CN201510230525.9A patent/CN106199374A/en active Pending
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| CN1609862A (en) * | 2004-11-19 | 2005-04-27 | 华南理工大学 | IP nuclear simulation confirmation platform based on PCI bus and proving method thereof |
| CN101334448A (en) * | 2008-05-23 | 2008-12-31 | 深圳市同洲电子股份有限公司 | Test platform and method for testing PC board |
| TW201126528A (en) * | 2010-01-20 | 2011-08-01 | King Yuan Electronics Co Ltd | Memory test equipment with extensible sample memory |
| CN103809106A (en) * | 2012-11-15 | 2014-05-21 | 佛山市顺德区顺达电脑厂有限公司 | Automatic test device and method |
| JP2016156798A (en) * | 2015-02-24 | 2016-09-01 | 力成科技股▲分▼有限公司 | Universal testing platform and testing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2016156798A (en) | 2016-09-01 |
| TW201631325A (en) | 2016-09-01 |
| TWI510798B (en) | 2015-12-01 |
| JP6033913B2 (en) | 2016-11-30 |
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Application publication date: 20161207 |
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