CN102201267A - Platform system for realizing circuit verification of Nandflash flash memory controller based on FPGA (Field Programmable Gate Array) and method thereof - Google Patents
Platform system for realizing circuit verification of Nandflash flash memory controller based on FPGA (Field Programmable Gate Array) and method thereof Download PDFInfo
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Abstract
The invention relates to a platform system for realizing circuit verification of a Nandflash flash memory controller based on an FPGA (Field Programmable Gate Array). An FPGA debugging plate is provided with an SOC (System on Chip) chip, an FPGA chip and a plurality of Nandflash signal interface modules, the FPGA chip is provided with a bus switching circuit module and an Nandflash controller circuit module, a computer to be tested is connected with each Nandflash signal interface module through a test simulator, the SOC chip, the bus switching circuit module and the Nandflash controller circuit module, and each Nandflash signal interface module is connected with a corresponding test board. The invention further relates to a method for realizing the circuit verification of the Nandflash flash memory controller through the platform system. By adopting the platform system for realizing the circuit verification of the Nandflash flash memory controller based on the FPGA (Field Programmable Gate Array) and the method thereof, disclosed by the invention, the degree of automation is extremely high, the period of research and development is shortened, the cost of research and development is reduced, the test efficiency is high, the use is convenient and fast, the working performance is stable and reliable and the application range is wider.
Description
Technical field
The present invention relates to integrated circuit fields, particularly digital integrated circuit verification technique field specifically is meant a kind of plateform system and method that realizes Nandflash flash controller Circuit verification based on FPGA.
Background technology
FPGA (Field Programmable Gate Array, field programmable gate array) checking is requisite important flow process in the Design of Digital Integrated Circuit process.
The key step of FPGA checking has:
(1) design input: promptly utilize HDL (Hardware Description Language, hardware description language) input tool, schematic diagram input tool or state machine input tool etc. that the circuit that will design is described out.
(2) comprehensive and placement-and-routing, complex optimum is an annexation (net table) of the HDL language being translated into the most basic AND, and (constraint condition) optimizes the gate-level logic connection that is generated as requested, files such as output edf and edn are led to the software of FPGA producer and are realized and placement-and-routing.
Realization and placement-and-routing's instrument that placement-and-routing just is to use FPGA manufacturer to provide according to the model of selected chip, carry out the actual connection and the mapping of chip internal functional unit.
(3) generation and download BIT or PROM file carry out the debugging of plate level.
After placement-and-routing finishes, can generate the BIT or the PROM file that have circuit function, the programming instrument that provides by FPGA manufacturer, in fpga chip, fpga chip just can have been realized the circuit function that will design like this with BIT or the programming of PROM file.
The present invention is primarily aimed at the Nandflash controller, below Nandflash and Nandflash controller is described in detail.
Nandflash (flash memory) is the popular storage medium of present industry, and the Nandflash memory cell area is little, and its die area is also very little.The Nandflash program speed is fast, the erasing time short, and supporting rate surpasses the lasting write operation of 5Mbps, and its block erase time is as short as 2ms.Obviously, Nandflash has absolute predominance aspect program speed, erasing time.Based on above-mentioned some advantage, Nandflash is suitable for storing heap file, so Nandflash almost is used to all erasable storage cards.
Along with becoming more and more popular of Nandflash, increasing manufacturer begins to produce the Nandflash flash chip, Samsung, Micron Technology and Toshiba etc. all are the Nandflash flash chip manufacturers of industry main flow, various Nandflash flash chip models in the market are more and more, otherness between the various flash chips is also increasing, and this just has higher requirement to the compatibility of Nandflash controller.
In digital SOC (system on chip, SOC (system on a chip)) chip architecture commonly used, our regular meeting's use Nandflash controller is responsible for the Nandflash flash memory communication with the chip outside.As the bridge between SOC chip inner treater and the Nandflash flash memory, processor is realized operations such as Nandflash programme, wipes by sending instruction to the Nandflash controller.Simultaneously, the Nandflash flash memory is given the Nandfash controller by returning corresponding status data, informs processor corresponding flash memory state.So the Nandfash controller plays irreplaceable effect in digital SOC chip and Nandflash flash memory communication process.Nandfash flash interface signal has 8 or 16 director data signal I/O and 6 control signals: chip start signal CEn, write enable signal WEn, read enable signal REn, instruction latch enable signal CLE, address latch enable signal ALE, ready/busy signal R/Bn.The Nandflash controller resets, reads and writes data in the Nandflash flash chip, reads Nandflash flash chip state and chip identifier, wipes data in the Nandflash flash chip, data in the Nandflash flash chip is carried out operations such as ECC (Error Check Correct) algorithm verification the Nandflash flash memory by above-mentioned signal.
As indicated above, the complicated operation of Nandflash controller, the existing Nandflash flash chip in market is of a great variety simultaneously, otherness is also increasing, and existing Nandflash controller FPGA proof scheme more and more is difficult to satisfy tester's test request.
Nandflash controller verification scheme of the prior art can't fully be verified the compatibility of Nandflash controller to various Nandflash flash chips; Cause testing efficiency low because Nandflash chip to be measured is more; And can't verify that fully test coverage is low to the various logic functions of Nandflash controller circuitry; Need great amount of manpower to participate in simultaneously, the test automation degree is lower; Can't reduce and avoid the defective of Nandflahs controller, thereby reduce the compatibility of Nandflash controller, make the R﹠D cycle prolong, R﹠D costs improve greatly.
So, how to design a kind of qualified FPGA proof scheme at the Nandflash controller circuitry, just become a challenge in present digital integrated circuit validation test field.
Summary of the invention
The objective of the invention is to have overcome above-mentioned shortcoming of the prior art, provide a kind of can be to the various functions of Nandflash controller and compatible fully verify, automaticity height, testing efficiency height, test coverage height, convenient to use, stable and reliable working performance, range of application realize Nandflash flash controller Circuit verification comparatively widely based on FPGA plateform system and method.
In order to realize above-mentioned purpose, plateform system and the method based on FPGA realization Nandflash flash controller Circuit verification of the present invention is as follows:
Should realize the plateform system of Nandflash flash controller Circuit verification based on FPGA, comprise test computer and the test board that carries the Nandflash flash chip, its principal feature is, also comprise tester simulator and FPGA debugging plate in the described plateform system, carry the SOC chip on the described FPGA debugging plate, fpga chip and several Nandflash Signal interface modules, be provided with bus switching circuit module and Nandflash controller circuitry module in the described fpga chip, described test computer is successively by described tester simulator, the SOC chip, the bus switching circuit module is connected with described each Nandflash Signal interface module respectively with Nandflash controller circuitry module, and each Nandflash Signal interface module is connected with corresponding test board.
Should be the SOC chip that is built-in with arm processor based on the SOC chip in the plateform system of FPGA realization Nandflash flash controller Circuit verification.
Should be the SOC chip of built-in ARM926EJ_S processor based on the SOC chip in the plateform system of FPGA realization Nandflash flash controller Circuit verification.
Should be that ARM changes FPGA bus circuit module based on the bus switching circuit module in the plateform system of FPGA realization Nandflash flash controller Circuit verification.
Should be the ARM emulator based on the tester simulator in the plateform system of FPGA realization Nandflash flash controller Circuit verification, and this ARM emulator be compiled into the discernible assembly instruction of described arm processor with the test code on the test computer.
Should be the test code of C language compilation based on the test code in the plateform system of FPGA realization Nandflash flash controller Circuit verification.
Should be vitex-4 Series FPGA chip based on the fpga chip in the plateform system of FPGA realization Nandflash flash controller Circuit verification.
Should be Nandflash signaling interface first slot based on the Nandflash Signal interface module in the plateform system of FPGA realization Nandflash flash controller Circuit verification, described test board is provided with Nandflash signaling interface second slot with the corresponding coupling of this Nandflash signaling interface first slot, described Nandflash signaling interface second slot is connected with described Nandflash flash chip, and the grafting that is coupled of Nandflash signaling interface first slot and corresponding Nandflash signaling interface second slot.
Should realize that Nandflash signaling interface second slot in the plateform system of Nandflash flash controller Circuit verification be arranged on the face that carries the Nandflash flash chip of test board or on the opposite face based on FPGA.
Should be connected with described tester simulator by the USB connecting line based on the test computer in the plateform system of FPGA realization Nandflash flash controller Circuit verification.
Should be connected with described SOC chip by the emulator connecting line based on the tester simulator in the plateform system of FPGA realization Nandflash flash controller Circuit verification.
This utilizes above-mentioned plateform system to realize the method for Nandflash flash controller Circuit verification, and its principal feature is that described method may further comprise the steps:
(1) described test computer is connected with described tester simulator, SOC chip successively, simultaneously described each Nandflash Signal interface module is connected with corresponding test board;
(2) described test computer, tester simulator and FPGA debugging plate are powered on simultaneously;
(3) generate the recordable paper of realizing bus switching circuit module and Nandflash controller circuitry module, and this recordable paper programming is arrived in the described fpga chip;
(4) described test computer is tested described Nandflash controller circuitry module by the test code of writing in advance.
Generation in the method for this realization Nandflash flash controller Circuit verification realizes the recordable paper of bus switching circuit module and Nandflash controller circuitry module and this recordable paper programming is arrived in the described fpga chip, may further comprise the steps:
(11) the FPGA instrument that uses fpga chip manufacturer to be provided will realize that the HDL language codes of bus switching circuit module and Nandflash controller circuitry functions of modules is converted to the BIT/PROM file;
(12) in the fpga chip of the FPGA programming instrument programming that is provided by fpga chip manufacturer to the FPGA debugging plate.
Test computer in the method for this realization Nandflash flash controller Circuit verification is tested described Nandflash controller circuitry module by the test code of writing in advance, may further comprise the steps:
(21) described test computer produces corresponding test instruction and delivers to described tester simulator according to described test code;
(22) described tester simulator is compiled into the assembly instruction that described SOC chip can be carried out with described test instruction, and delivers to described SOC chip;
(23) described bus switching circuit module of described SOC chip controls and Nandflash controller circuitry module are carried out corresponding test processes.
Described bus switching circuit module of SOC chip controls and Nandflash controller circuitry module in the method for this realization Nandflash flash controller Circuit verification are carried out corresponding test processes, may further comprise the steps:
(31) the circuit correctness and the internal circuit basic function of described fpga chip inside are verified, and the corresponding checking of record result;
(32) the Nandflash controller circuitry module in the described fpga chip of control resets and the read states operational testing to the Nandflash flash chip, and writes down corresponding test result;
(33) the Nandflash controller circuitry module in the described fpga chip of control is read the indications operational testing to the Nandflash flash chip, and writes down corresponding test result;
(34) the Nandflash controller circuitry module of control in the described fpga chip to the Nandflash flash chip wipe, write data and read data operational testing, and write down corresponding test result;
(35) the Nandflash controller circuitry module in the described fpga chip of control is carried out the test of ECC verification operation to the Nandflash flash chip, and writes down corresponding test result.
The plateform system and the method based on FPGA realization Nandflash flash controller Circuit verification of this invention have been adopted, because wherein whole test process is fully by the control of the test code in the test computer, automaticity is high, need not manpower fully participates in, thereby shortened the R﹠D cycle greatly, reduced R﹠D costs; Because the C language that test code adopted is very flexible, just can fully verify simultaneously all functions of Nandflash controller; Integrated a plurality of Nandflash interface slots on the test platform of the present invention in addition, the C language can be verified polylith Nandflash chip simultaneously, fully verified the compatibility of Nandflash controller to various Nandflash flash chips, and do not cause testing efficiency low because Nandflash chip to be measured is more, thereby obtained high as far as possible testing efficiency, not only convenient to use, and stable and reliable working performance, range of application is comparatively extensive.
Description of drawings
Figure l is a structural representation of realizing the plateform system of Nandflash flash controller Circuit verification based on FPGA of the present invention.
Fig. 2 is a process flow diagram of realizing the method for Nandflash flash controller Circuit verification based on FPGA of the present invention.
Embodiment
In order more to be expressly understood technology contents of the present invention, describe in detail especially exemplified by following examples.
See also shown in Figure 1, should realize the plateform system of Nandflash flash controller Circuit verification based on FPGA, comprise test computer and the test board that carries the Nandflash flash chip, wherein, also comprise tester simulator and FPGA debugging plate in the described plateform system, carry the SOC chip on the described FPGA debugging plate, fpga chip and several Nandflash Signal interface modules, be provided with bus switching circuit module and Nandflash controller circuitry module in the described fpga chip, described test computer is successively by described tester simulator, the SOC chip, the bus switching circuit module is connected with described each Nandflash Signal interface module respectively with Nandflash controller circuitry module, and each Nandflash Signal interface module is connected with corresponding test board.
Wherein, described SOC chip is the SOC chip that is built-in with arm processor, the SOC chip that this SOC chip is built-in ARM926EJ_S processor; Described bus switching circuit module is that ARM changes FPGA bus circuit module; Described tester simulator is the ARM emulator, and this ARM emulator is compiled into the discernible assembly instruction of described arm processor with the test code on the test computer, and this test code is the test code of C language compilation.
Simultaneously, described fpga chip is a vitex-4 Series FPGA chip, described Nandflash Signal interface module is Nandflash signaling interface first slot, described test board is provided with Nandflash signaling interface second slot with the corresponding coupling of this Nandflash signaling interface first slot, described Nandflash signaling interface second slot is connected with described Nandflash flash chip, and the grafting that is coupled of Nandfash signaling interface first slot and corresponding Nandflash signaling interface second slot; Described Nandflash signaling interface second slot is arranged on the face that carries the Nandflash flash chip of test board or on the opposite face; Described test computer is connected with described tester simulator by the USB connecting line, and this tester simulator is connected with described SOC chip by the emulator connecting line.
See also shown in Figure 2ly again, this utilizes above-mentioned plateform system to realize the method for Nandflash flash controller Circuit verification, and wherein, described method may further comprise the steps:
(1) described test computer is connected with described tester simulator, SOC chip successively, simultaneously described each Nandflash Signal interface module is connected with corresponding test board;
(2) described test computer, tester simulator and FPGA debugging plate are powered on simultaneously;
(3) generate the recordable paper of realizing bus switching circuit module and Nandflash controller circuitry module, and this recordable paper programming arrived in the described fpga chip, may further comprise the steps:
(a) the FPGA instrument that uses fpga chip manufacturer to be provided will be realized bus switching circuit module and Nandflash
The HDL language codes of controller circuitry functions of modules is converted to the BIT/PROM file;
(b) in the fpga chip of the FPGA programming instrument programming that is provided by fpga chip manufacturer to the FPGA debugging plate;
(4) described test computer is tested described Nandflash controller circuitry module by the test code of writing in advance, may further comprise the steps:
(a) described test computer produces corresponding test instruction and delivers to described tester simulator according to described test code;
(b) described tester simulator is compiled into the assembly instruction that described SOC chip can be carried out with described test instruction, and delivers to described SOC chip;
(c) described bus switching circuit module of described SOC chip controls and Nandflash controller circuitry module are carried out corresponding test processes, may further comprise the steps:
(i) the circuit correctness and the internal circuit basic function of described fpga chip inside are verified, and the corresponding checking of record result;
The Nandflash controller circuitry module of (ii) controlling in the described fpga chip resets and the read states operational testing to the Nandflash flash chip, and writes down corresponding test result;
The Nandflash controller circuitry module of (iii) controlling in the described fpga chip is read the indications operational testing to the Nandfash flash chip, and writes down corresponding test result;
(iv) control in the described fpga chip Nandflash controller circuitry module to the Nandflash flash chip wipe, write data and read data operational testing, and write down corresponding test result;
(the Nandflash controller circuitry module of v) controlling in the described fpga chip is carried out the test of ECC verification operation to the Nandflash flash chip, and writes down corresponding test result.
In the middle of reality is used, test platform of the present invention comprises that the PC that is used to write C language testing program, the ARM emulator that is used to connect PC and arm processor chip, one have the SOC chip of arm processor and the FPGA debugging plate of fpga chip and several Nandflash signaling interface slots, the some test platelets that comprise the Nandflash of different vendor flash chip.
PC computer in this verification platform can be any computer that can write the C language.
ARM emulator in this verification platform can be the ARM emulator of any a support arm processor debug function, and this emulator can be compiled into the C language of PC side the discernible assembly instruction of arm processor.
FPGA debugging plate in this verification platform comprises the SOC chip that has the disposable type arm processor that any company produces, such as Samsung produces ARM926EJ_S processor SOC chip.This FPGA debugging plate also comprises the fpga chip of any company production such as the vitex-4 Series FPGA chip of Xilinx company, and the chip internal programming has ARM to change FPGA bus circuit and Nandflash controller circuitry.This FPGA debugging plate also has the slot of several Nandflash flash interface signals.
Nandflash chip testing platelet front in this verification platform is welded with the Nandflash flash chip that any company produces, and the back side has Nandflash flash interface signal slot.This flash chip can be Micron (Micron Technology) or the Nandflash flash chip produced of Toshiba (Toshiba) as shown in Figure 1,
As shown in Figure 1, the PC in this FPGA hardware platform links to each other by a USB with the ARM emulator, and the ARM emulator links to each other by special-purpose emulator connecting line with the arm processor chip that FPGA debugs on the plate.Arm processor chip on the FPGA debugging plate changes the interior Nandflash controller of FPGA bus circuit control fpga chip by the ARM of fpga chip inside.The Nandflash flash memory of polylith different model test platelet is inserted in the slot of FPGA debugging plate by back slot, and the Nandflash flash chip of testing like this on the platelet just can be undertaken by the Nandflash controller circuitry in I/O data command signal mentioned above and 6 control signals and the fpga chip alternately.
See also shown in Figure 2ly again, FPGA proof scheme of the present invention roughly comprises following implementation step:
The first step is built hardware platform.The device that the present invention program is required correctly connects by method mentioned above.
Second step, generation, programming bit file.Generation can realize that ARM changes the bit file of FPGA bus circuit and Nandflash controller circuitry, and in the fpga chip of programming to the FPGA debugging plate.
In the 3rd step, write C language testing program.Write C language testing program in the PC side at the Nandflash controller.
In the 4th step, test platform moves automatically.C programmer is through the compiling of ARM emulator, convert the discernible assembly instruction of arm processor to, ARM by fpga chip inside changes the FPGA bus, the interior Nandflash controller circuitry of control arm processor and fpga chip carries out alternately, make the Nandflash controller to polylith Nandflash flash chip read and write data simultaneously, operations such as obliterated data, reading state and the verification of ECC algorithm.Show test results behind the Automatic Program end of run.
Checking flow process of the present invention mainly comprises four steps in specific implementation process:
The first step is built hardware platform.
According to shown in Figure 2, each device is linked to each other.PC is linked to each other with a USB with the ARM emulator.The ARM emulator is linked to each other by the emulator connecting line with the ARM SOC chip that FPGA debugs on the plate.The polylith Nandflash chip testing platelet of the needs tests slot by the back side is inserted on the slot of FPGA debugging plate.PC, ARM emulator and FPGA power on simultaneously.
Second step, generation, programming bit file.
According to background content, the FPGA instrument that uses FPGA manufacturer to provide, can realize that ARM changes the HDL language generation bit file of FPGA bus functionality and Nandflash controller circuitry, and in the fpga chip of programming to the FPGA debugging plate, for example the ISE Software tool of Xilinx company.
In the 3rd step, write C language testing program.Write C language testing program in the PC side at Nandflash controller all functions.
In the 4th step, test platform moves automatically.After C language testing programming is finished, be compiled into ARM assembly instruction (such as JEDI emulator of MICETEK company) by the ARM emulator, then the emulator connecting line by special use pour into ARM SOC chip on the FPGA debugging plate in, arm processor will automatically perform the ARM assembly instruction that the C test procedure converts to like this.The ARM of arm processor by fpga chip inside changes the FPGA bus circuit, control Nandflash controller simultaneously to polylith Nandflash flash chip read and write data simultaneously, various test operations such as obliterated data, reading state and the verification of ECC algorithm.Program run shows test results after finishing automatically.
C language testing program mentioned above is the present invention program's a marrow part, because the C language is characteristic easily flexibly, use the tester of this proof scheme to write test case flexibly, all functions of Nandflash controller are fully verified at the concrete function of Nandflash controller and Nandflash flash memory.
Now this test procedure is elaborated, supposes to have inserted Micron and two tests of Toshiba platelet on the slot of FPGA debugging plate, as follows at the master routine of the test code of these two platelets:
int?main(void)
{
volatile_u32?FPGA_WORK_FLAG＝0；
volatile_u32?status[8]＝{0}；
FPGA_WORK_FLAG＝FPGA_Work_Check()；
status[0]＝NANDCTRL_CASE0()；//Micron?reset?and?read?status?test
status[1]＝NANDCTRL_CASE1()；//Micron?read?id?test
status[2]＝NANDCTRL_CASE2()；//Micron?erase，write?and?read?test
status[3]＝NANDCTRL_CASE3()；//Micron?ecc?funciton?test
status[4]＝NANDCTRL_CASE8()；//Toshiba?reset?and?read?status?test
status[5]＝NANDCTRL_CASE9()；//Toshiba?read?id?test
status[6]＝NANDCTRL_CASE10()；//Toshiba?erase，write?and?read?test
status[7]＝NANDCTRL_CASE11()；//Toshiba?ecc?funciton?test
}
As mentioned, comprise 8 test cases in the principal function of this test procedure, represent the Nandflash controller circuitry that two every functions of Nandflash flash chip of Micron and Toshiba are tested respectively.Now above code is elaborated:
(1)FPGA_WORK_FLGA＝FPGA_Work_Check()；
This row test code is verified the circuit correctness of fpga chip inside.Before using fpga chip that the Nandflash flash memory is tested, must guarantee that the fpga chip internal circuit is in the main true, this row test code is tested fpga chip internal circuit basic function, if variable FPGA_WORK_FLGA equals 1, illustrate that fpga chip internal circuit basic function is correct, otherwise fpga chip work is incorrect.
(2)status[0]＝NANDCTRL_CASE0()；//Micron?reset?and?read?status?test
Nandflash controller circuitry in this row test case control fpga chip resets to Micron Nandflash flash chip and the read states operation.This test case is by variable stateu[0] show test results, if status[0] equal 1, illustrate that this test case passes through, the Nandflash controller circuitry in the fpga chip reset and the read states function correct; If equal 0, test crash is described, the Nandflash controller circuitry reset and the read states function has problem.
(3)status[1]＝NANDCTRL_CASE1()；//Micron?read?id?test
Nandflash controller circuitry in this row test case control fpga chip is read the indications operation to Micron Nandflash flash chip.This test case is by variable stateu[1] show test results, if status[1] equal 1, illustrate that this test case passes through, the Nandflash controller circuitry in the fpga chip to read the indications function correct; If equal 0, test crash is described, the Nandflash controller circuitry is read the indications function problem.
(4)status[2]＝NANDCTRL_CASE2()；//Micron?erase，write?and?read?test
Nandflash controller circuitry in this row test case control fpga chip to the MicronNandflash flash chip wipe, write data and read data operation.This test case is by variable stateu[2] show the last test result, if status[2] and equal 1, illustrate that this test case passes through, the function of wiping, read and write data of the Nandflash controller circuitry in the fpga chip is correct; If equal 0, test crash is described, the Nandflash controller circuitry function of wiping, read and write data has problem.
(5)status[3]＝NANDCTRL_CASE3()；//Micron?ecc?funciton?test
Nandflash controller circuitry in this row test case control fpga chip carries out the ECC verification operation to Micron Nandflash flash chip.This test case is by variable stateu[3] show the last test result, if status[3] and equal 1, illustrate that this test case passes through, the ECC verifying function of the Nandflash controller circuitry in the fpga chip is correct; If equal 0, test crash is described, the ECC verifying function of Nandflash controller circuitry has problem.
In above-mentioned test procedure, function NANDCLRL_CASE0 (), NANDCLRL_CASE1 (), NANDCLRL_CASE2 (), NANDCLRL_CASE3 () have realized the complete test of Nandflash controller circuitry to the MicronNandflash flash chip, its follow-up four function NANDCLRL_CASE4 (), NANDCLRL_CASE5 (), NANDCLRL_CASE6 (), NANDCLRL_CASE7 () act on similar with it, have realized the complete test of Nandflash controller to Toshiba Nandflash flash chip.
C language testing program flexibility and changeability of the present invention, when inserting the Nandflash flash chip of other models on the FPGA debugging plate, can in above-mentioned main () principal function, increase with NANDCLRL_CASE0 (), NANDCLRL_CASE1 (), NANDCLRL_CASE2 (), NANDCLRL_CASE3 () act on similar related example, the test code editor is very flexible.
Test procedure of the present invention changes into strong automatically, behind all Automatic Program end of runs, array status[] can show all use-case test results, if array status[] all members be equal to 1, illustrate that the checking of all test cases passes through, the all functions of Nandflash controller are entirely true, otherwise this function of explanation Nandflash controller has problem.
Proof scheme test process of the present invention is controlled by the C language fully, the automaticity height, and can verify polylith Nandflash chip simultaneously, testing efficiency is high, can fully verify the every function and the compatibility of Nandflash controller, need not manpower and participate in, shortened the R﹠D cycle greatly, reduced R﹠D costs.
Based on above-mentioned advantage, the present invention program has very wide application prospect in digital integrated circuit checking field.
Above-mentioned plateform system and method have been adopted based on FPGA realization Nandflash flash controller Circuit verification, because wherein whole test process is fully by the control of the test code in the test computer, automaticity is high, need not manpower fully participates in, thereby shortened the R﹠D cycle greatly, reduced R﹠D costs; Because the C language that test code adopted is very flexible, just can fully verify simultaneously all functions of Nandfash controller; Integrated a plurality of Nandflash interface slots on the test platform of the present invention in addition, the C language can be verified polylith Nandflash chip simultaneously, fully verified the compatibility of Nandflash controller to various Nandflash flash chips, and do not cause testing efficiency low because Nandflash chip to be measured is more, thereby obtained high as far as possible testing efficiency, not only convenient to use, and stable and reliable working performance, range of application is comparatively extensive.
In this instructions, the present invention is described with reference to its certain embodiments.But, still can make various modifications and conversion obviously and not deviate from the spirit and scope of the present invention.Therefore, instructions and accompanying drawing are regarded in an illustrative, rather than a restrictive.
Claims (15)
1. plateform system of realizing Nandflash flash controller Circuit verification based on FPGA, comprise test computer and the test board that carries the Nandflash flash chip, it is characterized in that, also comprise tester simulator and FPGA debugging plate in the described plateform system, carry the SOC chip on the described FPGA debugging plate, fpga chip and several Nandflash Signal interface modules, be provided with bus switching circuit module and Nandflash controller circuitry module in the described fpga chip, described test computer is successively by described tester simulator, the SOC chip, the bus switching circuit module is connected with described each Nandflash Signal interface module respectively with Nandflash controller circuitry module, and each Nandflash Signal interface module is connected with corresponding test board.
2. the plateform system of realizing Nandflash flash controller Circuit verification based on FPGA according to claim 1 is characterized in that described SOC chip is the SOC chip that is built-in with arm processor.
3. the plateform system of realizing Nandflash flash controller Circuit verification based on FPGA according to claim 2 is characterized in that the SOC chip that described SOC chip is built-in ARM926EJ_S processor.
4. the plateform system of realizing Nandflash flash controller Circuit verification based on FPGA according to claim 2 is characterized in that described bus switching circuit module is that ARM changes FPGA bus circuit module.
5. the plateform system of realizing Nandflash flash controller Circuit verification based on FPGA according to claim 2, it is characterized in that, described tester simulator is the ARM emulator, and this ARM emulator is compiled into the discernible assembly instruction of described arm processor with the test code on the test computer.
6. the plateform system of realizing Nandflash flash controller Circuit verification based on FPGA according to claim 5 is characterized in that described test code is the test code of C language compilation.
7. the plateform system of realizing Nandflash flash controller Circuit verification based on FPGA according to claim 1 is characterized in that described fpga chip is a vitex-4 Series FPGA chip.
8. according to each described plateform system of realizing Nandflash flash controller Circuit verification based on FPGA in the claim 1 to 7, it is characterized in that, described Nandflash Signal interface module is Nandflash signaling interface first slot, described test board is provided with Nandflash signaling interface second slot with the corresponding coupling of this Nandflash signaling interface first slot, described Nandflash signaling interface second slot is connected with described Nandflash flash chip, and the grafting that is coupled of Nandflash signaling interface first slot and corresponding Nandflash signaling interface second slot.
9. the plateform system of realizing Nandflash flash controller Circuit verification based on FPGA according to claim 8, it is characterized in that described Nandflash signaling interface second slot is arranged on the face that carries the Nandflash flash chip of test board or on the opposite face.
10. according to each described plateform system of realizing Nandflash flash controller Circuit verification based on FPGA in the claim 1 to 7, it is characterized in that described test computer is connected with described tester simulator by the USB connecting line.
11., it is characterized in that described tester simulator is connected with described SOC chip by the emulator connecting line according to each described plateform system of realizing Nandflash flash controller Circuit verification based on FPGA in the claim 1 to 7.
12. a method of utilizing the described plateform system of claim 1 to realize Nandflash flash controller Circuit verification is characterized in that described method may further comprise the steps:
(1) described test computer is connected with described tester simulator, SOC chip successively, simultaneously described each Nandflash Signal interface module is connected with corresponding test board;
(2) described test computer, tester simulator and FPGA debugging plate are powered on simultaneously;
(3) generate the recordable paper of realizing bus switching circuit module and Nandflash controller circuitry module, and this recordable paper programming is arrived in the described fpga chip;
(4) described test computer is tested described Nandflash controller circuitry module by the test code of writing in advance.
13. the method for realization Nandflash flash controller Circuit verification according to claim 12, it is characterized in that, described generation realizes the recordable paper of bus switching circuit module and Nandflash controller circuitry module and this recordable paper programming is arrived in the described fpga chip, may further comprise the steps:
(11) the FPGA instrument that uses fpga chip manufacturer to be provided will realize that the HDL language codes of bus switching circuit module and Nandflash controller circuitry functions of modules is converted to the BIT/PROM file;
(12) in the fpga chip of the FPGA programming instrument programming that is provided by fpga chip manufacturer to the FPGA debugging plate.
14. the method for realization Nandflash flash controller Circuit verification according to claim 12, it is characterized in that, described test computer is tested described Nandflash controller circuitry module by the test code of writing in advance, may further comprise the steps:
(21) described test computer produces corresponding test instruction and delivers to described tester simulator according to described test code;
(22) described tester simulator is compiled into the assembly instruction that described SOC chip can be carried out with described test instruction, and delivers to described SOC chip;
(23) described bus switching circuit module of described SOC chip controls and Nandflash controller circuitry module are carried out corresponding test processes.
15. the method for realization Nandflash flash controller Circuit verification according to claim 14, it is characterized in that, described bus switching circuit module of described SOC chip controls and Nandflash controller circuitry module are carried out corresponding test processes, may further comprise the steps:
(31) the circuit correctness and the internal circuit basic function of described fpga chip inside are verified, and the corresponding checking of record result;
(32) the Nandflash controller circuitry module in the described fpga chip of control resets and the read states operational testing to the Nandflash flash chip, and writes down corresponding test result;
(33) the Nandflash controller circuitry module in the described fpga chip of control is read the indications operational testing to the Nandflash flash chip, and writes down corresponding test result;
(34) the Nandflash controller circuitry module of control in the described fpga chip to the Nandflash flash chip wipe, write data and read data operational testing, and write down corresponding test result;
(35) the Nandflash controller circuitry module in the described fpga chip of control is carried out the test of ECC verification operation to the Nandflash flash chip, and writes down corresponding test result.
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