CN101419843A - Flash memory recognition method, recognition device and chip controller - Google Patents

Flash memory recognition method, recognition device and chip controller Download PDF

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Publication number
CN101419843A
CN101419843A CN 200810238909 CN200810238909A CN101419843A CN 101419843 A CN101419843 A CN 101419843A CN 200810238909 CN200810238909 CN 200810238909 CN 200810238909 A CN200810238909 A CN 200810238909A CN 101419843 A CN101419843 A CN 101419843A
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timing
speed
flash memory
test
write
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CN 200810238909
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浩 张
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北京中星微电子有限公司
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Publication of CN101419843A publication Critical patent/CN101419843A/en

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Abstract

The invention provides a recognition method of a flash memory, identification equipment thereof and a chip controller; wherein, the recognition method of the flash memory comprises the steps: the page types supported by the flash memory are judged, the positions of bad blocks are determined, the speed time sequence of the memory is acquired; the capacity of the memory is obtained, and a plurality of key parameters of the flash memory are obtained in a self-adapting way, thereby the chip controller can realize to control the flash memory according to the identified key parameters under the condition that a data decoder of a control chip does not store the key parameters of the flash memory connected with the chip controller.

Description

快闪存储器识别方法、识别装置、芯片控制器 A flash memory identification method identifying means, the controller chip

技术领域 FIELD

本发明涉及快闪存储器领域,特别地,涉及一种快闪存储器识别方法、识别装置、芯片控制器。 The present invention relates to a flash memory, and more particularly, to a method of identifying a flash memory, identifying means, the controller chip.

背景技术 Background technique

NAND型快闪存储器(NAND FLASH)是一种可在线进行电擦写的非易失半导体存储器,具有擦写速度快、低功耗、大容量、低成本等优点,广泛应用于MP3、 MP4、手机、数码照相机、摄像机等电子产品中。 NAND type flash memory (NAND FLASH) is an online electrically rewritable nonvolatile semiconductor memory, has the advantage of flash speed, low power consumption, high-capacity, low cost, is widely used in MP3, MP4, mobile phones, digital cameras, video cameras and other electronic products. NAND FLASH 芯片通过NAND FLASH控制器写入、读取数据,NAND FLASH控制器传送到NAND FLASH芯片的数据包括地址数据、命令数据和信息数据。 NAND FLASH chip NAND FLASH controller by writing, reading data, NAND FLASH controller transmits data to the NAND FLASH chip includes address data, command data and information data. 现有的NAND FLASH控制器通过内部数据传输通道,将地址和命令数据、及信息数据传送到NAND FLASH存储器。 Conventional NAND FLASH controller via the internal data transmission channel, transmits the address and command data and information data to the NAND FLASH memory.

参阅图l,为现有的NAND FLASH系统结构示意图,包括系统总线10、 位于NANDF LASH控制器内部的总线时序接口11、内部数据传输通道12、 命令数据解码器13、FLASH时序发生器14、NANDFLASH接口15以及NAND FLASH存储器16。 Referring to Figure L, is a schematic diagram of a conventional NAND FLASH system architecture, comprising a system bus 10, the bus timing controller located inside LASH NANDF interface 11, internal data transfer path 12, the command data decoder 13, FLASH timing generator 14, NANDFLASH interface 15, and NAND FLASH memory 16. 总线时序接口11将接收到的系统总线IO传送的数据通过内部数据通道12直接传送至FLASH时序发生器14, FLASH时序发生器14 将系统总线时序转换为NAND FLASH存储器时序,并通过NAND FLASH接口15,传送该数据到NAND FLASH存储器16。 IO bus data transfer system bus timing interface 11 directly transmits the received data through the internal passage 12 to the FLASH timing generator 14, a timing bus 14 to the system timing generator is converted into FLASH memory NAND FLASH timing, and interface 15 via NAND FLASH transmitting the data to the NAND FLASH memory 16. 在NAND FLASH的使用过程中,如果NAND FLASH控制器不能获取NAND FLASH存储器时序,将直接影响FLASH存储器数据的传输。 In the process of using the NAND FLASH, if the controller can not get NAND FLASH memory NAND FLASH sequence, FLASH memory will directly affect the data transmission.

并且,上述数据包括地址数据、命令数据和信息数据,命令数据在内部数据通道12上传输时,需要命令数据解码器13对命令数据进行解析,从而,转换为FLASH存储器16可以执行的数据。 And, said data including address data, command data and information data, command data on the internal data transfer path 12, required command data decoder 13 parses the command data, whereby the data is converted into the FLASH memory 16 can be performed. 并且,命令数据解析的前提是:控制器能够可以确定FLASH存储器16的命令转换信息,包括大、小页面类型、 坏块标记位、容量大小等。 And the premise, the data parsing commands are: controller can command the FLASH memory 16 may determine that conversion information, including large and small page type, bad block flag, the capacity size.

但是,由于NANDFLASH生产厂商非常多,不同厂商的产品的芯片时序、命令转换信息等关键参数并不相同,为了兼容不同的FLASH存储器,需要芯片控制器根据具体的FLASH存储器,获取与之连接芯片的各个关键参数,从而解析出能够为FLASH存储器所接收的命令,并且以FLASH存储器接口相应的传输速度发送数据。 However, because so many NANDFLASH manufacturers, chip timing different manufacturers products, key parameters such as command conversion information are not the same, different FLASH memory for compatibility, according to the specific needs of the controller chip FLASH memory chips connected thereto acquires various key parameters to parse the commands to be received into the FLASH memory, FLASH memory and transmits the data to the corresponding transmission speed of the interface.

针对这一问题,通常的做法是,厂家用户预先将多个FLASH存储器对应各个关lt参数等存储在数据解码器13中,在工作时,命令数据解码器13根据芯片控制器所连接的FLASH存储器类型,寻找对应的命令转换信息,完成对命令数据的解析,并且将解析的命令数据按照芯片的速度时序发送数据。 To solve this problem, it is common practice, the manufacturer of the user in advance corresponding to each of a plurality of FLASH memory Off lt parameters stored in the data decoder 13, in operation, the command data decoder 13 according FLASH memory chip controller connected type, find the corresponding command conversion information, complete parsing the command data, command data and transmits the parsed data according to the speed of the timing chip.

但是,这种方式的缺点是,命令数据解码器13可预先存储的关键参数非常有限,很难把所有厂商生产的FLASH存储器的转换信息都包括,并且, FLASH存储器更新的速度很快,如果控制器中没有新产品的对应的配置信息,该FLASH存储器将无法使用。 However, the disadvantage of this approach is that, previously stored key parameters 13 may command data decoder is very limited, it is difficult to convert all the information about the FLASH memory manufacturers are included, and, FLASH memory update quickly, if the control no configuration is information corresponding to the new product, the FLASH memory will not be available.

有鉴于此,需要本领域技术人员迫切解决的一个技术问题就是:提供一种FLASH存储器的识别方法,基于该方法,芯片控制器能够分析与之连接的各种FLASH存储器的关键参数,从而实现对FLASH存储器的控制。 In view of this, an urgent need in the art in the art to solve a technical problem is: A method for providing identification FLASH memory, based on this method, the controller chip can analyze various key parameters FLASH memory connected thereto, so as to achieve FLASH memory control.

发明内容 SUMMARY

本发明所要解决的技术问题是:提供一种FLASH存储器的识别方法,基于该方法,芯片控制器能够分析与之连接的各种FLASH存储器的关键参数, 从而实现对FLASH存储器的控制。 The present invention solves the technical problem are: to provide a method of identifying FLASH memory, based on this method, the controller chip can analyze various key parameters FLASH memory connected thereto, in order to achieve control of the FLASH memory.

为了解决上述问题,本发明公开了一种快闪存储器识别方法,所述方法在快闪存储器上电复位后,执行如下步骤:向所述快闪存储器发出小页面读指令, 并检测该指令是否执行,若是,则确定所述快闪存储器支持的读命令类型为小页面类型;若否,则确定所述快闪存储器支持的读命令类型为大页面类型;应 To solve the above problems, the present invention discloses a method of identifying a flash memory, after the power-on reset method of the flash memory, performing the steps of: issuing a read command to a small page of the flash memory, and detects whether the instruction performing, if a read command to the flash memory to determine the type of support is a small page type; if not, the read command of the flash memory to determine the type of support is a large page type; should

标记出坏块位置;分别应用多个读写时序进行快闪存储器的读写测试,并分析测试结果,获取该存储器的速度时序;预置所述快闪存储器的多个测试容量地址,并向所述测试容量地址发出写指令并检测,依据执行结果确定所述快闪存储器容量;以及,存储包括有所述读命令类型、速度时序、坏块位置、存储器容量的参数值。 Marked bad block position, respectively; a plurality of applications read and write timing of read and write test of the flash memory, and analyze the test results, the timing of the acquisition rate of the memory; a plurality of pre-testing of the flash memory capacity of the address, and the capacity of the test address and write command is issued for detecting, determining the capacity of the flash memory according to the execution result; and storing said read command including the type, speed, timing, bad block location, the parameter value of the memory capacity.

优选地,获取该快闪存储器的速度时序进一步包括如下步骤:不同频率的速度时序读写测试、中间频率的速度时序读写测试、重新确定两相邻频率的速度时序。 Preferably, the flash memory acquires further comprising the step of timing the speed: speed of reading and writing timings of the different test frequencies, an intermediate frequency timing write speed test, the speed of re-timing determining two adjacent frequency. 其中, among them,

不同频率的速度时序读写测试为应用所述多个读写时序中,两相邻频率的速度时序进行存储器的读写测试,若其中的小频率速度时序测试成功,而大频率速度时序的测试失败,则执行中间频率的速度时序读写测试的步骤; Timing speed read and write tests for the application of different frequencies in said plurality of read and write timing, the timing two adjacent frequency speed read and write tests of memory, wherein if the small timing clock speed test is successful, a large frequency and timing of the test speed fails, the step of timing an intermediate frequency read-write speed test is performed;

中间频率的速度时序读写测试为以所述两相邻频率和的均值作为中间频率,应用该中间频率的速度时序对存储器进行读写测试,若测试成功,则依据所述中间频率的速度时序确定存储器的速度时序,若失败,则执行重新确定两相邻频率的速度时序的步骤; Speed ​​Speed ​​Timing The timing of read and write tests to the intermediate frequency of two adjacent frequency as the intermediate frequency and the mean speed of the timing of the application of an intermediate frequency to the memory read and write test, if the test is successful, according to the intermediate frequency determining the speed of the memory timing, if failed, the two adjacent speed step timing re-determined frequency;

重新确定两相邻频率的速度时序为以所述小频率速度时序、中间频率的速速时序作为两相邻频率的速度时序,并返回中间频率的速度时序读写测试的步骤。 Re-determining the speed of two adjacent frequency to the minimum frequency for the timing speed timing, timing haste speed timing as an intermediate frequency of two adjacent frequency, timing and returns to step speed test write an intermediate frequency.

优选地,所述测试容量地址为2幂指数,并且,确定所述快闪存储器的容量进一步包括:向所述多个测试容量地址中的两相邻地址发出写指令后,若其中的小地址写成功,而大地址写失败,则依据小地址确定所述存储容量。 Preferably, the test address capacity of exponent 2, and determines the capacity of the flash memory further comprises: issuing to said plurality of test capacity addresses two adjacent address after the write instruction, wherein when the small address writing success, and a large failed to write the address, determining that the storage capacity is based on a small address.

优选地,所述读写时序由不同频率的时钟所产生。 Preferably, the read and write timing clock generated by the different frequencies.

依据本发明另一实施例,还公开了一种快闪存储器识别装置,所述快闪存储器包括:读命令类型判断模块、坏块位置确定模块、速度时序获取模块、存储器容量确定模块以及参数值存储模块。 According to another embodiment of the present invention, also discloses a flash memory identification means, said flash memory comprising: a read command type determining module, the bad block location determination module, speed timing acquisition module, the memory capacity determination module and a parameter value memory modules.

其中,读命令类型判断模块用于向所述快闪存储器发出小页面读指令,并检测该指令是否执行,若是,则确定所述快闪存储器支持的读命令类型为小页面类型;若否,则确定所述快闪存储器支持的读命令类型为大页面类型;坏块 Wherein the means for determining the type of the read command issued to a small page of the flash memory read instruction, and to detect whether the instruction is executed, if a read command to the flash memory to determine the type of support is a small page type; if not, determining that the flash memory type supported by a large page read command type; bad block

器的坏块读取测试,并标记出坏块的位置;速度时序获取模块用于分别应用多个读写时序进行快闪存储器的读写测试,并分析测试结果,获取该存储器的速 Bad block is read test, and mark the location of the bad block; speed timing acquisition means for applying a plurality of read and write timing of the read and write test of the flash memory, respectively, and to analyze the test results, the acquired speed memory

度时序;存储器容量确定模块用于预置所述快闪存储器的多个测试容量地址,并向所述测试容量地址发出写指令并检测,依据执行结果确定所述快闪存储器 Of timing; preset memory capacity determining means for testing said plurality of addresses of the flash memory capacity, and the capacity of the test write command is issued, and the address detecting, determining, based on the results of a flash memory

容量;以及,参数值存储模块用于存储包括有所述读命令类型、速度时序、坏块位置、存储器容量的参数值。 Capacity; and a storage module for storing a parameter value comprises the read command type, speed timing, bad block location, the parameter value of the memory capacity.

优选地,所述速度时序获取模块进一步包括:不同频率的速度时序读写测试单元、中间频率的速度时序读写测试单元以及重新确定两相邻频率的速度时序单元。 Preferably, the speed of the timing acquisition module further comprises: a timing different frequencies write speed test unit, the test write speed of the timing unit and an intermediate frequency re-timing unit determining the speed of two adjacent frequency.

其中,不同频率的速度时序读写测试单元用于应用所述多个读写时序中, Wherein, the speed of read and write tests of different frequencies timing means for applying said plurality of read and write timing,

两相邻频率的速度时序进行存储器的读写测试,若其中的小频率速度时序测试 Write timing test speed of two adjacent frequency of a memory, wherein if the timing clock speed small Test

成功,而大频率速度时序的测试失败,则选通中间频率的速度时序读写测试单元;中间频率的速度时序读写测试单元用于以所述两相邻频率的均值作为中间 Success rate and a large frequency timing test fails, then the write sequence selected from the group velocity test unit through an intermediate frequency; write speed of a timing test unit to an intermediate frequency for the average of two adjacent frequency as an intermediate

频率,应用该中间频率的速度时序对存储器进行读写测试,若测试成功,则依据所述中间频率的速度时序确定存储器的速度时序,若失败,则选通重新确定两相邻频率的速度时序单元;重新确定两相邻频率的速度时序单元用于以所述小频率速度时序、中间频率的速速时序作为两相邻频率的速度时序,并选通中间频率的速度时序读写测试单元。 Speed ​​frequency, the speed of the application timing of the intermediate frequency to the memory read and write test, if the test is successful, the memory timing is determined speed depending on the speed of the intermediate frequency timing, if failed, to redefine the strobe timing of two adjacent frequency unit; re-timing unit determining the speed of two adjacent frequency for timing of swift sequence to the small speed frequency, an intermediate frequency of two adjacent frequency as the speed of the timing and speed of the intermediate frequency of the strobe timing of reading and writing test unit.

优选地,所述测试容量地址为2指数幂,并且,所述存储器容量确定才莫块 Preferably, the capacity of the test address exponential power of 2, and the memory capacity determination block only Mo

进一步包括:写指令发出单元、检测单元。 Further comprising: a write instruction issue unit, the detection unit.

其中,写指令发出单元用于分别向所述多个测试容量地址中的两相邻地址 Wherein the write instruction issuing unit for respectively adjacent to said plurality of two tests the capacity of the address in the address

发出写指令;检测单元用于判断针对于所述两相邻地址的写指令是否执行成 Write command is issued; detecting means for determining whether two adjacent address to the write instruction to execute

功,若其中的小地址写成功,而大地址写失败,则依据小地址确定所述存储器容量。 Power, wherein if the address written little success, and large write address fails, it is determined that the memory capacity is small based on the address.

优选地,所述读写时序由不同频率的时钟所产生。 Preferably, the read and write timing clock generated by the different frequencies.

依据本发明另一实施例,还公开了一种芯片控制器,所述芯片控制器包括快闪存储器识别装置,所述快闪存储器识别装置包括:读命令类型判断模块、 坏块位置确定模块、速度时序获取模块、存储器容量确定模块以及参数值存储模块。 According to another embodiment of the present invention, also discloses a controller chip, the chip identification device controller comprises a flash memory, a flash memory identification means comprising: read command type determining module, the bad block location determination module, speed timing acquisition module, the memory capacity determination module and a storage module parameters.

其中,读命令类型判断模块用于向所述快闪存储器发出小页面读指令,并检测该指令是否执行,若是,则确定所述快闪存储器支持的读命令类型为小页面类型;若否,则确定所述快闪存储器支持的读命令类型为大页面类型;坏块位置确定模块用于应用所述快闪存储器支持的读命令类型进行所述快闪存储器的坏块读取测试,并标记出坏块的位置;速度时序获取模块用于分别应用多个读写时序进行快闪存储器的读写测试,并分析测试结果,获取该存储器的速 Wherein the means for determining the type of the read command issued to a small page of the flash memory read instruction, and to detect whether the instruction is executed, if a read command to the flash memory to determine the type of support is a small page type; if not, determining that the flash memory type supported by a large page read command type; bad block location determination module for applying the read command type flash memory supports bad block of the flash memory read test, and mark the location of bad blocks; means for timing acquisition rate were applied to test a plurality of read and write read and write timing of the flash memory, and analyze the test results, the memory acquisition speed

度时序;存储器容量确定沖莫块用于预置所迷快闪存储器的多个测试容量地址, 并向所述测试容量地址发出写指令并检测,依据执行结果确定所述快闪存储器容量;以及,参数值存储模块用于存储包括有所述读命令类型、速度时序、坏块位置、存储器容量的参数值。 Of timing; Mo punch block memory capacity determination for a plurality of pre-testing the capacity of the flash memory addresses of the fans, to test the capacity of the write command is issued, and the address is detected, determining that the flash memory capacity based on execution result; , value storage means for storing the parameter comprises the type of the read command, the timing rate, bad block location, the parameter value of the memory capacity.

优选地,所述速度时序获取模块进一步包括:不同频率的速度时序读写测试单元、中间频率的速度时序读写测试单元以及重新确定两相邻频率的速度时序单元。 Preferably, the speed of the timing acquisition module further comprises: a timing different frequencies write speed test unit, the test write speed of the timing unit and an intermediate frequency re-timing unit determining the speed of two adjacent frequency.

其中,不同频率的速度时序读写测试单元用于应用所述多个读写时序中, 两相邻频率的速度时序进行存储器的读写测试,若其中的小频率速度时序测试成功,而大频率速度时序的测试失败,则选通中间频率的速度时序读写测试单 Wherein the speed of the test write timing means for different frequencies of the plurality of read and write timing of application, timing of two adjacent frequency speed read and write tests of memory, wherein if the small timing clock speed test is successful, and a large frequency speed timing test fails, the strobe timing of reading and writing speed of the intermediate frequency test sheet

频率,应用该中间频率的速度时序对存储器进行读写测试,若测试成功,则依据所述中间频率的速度时序确定存储器的速度时序,若失败,则选通重新确定两相邻频率的速度时序单元;重新确定两相邻频率的速度时序单元用于以所述小频率速度时序、中间频率的速速时序作为两相邻频率的速度时序,并选通中间频率的速度时序读写测试单元。 Speed ​​frequency, the speed of the application timing of the intermediate frequency to the memory read and write test, if the test is successful, the memory timing is determined speed depending on the speed of the intermediate frequency timing, if failed, to redefine the strobe timing of two adjacent frequency unit; re-timing unit determining the speed of two adjacent frequency for timing of swift sequence to the small speed frequency, an intermediate frequency of two adjacent frequency as the speed of the timing and speed of the intermediate frequency of the strobe timing of reading and writing test unit.

与现有技术相比,本发明具有以下优点: Compared with the prior art, the present invention has the following advantages:

在控制芯片的数据解码器中没有存储与芯片控制器相连接的、FLASH存储器关键参数的情况下,通过测试的方法,自适应地获取FLASH存储器的多个关键参数,从而,控制芯片能够依据关键参数实现对FLASH存储器的控制。 No memory chip and the controller chip is connected to a control data decoder, a case where key parameters FLASH memory, by the method of testing a plurality of adaptively acquiring key parameters of the FLASH memory, so that, based on the control chip can be critical parameters to achieve control of the FLASH memory.

附图说明 BRIEF DESCRIPTION

图1现有技术中的NAND FLASH系统结构示意图; NAND FLASH system configuration of a prior art schematic diagram of FIG;

图2是根据本发明快闪存储器识别方法实施例的流程图; FIG 2 is a flowchart of an embodiment according to the present invention, a flash memory identification method;

图3是根据本发明获取快闪存储器速度时序的实施例的流程图;图4是根据本发明快闪存储器识别装置的结构示意图; FIG 3 is a flowchart of an embodiment of a flash memory speed acquisition timing in accordance with the present invention; FIG. 4 is a schematic view of a flash memory device according to the present invention is identified;

图5是^f艮据本发明包括有识别装置的控制芯片结构示意图。 FIG 5 is ^ f gen accordance with the invention comprises a configuration diagram of the control chip identification device.

具体实施方式 Detailed ways

为使本发明的上述目的、特征和优点能够更加明显易懂,下面结合附图和具体实施方式对本发明作进一步详细的说明。 For the above objects, features and advantages of the invention more comprehensible, the present invention is further the following detailed description in conjunction with the accompanying drawings and specific embodiments.

参照图2,示出了根据本发明快闪存储器识别方法实施例的流程图,在所述快闪存储器上电复位后,执行如下步骤: Referring to Figure 2, there is shown a flowchart of an embodiment of a flash memory according to the present invention, identification methods, in the flash memory after the power-on reset, perform the following steps:

步骤201:向所述快闪存储器发出小页面读指令,并检测该指令是否执行, 若是,则确定所述快闪存储器支持的读命令类型为小页面类型;若否,则确定所述快闪存储器支持的读命令类型为大页面类型; Step 201: issuing a read command to a small page of the flash memory, and detects whether the instruction is executed, and if so, determining that the flash memory read command type supported by small page type; if not, determining that the flash supported memory read command type is large page type;

步骤202:应用所述快闪存储器支持的读命令类型进行所述快闪存储器的坏块读取测试,并标记出坏块位置; Step 202: the application of the flash memory read command types supported by the bad block flash memory read test, and mark the bad block location;

步骤203:分别应用多个读写时序进行快闪存储器的读写测试,并分析测试结果,获取该存储器的速度时序; Step 203: respectively applying a plurality of read and write timing of the read and write test of the flash memory, and analyze the test results, the timing of the acquisition rate of the memory;

步骤204:预置所述快闪存储器的多个测试容量地址,并向所述测试容量地址发出写指令并检测,依据执行结果确定所述快闪存储器容量;以及, Step 204: the plurality of test preset address of the flash memory capacity, the capacity of the test address and write command is issued and detecting, determining the capacity of the flash memory according to the execution result; and,

步骤205:存储包括有所述读命令类型、速度时序、坏块位置、存储器容量的参数值。 Step 205: the memory comprises a read command type parameter value, timing rate, bad block location, the memory capacity.

下面具体解释步骤201: NAND FLASH小页面类型的读命令只需要一个机器周期的一段读指令,外加地址;而大页面类型的读指令需要两个机器周期的两段读指令,外加地址。 A specific interpretation step 201: NAND FLASH type small page read command requires only one machine cycle period of the read command plus the address; and large type of page read command read instruction requires two machine cycles of the two, plus the address. 因此使用小页面读命令可以区分大小页面类型。 Therefore, the use of small size of the page read command can differentiate page types. 在具体执行时,向快闪存储器发出小页面读指令,然后检测该指令是否马上执行: When the specific implementation, issuing a read command to the small flash memory page, and then detecting whether the instruction is executed immediately:

若该快闪存储器支持的是小页面读指令,那么,该指令将马上^皮执行,若该快闪存储器支持的是大页面读指令,则当该快闪存储器接收到小页面读指令时,只接收到了一个机器周期的一段指令,存储器会继续等待第二个机器周期的另一段指令,也就是说,小页面读指令不能启动快闪存储器进行命令的读取, 因此,该小页面读指令将不会被执行。 If the support is a small flash memory page read instruction, then the instruction will be executed immediately transdermal ^, if the flash memory supports a large page read instruction, when the flash memory receives a small page read command, receives only a period of a machine instruction cycle, memory will continue to wait for another period of the second cycle of the machine instructions, i.e., small page read instruction can not start a command to read the flash memory, and therefore, the small page read command It will not be executed. 通过小页面读指令的执行结果,就可以判断该快闪存储器能够支持的读命令类型。 Results of small pages by the read command, read command can determine the type of the flash memory can support. 在这里,需要着重说明的是:在上面所描述的用于获取各个参数的多个步骤中,步骤201—定是最先执行,即,确定所述快闪存储器所支持的读命令类型为大页面类型或者是小页面类型是最作为获取其他关键参数的前提,只有这个参数确定了,才能够依据这个参数,发出正确的指令,进行其他参数的确定。 Here, the need is highlighted: a step for acquiring a plurality of individual parameters described above, the first step is set 201- performed, i.e. determination of the flash memory read command types supported by a large page type or page type is small as most other key parameters to obtain the premise, this is the only parameter determines, based on the parameters to be able to send the right commands, determination of other parameters.

但是,步骤202、步骤203、步骤204的执行并没有时间先后的限制,也就是说,坏块位置参数、存储器速度时序参数以及快闪存储器容量参数之间的确定没有彼此间的依赖关系。 However, step 202, step 203, and step 204 have no time limit, that is, the bad block is determined between the position parameter, a timing parameter memory speed and memory capacity of the flash parameters no dependencies between them. 本发明在此描述的顺序只是执行中的一种情况, 本发明对此并不做限定。 One instance of the present invention, the order described herein is only performed, this does not restrict the present invention.

参照图3,示出了根据本发明获取快闪存储器速度时序的实施例的流程图, 包括如下步骤: Referring to Figure 3, there is shown a flowchart of an embodiment of a flash memory speed acquisition timing in accordance with the present invention, comprising the steps of:

步骤301:对不同频率的速度时序进行读写测试。 Step 301: reading and writing tests speed timing different frequencies.

步骤302:在多个不同频率的速度时序中,判断两相邻频率的速度时序进行测试时,是否相对较小的速度时序读写成功,而相对较大频率的速度时序读写失败? Step 302: when the speed of the timing of a plurality of different frequencies, it is determined the speed of two adjacent frequency timing tests, whether a relatively small velocity successful read timing, and write timing rate is relatively large frequency failure? 若不是这种情况,则返回执行步骤301;若是这种情况,则执行步骤303。 If this is the case, execution returns to step 301; if the case, step 303 is performed.

步骤303:对中间频率的速度时序进行读写测试。 Step 303: the speed of the read and write timing of an intermediate frequency test.

在一个实施例中,以所述两相邻频率和的均值作为中间频率。 In one embodiment, two adjacent to the intermediate frequency and the average frequency. 当然,实际中,可以两相邻频率之间的任何一个值作为中间频率,本发明在此不喉支任何限定,均值只是其中的一种实施方式。 Of course, in practice, it may be a value between any two adjacent frequency as the intermediate frequency in this invention is not limited in any laryngeal branched mean just one embodiment.

步骤304:判断中间频率的速度时序是否读写成功? Step 304: determining whether the speed of the read and write timing of the success of an intermediate frequency? 若成功,执行步骤305,若失败,执行步骤306。 If successful, step 305, if fails, step 306 is performed.

步骤305:将中间频率的速度时序作为快闪存储器的速度时序。 Step 305: the speed of the intermediate frequency timing as the timing speed of a flash memory.

步骤306:重新确定两相邻频率的速度时序,并返回执行步骤303。 Step 306: Re-determine the speed of two adjacent frequency timing, and returns to step 303.

下面结合一个实例详细说明获取快闪存储器速度时序的方法。 The following method of obtaining a binding speed of a flash memory timing example described in detail. 假设有多个由不同频率的时钟所产生读写时序,分别为& 、 f2..... d、 Suppose that there are a plurality of read and write timing clock generated by the different frequencies, respectively, &, f2 ..... d,

fn、 fn+1...,并且,f!〈f2〈…〈fn.i〈fn〈fn+,…,其中,f^、 fn为两相邻频率的速度时序。 fn, fn + 1 ..., and, f! <f2 <... <fn.i <fn <fn +, ..., wherein, f ^, fn is the frequency of the two adjacent speed timing. 首先,分别应用上述多个读写时序进行存储器的读写测试,在这里,所述 First, each of the plurality of applications read and write timing of the memory read and write tests, where the

的读写测试的过程是这样的:首先对存储器进行写操作,然后,将写的内容读出来,若读出的内容与写的内容相同,则测试成功,否则,测试失败。 The process of reading and writing test is this: First, memory write, then write the contents read out, if the content is read out and write the contents of the same, the test is successful, otherwise, the test fails.

在测试的过程中, 一定会出现这样的情况,即以f! In the process of testing, it will be the case, that f! 、 f2..... fn-!的读写 , F2 ..... fn-! Read and write

时序进行存储器的读写测试时,测试结果都是成功,而以fn读写时序进行存储 When the timing of the memory read and write tests, the test results are successful, and stores the read and write timing to fn

器的读写测试时,测试结果失败,此时,可以确定FLASH存储器的能够支持 When the reader of the tester, the test fails, this time may be determined FLASH memory can support

的速度时序一定介于d、 fn之间; The timing between the speed constant d, fn;

接下来,以f^、 fn之间的中间频率的速度时序进行读写测试,例如d为 Subsequently, at a speed intermediate between the timing f ^, fn the frequency of the read and write tests, such as d

100Hz、 fn为200Hz,则以150Hz的速度时序进行读写测试: 100Hz, fn read and write tests of 200Hz, 150Hz sequence of places speed:

若测试成功,则依据150 Hz的速度时序确定存储器的速度时序, 一种情况是,以150 Hz的速度时序作为存储器的速度时序,另一种情况是,以稍小于150Hz的速度时序作为存储器的速度时序。 If the test is successful, the 150 Hz timing depending on the speed of the memory speed is determined timing, a case, a speed of 150 Hz as the speed of the timing sequence of a memory, another case is slightly less than the speed at the timing of a memory of 150Hz speed timing. 因为实际上,小于150Hz的速度时序都可以得到存储器的支持; Because in fact, the timing is less than the speed of 150Hz can be supported in a memory;

若测试失败,则以100Hz、 150Hz重新确定两相邻频率的速度时序,并以该两相邻频率和的均值125 Hz作为中间频率,应用该125 Hz的速度时序对存储器进行读写测试,若测试成功,则依据125 Hz的速度时序确定存储器的速度时序。 If the test fails, places 100Hz, 150Hz velocity to redefine the timing of the two adjacent frequencies, and in that two adjacent frequencies and the mean value as an intermediate frequency 125 Hz, 125 Hz a speed of the application timing of the memory read and write test, if test is successful, determine the speed of the timing of memory depending on the speed of the timing of 125 Hz. 若测试失败,则与上述过程类似,重复上述过程,直到找到能够正确读写的速度时序。 If the test fails, the procedure is similar to the above, the above process is repeated until you find the speed can be accurately read and write timing.

另外,在确定所述存储器的容量时,其中的测试容量地址为2指数幂,这样取的原因是,由于FLASAH存储器的容量都是2的指数幂,例如,1G大小的存储器为2的30次方,4G大小的存储器为2的32次方。 Further, in determining the capacity of the memory, wherein the capacity of the test address exponential power of 2, taking this reason that, since the capacity of the memory is FLASAH exponential power of 2, e.g., 1G memory size of 2 to 30 Fang, 4G memory size is 2 to the power 32. 确定所述快闪存储器的容量可以这样做:向所述多个测试容量地址中的两相邻地址发出写指令后,若其中的小地址写成功,而大地址写失败,则依据小地址确定所述存储容量。 Determine the capacity of the flash memory can do this: test capacity issued to said plurality of addresses in two adjacent address after the write command, if a write address wherein a small success, but large write address fails, it is determined based on a small address the storage capacity. 举例来说,若向23G的测试容量地址发出写指令后,测试成功,而向231 的测试容量地址发出写指令后,测试失败,则可以确定该快闪存储器的容量为23()4立,即为1G。 For example, if the write command is issued to address 23G capacity test, the test is successful, a test 231 is issued to the write command address capacity test fails, it may be determined that the capacity of flash memory 23 () 4 stand, namely 1G.

进一步地,上面所描述的实施例中,读写时序可以由不同频率的时钟所产生。 Further, the embodiments described above, the read and write timing can be generated by a different clock frequencies. 另夕卜,除了自适应获取的包括括有所述读命令类型、速度时序、坏块位置、 存储器容量的参数值外,还可以自适应的获得所述存储器是否支持一些用户关心的特殊指令,如果支持允许使用,否则使用禁止,使用常规命令代替。 Another Bu Xi, comprising in addition comprises obtaining adaptive with said external read command type, speed timing, bad block location, the parameter value of the memory capacity can be obtained if the adaptive memory supports a number of special concern to the user instruction, If you support allows the use of, or the use of prohibited use of conventional command instead. 具体 specific

获取该信息的方式是:向所述存储器发出某一特殊指令,若存储器返回错误信息,则存储器不支持这个特殊指令,否则,存储器支持这个特殊指令。 The information acquired is: issuing a special instruction to the memory, when the memory returns an error message, the memory does not support the special instruction, otherwise, the memory supports special instructions. 其中的特殊指令可以包括拷贝读指令、拷贝写指令、緩存编程指令等,这里只是示例性的给出这几个例子,本发明不限于此。 Wherein special instructions may include instructions read copy, copy write instruction cache program instructions, etc., are given herein are exemplary only these few examples, the present invention is not limited thereto.

参阅图4,示出了根据本发明快闪存储器识别装置的结构示意图,该识别装置包括: Referring to Figure 4, a schematic diagram showing the structure of a flash memory of the identification device according to the present invention, the identification apparatus comprising:

读命令类型判断模块401,用于向所述快闪存储器发出小页面读指令,并检测该指令是否执行,若是,则确定所述快闪存储器支持的读命令类型为小页面类型;若否,则确定所述快闪存储器支持的读命令类型为大页面类型; Read command type determining module 401, for sending to a small page of the flash memory read instruction, and to detect whether the instruction is executed, if a read command to the flash memory to determine the type of support is a small page type; if not, determining that the read command type flash memory support for large page type;

坏块位置确定模块402,用于应用所述快闪存储器支持的读命令类型进行所述快闪存储器的坏块读取测试,并标记出坏块的位置; Bad block location determination module 402, a read command for the types of applications supported by the flash memory performs the read bad block of a flash memory test, and mark the location of bad blocks;

速度时序获取模块403,用于分别应用多个读写时序进行快闪存储器的读写测试,并分析测试结果,获取该存储器的速度时序; Speed ​​timing acquisition module 403, a plurality of read and write tests were applied for read and write timing of the flash memory, and analyze the test results, the timing of the acquisition rate of the memory;

存储器容量确定^f莫块404,用于预置所述快闪存储器的多个测试容量地址, 并向所述测试容量地址发出写指令并检测,依据执行结果确定所述快闪存储器容量;以及, ^ F Mo memory capacity determination block 404, a plurality of the preset address of the flash memory capacity of the test, the test and issues a write command and address capacity detecting, determining, based on the capacity of the flash memory execution result; ,

参数值存储模块405,用于存储包括有所述读命令类型、速度时序、坏块位置、存储器容量的参数值。 Parameter storage module 405 for storing a read command including the type, speed, timing, bad block location, the parameter value of the memory capacity.

其中,速度时序获取模块403的具体结构如下,包括不同频率的速度时序读写测试单元、中间频率的速度时序读写测试单元、重新确定两相邻频率的速度时序单元:其中, Wherein the speed timing acquisition module 403 as a specific configuration, including the speed of reading and writing timings of the different frequencies test unit, the test write speed timing means intermediate frequency, the frequency of re-determining the speed of two adjacent timing units: wherein,

不同频率的速度时序读写测试单元用于应用所述多个读写时序中,两相邻频率的速度时序进行存储器的读写测试,若其中的小频率速度时序测试成功, 而大频率速度时序的测试失败,则选通中间频率的速度时序读写测试单元;间频率,应用该中间频率的速度时序对存储器进行读写测试,若测试成功,则依据所述中间频率的速度时序确定存储器的速度时序,若失败,则选通重新确 Write timing rate different frequency testing unit for reading and writing timings of the plurality of applications, two adjacent frequency timing speed read and write tests of memory, wherein if the small timing clock speed test is successful, the speed and timing of a large frequency test fails, the speed of the strobe timing of reading and writing an intermediate frequency test unit; inter- frequency, application timing of the intermediate frequency speed memory read and write test, if the test is successful, the memory timing is determined depending on the speed of the intermediate frequency speed timing, if fails, then re-determined gating

定两相邻频率的速度时序单元; Timing means set the speed of two adjacent frequency;

重新确定两相邻频率的速度时序单元用于以所述小频率速度时序、中间频率的速速时序作为两相邻频率的速度时序,并选通中间频率的速度时序读写测试单元。 Re-determining the speed of two adjacent frequency to the timing means for timing the speed of small frequency, timing of swift speed timing as an intermediate frequency of two adjacent frequency, an intermediate frequency gating rate and write timing test unit.

进一步地,所述测试容量地址为2指数幂,并且,所述存储器容量确定沖莫块进一步包括写指令发出单元和;f全测单元:其中, Furthermore, the capacity of the test address exponential power of 2, and the memory capacity determination Mo punch further includes a write block and the instruction issue unit; F full sensing unit: wherein,

写指令发出单元用于分别向所述多个测试容量地址中的两相邻地址发出写指令;检测单元用于判断针对于所述两相邻地址的写指令是否执行成功,若其中的小地址写成功,而大地址写失败,则依据小地址确定所述存储器容量。 Write command issuing unit for issuing to each of the plurality of addresses in the capacity test of two adjacent address write command; detecting means for determining a write command to the two adjacent address executed successfully, wherein when the small address writing success, and address a large write fails, the memory capacity is determined based on a small address.

并且,在上面描述的识别装置中,读写时序由不同频率的时钟所产生,但本发明不限于此。 Further, in the above-described identifying means, read and write timing generated by the clock of a different frequency, but the present invention is not limited thereto.

在上述的识别装置中,还可以包括判断存储器能否支持用户所关心的一些特殊指令,例如拷贝读指令、拷贝写指令、緩存编程指令等,由于在方法部分已经对此做了说明,在此不再赘述。 In the recognition apparatus may further include determining whether a memory support special interest to the user instruction, for example, copying a read command, a write copy instruction cache program instructions, etc., since the method has been part This is illustrated in this No longer.

参照图5,示出了本发明还提供了一种芯片控制器,该芯片控制器包括快闪存储器识别装置上面所描述的快闪存储器识别装置。 Referring to FIG. 5, there is shown the present invention further provides a controller chip, the chip is a flash memory controller comprises a flash memory identification means identifying means described above. 其中识别装置已经做了详细的说明,在此不再赘述。 Wherein the identifying means has a detailed description is not repeated herein. 下面结合图5,描述本发明的芯片控制器的工作原理: Below in connection with FIG. 5, description of how the controller chip of the present invention:

芯片卡控制器包括控制器内部的总线时序接口51、内部数据传输通道52、 命令数据解码器53、 FLASH时序发生器54、识别装置57、识别装置57与命令数据解码器53之间的数据传输通道58、识别装置57与FLASH时序发生器54之间的数据传输通道59。 Inside the chip card controller comprises a timing controller bus interface 51, internal data transfer path 52, the command data decoder 53, FLASH timing generator 54, the data transmission between the identification means 53 57, a command recognition device 57 and the data decoder channel 58, a data transmission channel 59 between the recognition device 57 and the timing generator 54 FLASH.

在工作时,总线时序接口51将接收到的系统总线50传送的数据通过内部数据通道52直接传送至FLASH时序发生器54, FLASH时序发生器54通过数据传输通道59,从识别装置57获取该FLASH存储器的速度时序参数,并将系统总线时序转换为FLASH存储器的速度时序,然后通过FLASH存储器接口55,传送该数据到FLASH存储器56。 The data transfer system bus 50 during operation, the bus timing interface 51 transmits the received data through the internal passage 52 directly to the FLASH timing generator 54, the timing generator 54 FLASH 59 FLASH 57 acquires from the identification device via a data transmission channel the timing parameter memory speed, and a speed conversion timing system bus timing FLASH memory, FLASH memory through the interface 55 and then transmitting the data in the FLASH memory 56.

其中,命令数据解码器53对命令数据进行解析前,需要经过数据传输通道58,从识别装置57获取包括大、小页面类型、坏块标记位、容量大小等命令转换信息,从而使FLASH存储器56可以工作。 Wherein the command data decoder 53 commands data before parsing, need to go through data transmission channel 58, 57 acquiring including large and small page type, bad block flag, the capacity size of the command conversion information from the identification means, so that the FLASH memory 56 It can work.

综上,在本发明中: In summary, in the present invention:

在控制芯片的数据解码器中没有存储与芯片控制器相连接的、FLASH存储器关键参数的情况下,通过测试的方法,自适应地获取FLASH存储器的多个关键参数,从而,控制芯片能够依据关键参数实现对FLASH存储器的控制。 No memory chip and the controller chip is connected to a control data decoder, a case where key parameters FLASH memory, by the method of testing a plurality of adaptively acquiring key parameters of the FLASH memory, so that, based on the control chip can be critical parameters to achieve control of the FLASH memory.

本说明书中的各个实施例均采用递进的方式描述,每个实施例重点说明的都是与其他实施例的不同之处,各个实施例之间相同相似的部分互相参见即可。 In this specification various embodiments are described in a progressive way, differences from the embodiment and the other embodiments each of which emphasizes embodiment, the same portions similar between the various embodiments refer to each other. 对于系统实施例而言,由于其与方法实施例基本相似,所以描述的比较简单,相关之处参见方法实施例的部分说明即可。 For embodiments of the system, since the method of the embodiment which is substantially similar, the description is relatively simple, see Methods section of Example place related to embodiments described.

以上对本发明所提供的一种快闪存储器类型识别方法、识别装置,进行了 A flash memory of the above type identification method of the present invention provides identification means, were

上实施例的说明只是用于帮助理解本发明的方法及其核心思想;同时,对于本领域的一般技术人员,依据本发明的思想,在具体实施方式及应用范围上均会有改变之处,综上所述,本说明书内容不应理解为对本发明的限制。 The description of the embodiments only used to help understand the method and core idea of ​​the present invention; while those of ordinary skill in the art, according to the ideas of the present invention, in the embodiments and application scopes change place, Therefore, the specification shall not be construed as limiting the present invention.

Claims (10)

1、一种快闪存储器识别方法,其特征在于,在所述快闪存储器上电复位后,执行如下步骤:向所述快闪存储器发出小页面读指令,并检测该指令是否执行,若是,则确定所述快闪存储器支持的读命令类型为小页面类型;若否,则确定所述快闪存储器支持的读命令类型为大页面类型;应用所述快闪存储器支持的读命令类型进行所述快闪存储器的坏块读取测试,并标记出坏块位置;分别应用多个读写时序进行快闪存储器的读写测试,并分析测试结果,获取该存储器的速度时序;预置所述快闪存储器的多个测试容量地址,并向所述测试容量地址发出写指令并检测,依据执行结果确定所述快闪存储器容量;以及,存储包括有所述读命令类型、速度时序、坏块位置、存储器容量的参数值。 1. A method of identifying a flash memory, wherein, in the flash memory after the power-on reset, perform the following steps: issuing a read command to a small page of the flash memory, and detects whether the instruction is executed, and if so, determining that the flash memory read command types supported by small page type; if not, determining that the flash memory read command type supported by a large page type; be applied to the flash memory read command types supported bad block of said flash memory read test, and mark the location of bad blocks, respectively; a plurality of applications read and write timing of read and write test of the flash memory, and analyze the test results, to acquire the timing of the speed of memory; said preset a plurality of addresses of the flash memory capacity of the test, to test the capacity of a write command and address that detects, determines the capacity of the flash memory according to the execution result; and storing said read command including the type, speed, timing, bad block position, the value of the parameter memory capacity.
2、 根据权利要求1所述的快闪存储器识别方法,其特征在于,获取该快闪存储器的速度时序进一步包括如下步骤:不同频率的速度时序读写测试:应用所述多个读写时序中,两相邻频率的速度时序进行存储器的读写测试,若其中的小频率速度时序测试成功,而大频率速度时序的测试失败,则执行中间频率的速度时序读写测试的步骤;中间频率的速度时序读写测试:以所述两相邻频率和的均值作为中间频率,应用该中间频率的速度时序对存储器进行读写测试,若测试成功,则依据所述中间频率的速度时序确定存储器的速度时序,若失败,则执行重新确定两相邻频率的速度时序的步骤;重新确定两相邻频率的速度时序:以所述小频率速度时序、中间频率的速速时序作为两相邻频率的速度时序,并返回中间频率的速度时序读写测试的步骤。 2. The flash memory identification method according to claim 1, characterized in that, to obtain the flash memory further comprises the step of timing the speed: speed reading and writing test sequence of different frequencies: the plurality of read and write timing of the application , the speed of two adjacent frequency timing memory read and write test, if the speed of the timing in which the frequency a small test is successful, a large frequency and timing of the speed test fails, the read and write timing step speed test performed an intermediate frequency; an intermediate frequency timing speed reading and writing tests: two adjacent to the intermediate frequency and the average frequency, the speed of the application timing of the intermediate frequency to the memory read and write test, if the test is successful, the memory timing is determined depending on the speed of the intermediate frequency speed timing, if failed, the speed step two adjacent timing re-determined frequency; re-timing determining two adjacent frequency speed: speed at the small timing frequency, an intermediate frequency as the timing of swift two adjacent frequency speed timing, write timing and returns to step speed test an intermediate frequency.
3、 根据权利要求2所述的快闪存储器识别方法,其特征在于,所述测试容量地址为2幂指数,并且,确定所述快闪存储器的容量进一步包括:向所述多个测试容量地址中的两相邻地址发出写指令后,若其中的小地址写成功,而大地址写失败,则依据小地址确定所述存储容量。 3, the flash memory of the identification method according to claim 2, characterized in that said test address capacity of exponent 2, and determines the capacity of the flash memory further comprises: a plurality of addresses to test capacity two adjacent address after the write command is issued, if the write address wherein a small success, but large write address fails, the storage capacity is determined based on the small address.
4、 根据权利要求3所述的快闪存储器识别方法,其特征在于,所述读写时序由不同频率的时钟所产生。 4, flash memory according to claim recognition method according to claim 3, wherein said read and write timing clock generated by the different frequencies.
5、 一种快闪存储器识别装置,其特征在于,所述快闪存储器包括: 读命令类型判断模块,用于向所述快闪存储器发出小页面读指令,并检测该指令是否执行,若是,则确定所述快闪存储器支持的读命令类型为小页面类型;若否,则确定所述快闪存储器支持的读命令类型为大页面类型;坏块位置确定模块,用于应用所述快闪存储器支持的读命令类型进行所述快闪存储器的坏块读取测试,并标记出坏块的位置;速度时序获取模块,用于分别应用多个读写时序进行快闪存储器的读写测试,并分析测试结果,获取该存储器的速度时序;存储器容量确定模块,用于预置所述快闪存储器的多个测试容量地址,并向所述测试容量地址发出写指令并检测,依据执行结果确定所述快闪存储器容量;以及,参数值存储模块,用于存储包括有所述读命令类型、速度时序、 5. A flash memory device identification, wherein said flash memory comprises: a read command type determining module, for sending the page to the small flash memory read instruction, and to detect whether the instruction is executed, and if so, determining that the flash memory read command types supported by small page type; if not, determining that the flash memory type supported by a large page read command type; bad block location determination module for use of the flash memory supports read command types bad blocks of the flash memory read test, and mark the location of bad blocks; speed timing acquisition modules for applying a plurality of read and write timing of the read and write test of the flash memory, and analyze the test results, the timing of the acquisition rate of the memory; memory capacity determination module configured to preset a plurality of addresses of the flash memory capacity of the test, to test the capacity of the write command is issued, and the address is detected, it is determined based on the results of capacity of the flash memory; and a parameter value storage module for storing a read command including the type, speed, timing, 坏块位置、 存储器容量的参数值。 Bad block location, the parameter value of the memory capacity.
6、 根据权利要求5所述的快闪存储器识别装置,其特征在于,所述速度时序获^^莫块进一步包括:不同频率的速度时序读写测试单元:用于应用所述多个读写时序中,两相邻频率的速度时序进行存储器的读写测试,若其中的小频率速度时序测试成功,而大频率速度时序的测试失败,则选通中间频率的速度时序读写测试单元;中间频率的速度时序读写测试单元:用于以所述两相邻频率的均值作为中间频率,应用该中间频率的速度时序对存储器进行读写测试,若测试成功,则依据所述中间频率的速度时序确定存储器的速度时序,若失败,则选通重新确定两相邻频率的速度时序单元;重新确定两相邻频率的速度时序单元:用于以所述小频率速度时序、中间频率的速速时序作为两相邻频率的速度时序,并选通中间频率的速度时序读写测试单元。 6, a flash memory according to claim recognition apparatus according to claim 5, wherein said velocity is eligible ^^ Mo timing block further comprises: a timing write speed test cells of different frequencies: the plurality of read-write applications for timing, the timing of two adjacent frequency speed read and write tests of memory, wherein if the test is successful small timing clock speed, and the speed of a large frequency timing test fails, the strobe timing of reading and writing speed of the intermediate frequency test unit; intermediate velocity test unit write timing frequency: as the mean for the two adjacent frequency as the intermediate frequency, the application timing of the intermediate frequency speed memory read and write test, if the test is successful, based on the speed of the intermediate frequency determining the speed of the memory timing sequence, if fails, then re-determined gating rate timing means two adjacent frequency; re-timing unit determining the speed of two adjacent frequency: for haste to the small speed timing frequency, an intermediate frequency timing timing as the speed of two adjacent frequency, timing and speed of reading and writing test strobe unit an intermediate frequency.
7、 根据权利要求6所述的快闪存储器识别装置,其特征在于,所述测试容量地址为2指数幂,并且,所述存储器容量确定模块进一步包括:写指令发出单元,用于分别向所述多个测试容量地址中的两相邻地址发出写指令;检测单元,用于判断针对于所述两相邻地址的写指令是否执行成功,若其中的小地址写成功,而大地址写失败,则依据小地址确定所述存储器容量。 7, a flash memory according to claim recognition apparatus according to claim 6, characterized in that said test address capacity exponential power of 2, and the memory capacity determination module further comprises: a write instruction issuing unit for respectively the said plurality of addresses in the capacity test of two adjacent address write command is issued; detecting means for determining for a write command to the two adjacent address executed successfully, wherein when the small address is written successfully, the address write failure and large determining that the memory capacity is small based on the address.
8、 根据权利要求7所述的快闪存储器识别装置,其特征在于,所述读写时序由不同频率的时钟所产生。 8, a flash memory recognition apparatus as claimed in claim 7, wherein said read and write timing clock generated by the different frequencies.
9、 一种芯片控制器,其特征在于,所述芯片控制器包括快闪存储器识别装置,所述快闪存储器识别装置包括:读命令类型判断模块,用于向所述快闪存储器发出小页面读指令,并检测该指令是否执行,若是,则确定所述快闪存储器支持的读命令类型为小页面类型;若否,则确定所述快闪存储器支持的读命令类型为大页面类型;坏块位置确定模块,用于应用所述快闪存储器支持的读命令类型进行所述快闪存储器的坏块读取测试,并标记出坏块的位置;速度时序获取模块,用于分别应用多个读写时序进行快闪存储器的读写测试,并分析测试结果,获取该存储器的速度时序;存储器容量确定模块,用于预置所述快闪存储器的多个测试容量地址,并向所述测试容量地址发出写指令并;f企测,依据执行结果确定所述快闪存储器容量;以及,参数值存储模块, 9. A chip controller, wherein said controller comprises a flash memory chip identifying means, said flash memory identification means comprises: a read command type determining module, for sending to a small page of the flash memory read command, and to detect whether the instruction execution, if yes, determining that the flash memory read command types supported by small page type; if not, determining that the flash memory read command type supported by a large page type; bad block position determining module, for applying the read commands supported by the flash memory type bad blocks of the flash memory read test, and mark the location of bad blocks; speed timing acquisition modules for a plurality of applications read and write timing of read and write test of the flash memory, and analyze the test results, the timing of the acquisition rate of the memory; memory capacity determination module configured to preset a plurality of addresses of the flash memory capacity of the test, and the test address write command is issued and capacity; F enterprises measured, determining the capacity of the flash memory according to the execution result; and a parameter storage module, 于存储包括有所述读命令类型、速度时序、坏块位置、 存储器容量的参数值。 Storing said read command including the type, speed, timing, bad block location, the parameter value of the memory capacity.
10、 根据权利要求9所述的芯片控制器,其特征在于,所述速度时序获取模块进一步包括:不同频率的速度时序读写测试单元,用于应用所述多个读写时序中,两相邻频率的速度时序进行存储器的读写测试,若其中的'J、频率速度时序测试成功,而大频率速度时序的测试失败,则选通中间频率的速度时序读写测试单元;中间频率的速度时序读写测试单元:用于以所述两相邻频率的均值作为中间频率,应用该中间频率的速度时序对存储器进行读写测试,若测试成功,则依据所述中间频率的速度时序确定存储器的速度时序,若失败,则选通重新确定两相邻频率的速度时序单元;重新确定两相邻频率的速度时序单元:用于以所述小频率速度时序、中间频率的速速时序作为两相邻频率的速度时序,并选通中间频率的速度时序读写测试单元。 10, the controller chip according to claim 9, wherein said speed timing acquisition module further comprises: a timing different frequencies write speed test unit for applying the plurality of read and write timing, the two phases o test speed read and write timing frequency of a memory, wherein if the 'J, the test is successful the timing clock speed, and the speed of a large frequency timing test fails, the strobe timing of reading and writing speed of the intermediate frequency test unit; speed of the intermediate frequency write timing test unit: as the mean for the two adjacent frequency as the intermediate frequency, the application timing of the intermediate frequency speed memory read and write test, if the test is successful, the memory is determined depending on the speed of the intermediate frequency timing speed timing, if fails, then re-determined gating rate timing means two adjacent frequency; re-timing unit determining the speed of two adjacent frequency: means for timing the speed of the small frequency, an intermediate frequency as timing of swift two adjacent frequency speed timing, and write strobe timing test speed of an intermediate frequency unit.
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