CN106165120B - The manufacture method of solar cell and solar cell - Google Patents
The manufacture method of solar cell and solar cell Download PDFInfo
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- CN106165120B CN106165120B CN201580017041.4A CN201580017041A CN106165120B CN 106165120 B CN106165120 B CN 106165120B CN 201580017041 A CN201580017041 A CN 201580017041A CN 106165120 B CN106165120 B CN 106165120B
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- 238000000034 method Methods 0.000 title claims description 34
- 238000004519 manufacturing process Methods 0.000 title claims description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 134
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 130
- 239000010703 silicon Substances 0.000 claims abstract description 130
- 239000000463 material Substances 0.000 claims abstract description 14
- 229910021419 crystalline silicon Inorganic materials 0.000 claims abstract description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 58
- 239000000758 substrate Substances 0.000 claims description 44
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 30
- 239000002070 nanowire Substances 0.000 claims description 23
- 239000002210 silicon-based material Substances 0.000 claims description 19
- 238000010276 construction Methods 0.000 claims description 18
- 239000013078 crystal Substances 0.000 claims description 10
- 238000003475 lamination Methods 0.000 claims description 10
- 230000005611 electricity Effects 0.000 claims description 8
- 238000001994 activation Methods 0.000 claims description 6
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical group O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 claims description 6
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 4
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 3
- 238000009832 plasma treatment Methods 0.000 claims description 3
- GRPQBOKWXNIQMF-UHFFFAOYSA-N indium(3+) oxygen(2-) tin(4+) Chemical compound [Sn+4].[O-2].[In+3] GRPQBOKWXNIQMF-UHFFFAOYSA-N 0.000 claims 1
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- 229910052681 coesite Inorganic materials 0.000 description 4
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- 238000005984 hydrogenation reaction Methods 0.000 description 4
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- 239000007943 implant Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052682 stishovite Inorganic materials 0.000 description 4
- 229910052905 tridymite Inorganic materials 0.000 description 4
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- 239000000377 silicon dioxide Substances 0.000 description 3
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- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
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- 239000004020 conductor Substances 0.000 description 2
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- 238000005530 etching Methods 0.000 description 2
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- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
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- 229910052709 silver Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
- H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
- H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/042—PV modules or arrays of single PV cells
- H01L31/043—Mechanically stacked PV cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
- H01L31/0682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/548—Amorphous silicon PV cells
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- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Life Sciences & Earth Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Sustainable Energy (AREA)
- Crystallography & Structural Chemistry (AREA)
- Sustainable Development (AREA)
- Chemical & Material Sciences (AREA)
- Photovoltaic Devices (AREA)
Abstract
The solar cell (300) of the present invention is, for example, following series solar energy batteries, and the series solar energy battery is laminated with：Upper cell (100) located at light incident side and the lower battery (200) located at the lower section of the upper cell (100), and select the big material of the energy gap of the energy gap lower part battery (200) of upper cell (100).In the present invention, the thickness of the crystallizing silicon layer of upper cell (100) is set to less than 30 μm, preferably 5 μm~10 μm of scope.In the case that the thickness of n-type crystalline silicon layer is less than 10 μm, the auger recombination of the carrier in crystallizing silicon layer is substantially suppressed, as a result, open-circuit voltage significantly improves.Further, since output can be separately taken out from upper cell (100) and lower battery (200), thus, it is not necessary to obtain the matching of the generation current required for being connected in series in type concatenation type battery.
Description
Technical field
The present invention is more specifically the solar-electricity more previous on photoelectric transformation efficiency on solar battery technology
The high silicon solar cell in pond and its manufacture method.
Background technology
In the field of solar cell, it is known that a kind of concatenation type (more maqting types) solar cell, it is laminated with multiple
Photoelectric conversion part, scheme to improve photoelectric transformation efficiency (for example, referring to patent by carrying out opto-electronic conversion to the sunshine of wide band
Document 1~3).In order to further improve the photoelectric transformation efficiency of such a series solar energy battery, it is necessary to further increase light
Utilization ratio improves output current.
As the solar cell using monocrystalline silicon wafer crystal, the technology for having realized high-photoelectric transformation efficiency at present is, will be non-
Crystal silicon be deposited on the two sides of monocrystalline silicon wafer crystal heterogeneous engagement solar cell and in the face of the opposite side of incident light side formed with
Emitter-base bandgap grading and the back contact solar battery in back surface field region (BSF regions).
In order to further improve the photoelectric transformation efficiency of concatenation type silicon solar cell, to the auger recombination in crystallizing silicon layer
Suppression turn into important problem.As one of method to solve the problem, have what the thickness of crystallizing silicon layer was thinned
Method, crystallizing silicon layer is thinned to 100 μm or so the solar-electricities that can obtain higher photoelectric transformation efficiency in level in studying
Pond.
[prior art document]
[patent document]
Patent document 1：Japanese Unexamined Patent Publication 10-335683 publications
Patent document 2：Japanese Unexamined Patent Publication 2001-267598 publications
Patent document 3：Japanese Unexamined Patent Publication 2009-260310 publications
The content of the invention
[the invention problem to be solved]
As described above, in order to further improve the photoelectric transformation efficiency of concatenation type silicon solar cell, by the thickness of crystallizing silicon layer
Degree is thinned, quite effective to suppressing the auger recombination in crystallizing silicon layer.If however, conversely the thickness of crystallizing silicon layer is thinned,
It can be shortened because of light absorbs length, and cause the reduction of short-circuit current density, if integrally evaluating solar cell, whether there is
Method reaches the problem of desired photoelectric transformation efficiency.Moreover, in the manufacturing step of solar cell, also require exploitation to
The damaged method of thin crystallization silicon layer is not made.
The present invention in view of this kind of problem and complete, its object is to, there is provided a kind of concatenation type silicon solar cell and its system
Method is made, wherein, the crystallizing silicon layer of upper cell is thinned, suppresses the auger recombination in crystallizing silicon layer, and in manufacturing step
Also thin crystallization silicon layer will not be made damaged, and photoelectric transformation efficiency is high.
[means to solve the problem]
In order to solve the above problems, solar cell of the invention is characterised by：Upper cell is located at the interarea of matrix
On, the upper cell constructs including lamination, and lamination construction sequentially has transparency conducting layer, the 1st conductivity type from light incident side
Amorphous silicon material layer, the 2nd conductivity type crystallizing silicon layer opposite with the 1st conductivity type, the 2nd conductivity type amorphous silicon layer, in the top
The surface of battery is provided with smooth surface electrode, and the matrix is provided with backplate, the 2nd conductivity type silicon metal of the upper cell
The thickness of layer is less than 30 μm.
Preferably it is configured to, the thickness of the 2nd conductivity type crystallizing silicon layer of the upper cell is 3 μm~30 μm.
In addition, being preferably configured to, the thickness of the 2nd conductivity type crystallizing silicon layer of the upper cell is 4 μm~20 μm.
Preferably it is configured to, the thickness of the 2nd conductivity type crystallizing silicon layer of the upper cell is 5 μm~10 μm.
In one form, the upper cell is to have between the 1st conductivity type amorphous silicon material layer and the 2nd conductivity type crystallizing silicon layer
Standby i type amorphous silicon material layers.
In addition, in a form, the upper cell is between the 2nd conductivity type crystallizing silicon layer and the 2nd conductivity type amorphous silicon layer
Possess i type amorphous silicon layers.
Also, in a form, possesses insulating properties transparent passivating layer between the upper cell and the matrix.
Preferably it is configured to, the insulating properties transparent passivating layer is the layer being made up of Si oxide or aluminum oxide.
For example, the matrix is to be made up of monocrystalline silicon.
In one form, the matrix is made up of monocrystalline silicon, is possessed between the upper cell and the matrix by tin indium oxide (ITO)
The layer of composition.
In addition, in a form, the matrix is the lower battery being made up of monocrystalline silicon, and the upper cell side is the 2nd conductivity type
Region, formed with the 1st conductive area, the back side of the lower battery is provided with the backplate in below and is concatenated.
Also, in a form, the lower battery in the upper cell side of the 2nd conductive area possess donor concentrations compared with
The 2nd high conductive layer of 2nd conductive area.
In one form, the upper cell has the 2nd transparency conducting layer located at the downside of the 2nd conductivity type amorphous silicon layer.
Also, in a form, when observing the upper cell from top, the surface of the 2nd transparency conducting layer is in have bus
Portion and from the bus portion extension multiple finger sections comb teeth-shaped and expose.
In one form, be provided with the surface of the upper cell the 1st comb teeth-shaped that is electrically connected to the transparency conducting layer by
Smooth surface electrode and be electrically connected to the 2nd transparency conducting layer the 2nd comb teeth-shaped smooth surface electrode.
It is also, conductive formed with the 1st conductive area and secondary the 2nd in the rear side of the lower battery in a form
Type region, the 1st conductive area are formed as the comb teeth-shaped with bus portion and multiple finger sections from bus portion extension, should
Secondary 2nd conductive area is formed as the comb teeth-shaped with bus portion and multiple finger sections from bus portion extension, and donor
Concentration is high compared with the 2nd conductive area, the finger section of the 1st conductive area and the finger section of the conductive area of secondary the 2nd
Interacted and configured with predetermined distance.
In one preferable form, the 1st broach for being electrically connected to the 1st conductive area is provided with the back side of the lower battery
The backplate of shape and be electrically connected to the conductive area of secondary the 2nd the 2nd comb teeth-shaped backplate.
Also, in a preferable form, when observing the solar cell from top, the smooth surface electrode of the 1st comb teeth-shaped
Bus portion is located at parallel position, the light of the 2nd comb teeth-shaped with the bus portion of the backplate of the 2nd comb teeth-shaped in a side
The bus portion of face electrode is located at parallel position with the bus portion of the backplate of the 1st comb teeth-shaped in another side.
For example, the transparency conducting layer located at the upper cell is tin indium oxide (ITO).
Preferably it is configured to, the transparency conducting layer located at the light incident side of the upper cell doubles as antireflection layer.
Preferably it is configured to, the 2nd conductivity type crystallizing silicon layer of the upper cell is designed as following thickness, and the thickness makes on this
Portion's battery is identical with the generation current of the lower battery.
Also, preferably it is configured to, when observing the solar cell from top, what the upper cell possessed has electrically conducting transparent
Layer, the 1st conductivity type amorphous silicon material layer, the 2nd conductivity type crystallizing silicon layer, the lamination of the 2nd conductivity type amorphous silicon layer are configured to array
Construction, the array structure have be divided into be aligned in a plurality of nano wire or wall of predetermined distance two-dimensional arrangements it is set
Direction and with the nm wall of multiple wall-like of predetermined distance two-dimensional arrangements, the thickness of the diameter of the nano wire or the nm wall, in
It is below 10nm on the position of 2nd conductivity type crystallizing silicon layer.
Preferably it is configured to, the nano wire or the nm wall to adjoin each other is isolated by insulating properties material.
The manufacture method of the solar cell of the present invention, it is in the manufacture for the solar cell for possessing upper cell on matrix
Method, the manufacture method include：1st step, it makes primary 2nd conduction type silicon crystalline substrate with being somebody's turn to do with less than 400 DEG C of temperature
The surface of matrix is bonded each other, and the conduction type silicon crystalline substrate of primary the 2nd is in surface region formed with the 2nd conductivity type non-crystalline silicon
Layer, and in being provided with transparency conducting layer on the 2nd conductivity type amorphous silicon layer, the matrix is in surface formed with transparency conducting layer or exhausted
Edge transparent passivating layer；Second step, the conduction type silicon crystalline substrate of primary the 2nd is thinned to below 30 μm of thickness by it from the back side,
The 2nd conductivity type crystallizing silicon layer as the upper cell.
Preferably be configured to, the matrix be in surface region formed with donor concentrations 2nd conductive layer high compared with blocks, and
In the conduction type silicon crystalline substrate of secondary the 2nd that insulating properties transparent passivating layer is provided with the 2nd conductive layer.
Preferably it is configured to, the 1st step possesses the surface to the conduction type silicon crystalline substrate of the primary the 2nd and the table of the matrix
At least one of face implements the secondary step of surface activation process.
For example, the surface activation process carries out at least one of plasma treatment or ozone processing.
For example, the transparency conducting layer is tin indium oxide (ITO), the insulating properties transparent passivating layer is by Si oxide or alumina
The layer that compound is formed.
In one form, possess in the 1st step previous dynasty conduction type silicon crystalline substrate of primary the 2nd surface region implantation both
Determine the step of hydrogen of dosage is to form hydrogen ion implant layer, in the second step, by the hydrogen ion implant layer apply machinery or
Thermal shock, the 2nd conductivity type crystallizing silicon layer is set to be peeled off from the conduction type silicon crystalline substrate of primary the 2nd, to be used as the upper cell
2nd conductivity type crystallizing silicon layer.
In addition, in a form, possesses third step after the second step, in this third step, in the 2nd conductivity type knot
The top of crystal silicon layer forms the 1st conductivity type amorphous silicon material layer opposite with the 2nd conductivity type.
Also, in a form, the third step possesses before the formation of the 1st conductivity type amorphous silicon material layer, by the 2nd
Conductivity type crystallizing silicon layer is divided into the secondary step of nano wire or nm wall, and the wherein nano wire is with predetermined distance two-dimensional arrangements
A plurality of nano wire, and be aligned in a diameter of below 10nm on the position of the 2nd conductivity type crystallizing silicon layer, the nm wall for wall
Set direction and with the nm wall of multiple wall-like of predetermined distance two-dimensional arrangements, and in the position of the 2nd conductivity type crystallizing silicon layer
Upper thickness is below 10nm.
[The effect of invention]
The solar cell of the present invention is significantly by the 2nd conductivity type knot of upper cell using the composition compared with prior art
The thinned construction of crystal silicon layer.As a result, compared with the 2nd conductivity type crystallizing silicon layer is set as into 100 μm of composition, upper cell
Open-circuit voltage become to be higher by more than 0.1V, using high voltage output current, thus photoelectric transformation efficiency can be improved.
In addition, in the case that the present invention is set into series solar energy battery, due to can be from upper cell and bottom electricity
Pond separately exports, and therefore, there is no need to obtain the matching of the generation current required for being connected in series in type concatenation type battery.
Moreover, the manufacture method of the solar cell of the present invention, to apply so-called " fitting " technology, enters in less than 400 DEG C
" fitting " of row upper cell and matrix or lower battery, therefore the feelings that hydrogen-free departs from from hydrogenated amorphous silicon layer and reduces film quality
Condition, will not also the defects of new be produced to crystallizing silicon layer.Therefore, in the case that the present invention is set into series solar energy battery,
The deterioration of the heterogeneous engaging battery with concatenationization will not be produced.
Brief description of the drawings
Fig. 1 is the profile for illustrating the summary of the essential structure of the concatenation type silicon solar cell of the present invention.
Fig. 2 is the figure of the thickness dependence of the upper cell n-type crystallizing silicon layer of display photoelectric transformation efficiency.
Fig. 3 is the figure of the analog result of the thickness dependence of the n-type crystallizing silicon layer of the open-circuit voltage of display upper cell.
Fig. 4 is the figure of the form of the smooth surface electrode possessed for illustrating the solar cell of the present invention.
Fig. 5 is to illustrate the form from smooth surface electrode during light incident side (top) observation of the solar cell of the present invention
Figure (Fig. 5 (A)) and explanation from rear side (lower section) observe when backplate form figure (Fig. 5 (B)).
Fig. 6 is to show the dotted line display part in the figure of Fig. 5 (A) and Fig. 5 (B) when being set to 2 terminal concatenation type battery structure
The figure of the summary of the profile construction divided.
Fig. 7 is the flow chart of the process example of the solar cell of the manufacture present invention.
Fig. 8 is for illustrating that upper cell is to be divided into the nm wall of multiple wall-like of predetermined distance two-dimensional arrangements
The schematic perspective view of the composition of the series solar energy battery of the situation of array structure.
Fig. 9 has for observation to be divided into the array structure of the nm wall of the silicon of multiple wall-like of predetermined distance two-dimensional arrangements
The transmission electron microscope image of a part for the upper cell made.
Figure 10 is the reflectivity for the array structure (A) that display is divided into nm wall and is embedded to each other absolutely in nm wall
Edge material is SiO2Array structure (B) reflectivity wavelength dependency figure.
Embodiment
Below, the solar cell and its manufacture method of the present invention are illustrated referring to the drawings.Furthermore explanation afterwards
In, if the 1st conductivity type is p-type, and sets the 2nd conductivity type and illustrated as n-type, but is alternatively opposite relation, that is, it is conductive to set the 1st
Type is n-type, and sets the 2nd conductivity type as p-type.In addition, in explanation afterwards, " amorphous silicon material layer " is carried out as amorphous silicon layer
Illustrate, in addition, can also be used as noncrystalline SiO layer or noncrystalline SiN layer etc..
Afterwards, the solar cell of the present invention is illustrated for the situation of series solar energy battery, but differs and be set to
Concatenation type.The solar cell of the present invention, which is alternatively, does not possess lower battery, in the solar energy that upper cell is provided with matrix
Battery.That is, " lower battery " is not necessarily intended to play a role as solar cell.
(summary of the essential structure of series solar energy battery of the invention)
Fig. 1 is the profile for illustrating the summary of the basic structure of the concatenation type silicon solar cell of the present invention.Solar energy
Battery 300 is that will be located at the upper cell 100 of light incident side (upside of figure) and under the lower section of the upper cell 100
The series solar energy battery that the lamination of portion's battery 200 forms.
Upper cell 100 uses the 1st n-type silicon crystalline substrate 10, and is manufactured by process example described later.The upper cell
100 be sequentially to possess transparency conducting layer 110, p-type amorphous silicon layer 120, n as p-type amorphous material layer from light incident side
Type crystallizing silicon layer 130, n-type amorphous silicon layer 140.In example shown in Fig. 1, the downside of n-type amorphous silicon layer 140 is provided with the 2nd
Transparency conducting layer 150, can be with lower battery by using the transparency conducting layer 150 of transparency conducting layer 110 and the 2nd as 2 electrode layers
200 independently take out the output of upper cell 100.Transparency conducting layer 110 is for example made up of tin indium oxide (ITO), can also make it
As antireflection layer.Furthermore the smooth surface electrode (not shown) on the surface on being located at upper cell 100, is treated aftermentioned.
Furthermore p-type amorphous material layer can also be set to the noncrystalline SiO layer of p-type and the noncrystalline SiN layer of p-type to substitute the p-type
Amorphous silicon layer 120.In addition, i type amorphous materials can be also provided as between p-type amorphous silicon layer 120 and n-type crystallizing silicon layer 130
The i type amorphous silicon layers of layer, also may replace i types amorphous silicon layer and set the noncrystalline SiO layer of i types or the noncrystalline SiN layer of i types.
Furthermore the p-type amorphous silicon layer 120, i types amorphous silicon layer, n-type amorphous silicon layer 140 in being all set as in most cases
The noncrystalline layer being hydrogenated.This is in the feelings that p-type amorphous silicon layer 120 and i types amorphous silicon layer are above-mentioned other amorphous silicon material layers
During condition similarly.
Lower battery 200 is the n-type silicon crystalline substrate 20 using the 2nd, and is manufactured by process example described later.Bottom electricity
Pond 200 is made up of monocrystalline silicon, and upper cell side is n-type region 210, and in below, (i.e. the rear side of solar cell) is provided with
P-type area 220 as emitter layer.
In addition, in the example shown in the figure, the upper cell side of the n-type region 210 of lower battery 200 is provided with confession
The bulk concentration n-layer 230 high compared with the n-type region as blocks, and it is used as surface field layer (FSF).Also, with as transmitting
The p-type area 220 of pole layer abuts to form donor concentrations 2nd n-layer 240 high compared with the n-type region as blocks, to make
For back surface field layer (BSF).
1st backplate 260 and the 2nd backplate 270 are electrically connected to emitter layer i.e. p-type area via insulating film 250
The n-layer 240 in domain 220 and the 2nd it is each, by being the n-layer 240 of p-type area 220 and the 2nd using emitter layer as 2 electrodes
Layer, the output of lower battery 200 can be independently taken out with upper cell 100.
Furthermore in form described later, p-type area 220 is formed as having bus portion and extended from the bus portion multiple
The comb teeth-shaped of finger section, and the 2nd n-type region 240 is similarly formed as having bus portion and extended from the bus portion more
The comb teeth-shaped of individual finger section, and the finger section of p-type area 220 and the finger section of the 2nd n-type region 240 is handed over predetermined distance
Mutually configure.
Here, the bus portion in the p-type area 220 is not necessarily intended to the conductivity type for p-type, but for convenience, this is total
Line portion is also included referred to as " p-type area ".Equally, the bus portion in the 2nd n-type region 240, is also not necessarily intended to as n-type
Conductivity type, but for convenience, the bus portion is also included referred to as " n-type region ".In other words, the hand of p-type area 220
The finger section of finger portion and the 2nd n-type region 240 is respectively " p-type " and " n-type " ", it can also make these finger sections be in predetermined distance
Striated interaction configuration.
The layer shown in symbol 160 between upper cell 100 and lower battery 200, it is insulating properties transparent passivating layer,
And it is the layer for being used to be bonded in manufacturing process described later.Insulating properties transparent passivating layer 160 is, for example, by Si oxide, alumina
The layer that thing is formed.
Composition and thickness of each layer of upper cell 100 etc., such as be designed in the following manner.Transparency conducting layer 110
Total thickness for 0.1 μm or so of ITO, p-type amorphous silicon layer 120 and i type amorphous silicon layers is 0.01 μm or so, n-type crystallizing silicon layer 130
Thickness be less than 30 μm, the total thickness of i types amorphous silicon layer and n-type amorphous silicon layer 140 is 0.01 μm or so, the 2nd transparency conducting layer
150 be 0.1 μm or so of ITO.Furthermore the thickness of the n-type crystallizing silicon layer of upper cell is preferably 3 μm~30 μm, more preferably 4 μm
~20 μm, most preferably 5 μm~10 μm.Treated on its reason aftermentioned.
Thickness of each layer of lower battery 200 being made up of monocrystalline silicon etc., such as can be designed in the following manner.As
The n-type region 210 of blocks, its thickness is 200~500 μm or so and ratio resistance is 1 Ω cm or so, the p as emitter layer
Type region 220, its acceptor density are 5 × 1019cm-3Left and right, and thickness is 2~3 μm or so, as surface field layer (FSF)
N-layer 230, its donor concentrations are 1 × 1019cm-3Left and right, and thickness is 0.1~1 μm or so, as back surface field layer (BSF)
The 2nd n-layer 240, its donor concentrations be 5 × 1019cm-3~1 × 1020cm-3Left and right, and thickness is 1~2 μm or so.
Furthermore it can suitably use SiO as insulating film 2502.In addition, SiO2Also can suitably be used in located at top electricity
Insulating properties transparent passivating layer 160 between pond 100 and lower battery 200, its thickness are, for example, 0.1 μm or so.
In addition, smooth surface electrode described later or the backplate 260,270 are to being formed at comprehensively using sputter and evaporation
Metal (such as Al or Ag etc.) carry out pattern processing and formed, or using Al, Ag etc. paste carry out screen painting after sinter
Formed.
(thickness of the n-type crystallizing silicon layer of upper cell)
Fig. 2 is the figure of the analog result of the thickness dependence of the upper cell n-type crystallizing silicon layer of display photoelectric transformation efficiency.
In the simulation, if the thickness of lower battery is 300 μm, and the thickness of the n-type crystallizing silicon layer of upper cell is asked as parameter
Take photoelectric transformation efficiency.According to the result, the photoelectricity when thickness of the n-type crystallizing silicon layer of upper cell is 100 μm of situation turns
Change efficiency, roughly equal (23.5%) with situation that the thickness of n-type crystallizing silicon layer is 1 μm, if thickness more than 100 μm, the value
Decline.
The thickness of n-type crystallizing silicon layer is less than 30 μm, more than 24% photoelectric transformation efficiency can be obtained, if n-type silicon metal
Scope of the thickness of layer at 3~30 μm, then it can obtain more than 24% photoelectric transformation efficiency.In addition, in the thickness of n-type crystallizing silicon layer
Spend for the photoelectric transformation efficiency more than 24.1% can be obtained in the range of 4 μm~20 μm, can be obtained in the range of 5 μm~10 μm
Photoelectric transformation efficiency more than 24.2%.
Fig. 3 is the open-circuit voltage V of display upper cellocN-type crystallizing silicon layer thickness dependence analog result figure,
Open-circuit voltage V in figure to justify symbol to show the silicon for being assumed to blocks and obtainocValue.Fig. 3 (A) shows n-type crystallizing silicon layer
Open-circuit voltage of the thickness in the range of 1~100 μm, Fig. 3 (B) shows scope of the thickness of n-type crystallizing silicon layer at 1~10 μm
Interior open-circuit voltage.
According to the result shown in these figures, in n-type crystallizing silicon layer thickness for 10~20 μm near, open-circuit voltage, which truly has, to be carried
Height, it is less than 10 μm particularly in the thickness of n-type crystallizing silicon layer, open-circuit voltage significantly improves, and can obtain more than 0.8V value.This
The thickness of n-type crystallizing silicon layer is thinned for expression, and thus the auger recombination of the carrier in crystallizing silicon layer is substantially suppressed.
Result according to Fig. 3, it is less than 10 μm in the thickness of n-type crystallizing silicon layer, open-circuit voltage, which truly has, to be significantly improved,
On the other hand, the result according to Fig. 2, it is contemplated that opto-electronic conversion is imitated if the thickness of n-type crystallizing silicon layer becomes compared with 5 μm thinner
The fact that rate is gradually reduced, it is believed that the thickness range of optimal n-type crystallizing silicon layer is 5 μm~10 μm.
(taking out the output from upper cell and lower battery)
Fig. 4 is the figure of the form of the smooth surface electrode possessed for illustrating the solar cell of the present invention.In the form, in
The surface of upper cell 100 is provided with the 1st smooth surface electrode 170 for being electrically connected to the transparency conducting layer 110 and is electrically connected to
2nd smooth surface electrode 180 of 2 transparency conducting layers 150, using the transparency conducting layer 150 of transparency conducting layer 110 and the 2nd as 2 electrodes
Layer, the output of upper cell 100 thus can be independently taken out with lower battery 200.
Furthermore as already explained above, the output of lower battery 200 also can be by being p-type area 220 and the 2nd by emitter layer
N-layer 240 be used as 2 electrode layers, and the output of lower battery 200 can be independently taken out with upper cell 100.
Fig. 5 (A) and Fig. 5 (B) is respectively to illustrate the smooth surface from during light incident side (top) observation of solar cell 300
The figure (Fig. 5 (A)) of the form of electrode and explanation are from backplate during rear side (lower section) observation of solar cell 300
The figure (Fig. 5 (B)) of form.
As shown in Fig. 5 (A), when being observed from top, upper cell 100 is provided with the smooth surface electrode 170 of the 1st comb teeth-shaped
And the 2nd comb teeth-shaped smooth surface electrode 180.Also, the surface of the 2nd transparency conducting layer 150 of upper cell 100 is in have bus
Portion and from the bus portion extension multiple finger sections comb teeth-shaped and expose, the smooth surface electrode 170 of the 1st comb teeth-shaped is electrically connected to
The smooth surface electrode 180 of the comb teeth-shaped of transparency conducting layer the 110, the 2nd is electrically connected to the 2nd transparency conducting layer 150.
That is, when being observed from top, the surface of the 2nd transparency conducting layer 150 is in bus portion and certainly should upper cell 100
The comb teeth-shaped of multiple finger sections of bus portion extension and expose, and be provided with the 1st comb teeth-shaped for being electrically connected to transparency conducting layer 110
Smooth surface electrode 170 and be electrically connected to the 2nd transparency conducting layer 150 the 2nd comb teeth-shaped smooth surface electrode 180, thus, can
The output of upper cell 100 is independently taken out with lower battery 200.
In addition, in this form, in n-type region 240 of the rear side of lower battery 200 formed with p-type area 220 and the 2nd,
The p-type area 220 is formed as the comb teeth-shaped with bus portion and multiple finger sections from bus portion extension, the 2nd n-type area
Domain 240 is formed as the comb teeth-shaped with bus portion and multiple finger sections from bus portion extension, and donor concentrations are relatively used as block
The n-type region 210 of shape body is high, and the finger section of the finger section of p-type area 220 and the 2nd n-type region 240 is interacted with predetermined distance
Ground configures.
Also, the back side of lower battery 200 is provided with the backplate for the 1st comb teeth-shaped for being electrically connected to p-type area 220
260 and be electrically connected to the 2nd n-type region 240 the 2nd comb teeth-shaped backplate 270, thus, can be only with upper cell 100
On the spot take out the output of lower battery 200.
The construction of the smooth surface electrode of such a form, to can not ignore because upper cell 100 transparency conducting layer (110,
150) film resistance it is high and caused by situation about losing be particularly effective.Also, due to can independently take out the defeated of upper cell 100
Go out and the output of lower battery 200, therefore, there is no need to obtain both as 2 terminal concatenation type batteries being electrically connected in series
Generation current matching, so as to reduce the limitation of battery design.
In addition, in the form, because the lead-out terminal of upper cell 100 is located at incident light surface side, lower battery 200
Lead-out terminal is located at rear side, therefore in entering several batteries by group come in the case of making module, by upper cell each other or under
Portion's battery is serially connected, and the terminal of module is set to 4 terminals.
Furthermore also can be by the thickness of the crystallizing silicon layer 130 of adjustment upper cell 100, so that upper cell 100 and bottom electricity
The generation current in pond 200 becomes identical.In this case 2 terminals can also be realized.For example, upper cell and bottom can be connected in series
The output of battery and group enters in module, the output from upper cell can be also connected in series in the terminal box of module and is come from down
The output of portion's battery and be set to 2 terminals.
In order to be set to 2 terminal concatenation type battery structures, such as annexation between following electrode can be used.
Fig. 6 is the figure of the summary of the profile construction of the dotted line display portion in display Fig. 5 (A) and Fig. 5 (B) figure.First,
The thickness of 130 layers of the silicon metal of upper cell 100 is adjusted, so that the most suitable action current of upper cell 100 and lower battery 200
It is roughly equal.Then, in the form of the end of crosscutting lower battery 200 on the thickness direction in battery, by conductive material 280
Connect following buses, i.e. to take out the bus and electricity of the comb electrodes 260 of the output of the emitter stage from lower battery 200
It is connected to the bus of the comb electrodes 180 of the 2nd transparency conducting layer 150 of the n-type amorphous silicon layer side for being located at upper cell 100.
In this case, the bus for the comb electrodes to be connected is pre-configured with a manner of the same end edge as battery
Each other.That is, when solar cell 100 is observed from top, smooth surface electrode i.e. the 2nd transparency conducting layer 150 of the 2nd comb teeth-shaped is made
Bus portion be located at parallel position in another side with the bus portion that the backplate of the 1st comb teeth-shaped is the 1st backplate 260
Put.On the other hand, the smooth surface electrode of the 1st comb teeth-shaped is the back side of the bus portion with the 2nd comb teeth-shaped of the 1st transparency conducting layer 110
Electrode is that the bus portion of the 2nd backplate 270 is to be located at parallel position in another side.
When carrying out such a interelectrode connection, by voltage caused by generation current decline become fully small in a manner of enter
OK.In the case that the insulating film 250 of cell backside is the oxide-film formed by thermal oxide or plasma CVD, if considering
The end face of battery is also covered by this kind of insulating film 250, and the situation that the thickness of such as consideration battery is hundreds of μm, then with use
Thickness is that the conductive paste of more than several μm of Ag pastes etc. is preferable.If using this kind of conductive paste, as long as to be contacted with
The mode of above-mentioned two bus is coated on the end of battery and is sintered, you can makes the electricity of the connecting portion caused by generation current
Drops are fully small compared with generating voltage.
[embodiment]
Hereinafter, the summary of the manufacture method of the solar cell of the invention of the construction is illustrated by illustrating.Furthermore
The 1st conductivity type is set in following embodiments as p-type, and sets the 2nd conductivity type as n-type, but is alternatively opposite relation, that is, sets the 1st and leads
Electric type is n-type, and sets the 2nd conductivity type as p-type, as this puts as described.In addition, " amorphous silicon material layer " can also be not as non-
Crystal silicon layer, but be used as noncrystalline SiO layer or noncrystalline SiN layer etc., this point also as described as.
Fig. 7 is the flow chart of the process example of the solar cell of the manufacture present invention.First, the n-type monocrystalline silicon of 2 is prepared
Substrate (10,20).It is without particular limitation to the thickness of silicon substrate, generally 200~500 μm.1st n-type silicon crystalline substrate 10
Make and use for upper cell, the 2nd n-type silicon crystalline substrate 20 makes for lower battery to be used.In following embodiments, the 1st n-type
Even one side mirror finish can be used in silicon crystalline substrate 10, but the 2nd n-type silicon crystalline substrate 20 is to be added using two-sided minute surface
Work.In addition, the ratio resistance value of silicon substrate is the design item of solar cell, herein using 1 Ω cm or so.
N-type hydrogenated amorphous silicon layer 140 (S101) is formed in the surface of the 1st n-type silicon crystalline substrate 10, and in the n-type
The transparency conducting layer 150 (S102) being made up of ITO is formed on hydrogenated amorphous silicon layer 140.
On the other hand, in the 2nd n-type silicon crystalline substrate 20 the back side, in striated (or comb shape) formed n+Region (phosphorus
Concentration 1019~1020cm-3Left and right) and p+Region (boron concentration 1019~1020cm-3The p of left and right+Layer), and these are set to as the back of the body
2nd n-layer 240 of face electric field layer (BSF) and the p-type area 220 (S201) as emitter layer.These n+Region and p+Area
Domain is to be formed by ionic-implantation, thermal diffusion method or laser doping method etc..
Then, (the phosphorus of n-layer 230 as surface field layer (FSF) is formed in the surface of the 2nd n-type silicon crystalline substrate 20
Concentration 1019cm-3The n of left and right+Layer) (S202).The FSF layers are to be formed by thermal diffusion method and ionic-implantation.
Then, insulating properties transparent passivating layer 160 is formed above the n-layer 230 as surface field layer (FSF)
(S203).The diaphragm is that the hydrogenation that heat oxide film, CVD deposited oxide film, plasma CVD or HF CVD are formed is noncrystalline
SiO films etc..
Then, to the 1st n-type silicon crystalline substrate 10 surface (that is, the transparency conducting layer 150 being made up of ITO) and the 2nd
At least one of the surface (that is, insulating properties transparent passivating layer 160) of n-type silicon crystalline substrate 20 implements surface activation process
(S301).The surface activation process is, for example, plasma treatment or ozone processing.
After the surface activation process, using the coating technique between known semiconductor substrate, crystallize the 1st n-type silicon
The surface (that is, the transparency conducting layer 150 being made up of ITO) of substrate and the surface of the 2nd n-type silicon crystalline substrate (that is, are aoxidized by silicon
The insulating properties transparent passivating layer 160 of the composition such as thing or aluminum oxide) it is bonded (S302) each other.Furthermore this fit into 400 DEG C with
Under temperature under carry out.This is the film quality drop in order to be imported the defects of suppressing film quality reduction and the toward upper crystallizing silicon layer of battery
It is low to cause because departing from from the hydrogen of upper cell hydrogenated amorphous silicon layer, accordingly, do not make characteristic of solar cell production during concatenation
Raw deterioration.
Furthermore, also can be in the electrically conducting transparent being made up of ITO of upper cell side in order to improve the purpose of the intensity of the fitting
Layer 150 is previously deposited the noncrystalline SiO films of hydrogenation again above.
After the fitting, the crystalline portion of the rear side of the 1st n-type silicon crystalline substrate is removed, is thinned to 30 μm of thickness
(generally less than 10 μm) below, form the n-type crystallizing silicon layer 130 (S303) of upper cell.
The thinning step also " can intelligently be cut in addition to the rear side of the n-type silicon crystalline substrate of mechanical lapping the 1st by so-called
Cut method " etc. gimmick carry out.
In the case of smart-cut method, before step S101, planted in the surface region of the 1st n-type silicon crystalline substrate
Enter the hydrogen of set dosage and be pre-formed hydrogen ion implant layer, in step S303, by applying machinery to the hydrogen ion implant layer
Or thermal shock so that n-type silicon crystalline substrate of the n-type crystallizing silicon layer from the 1st peel off and as the n-type crystallizing silicon layer of upper cell.
After this kind of thinning step, the etching for being ground damaging layer as needed removes, by the thickness of crystallizing silicon layer
Adjust to desired value.
Thereafter, formed in light entrance face side deposited in sequential hydrogenation i types amorphous silicon layer, hydrogenation p-type amorphous silicon layer 120, by ITO
Transparency conducting layer 110 (S304~S306).
Then, as shown in figure 4, the part for making the 2nd transparency conducting layer 150 by photolithographic techniques is exposed (S307), formed
Smooth surface electrode 170,180 (S308).Thus, the 1st smooth surface electrode 170 is electrically connected to transparency conducting layer 110, the 2nd smooth surface
Electrode 180 is electrically connected to the 2nd transparency conducting layer 150, and then completes upper cell.
Finally, contact hole is formed in the rear side of the 2nd n-type silicon crystalline substrate, forms backplate as shown in Figure 4
260th, 270 (S309), complete upper cell and complete solar cell.
As already explained above, the thickness of the crystallizing silicon layer of upper cell is subtracted by the solar cell as the present invention
It is thin, open-circuit voltage can be improved.On the other hand, if the thickness of the crystallizing silicon layer of upper cell is thinning, the light absorbs of upper cell
Length (optical path length) shortens, as a result, short-circuit current density diminishes, under power output is compared with the battery of silicon metal thickness
Drop.However, because the solar cell of the present invention constructs for concatenation type, therefore can be by bottom in the nonabsorbable light of upper cell
Battery absorbs, so as to provide generating.As a result, compared with situation about being generated electricity with bottom battery cell, can improve quite
Conversion efficiency in the part for the generation current that upper cell can be exported with high voltage.
In this way, the solar cell of the present invention is to be formed using more previous substantially by the 2nd conductivity type knot of upper cell
The thinned construction of crystal silicon layer.As a result, compared with the 2nd conductivity type crystallizing silicon layer is set into 100 μm of composition, due to upper cell
Open-circuit voltage increase more than 0.1V, can be with high voltage output current, therefore photoelectric transformation efficiency can be improved.
Further, since output can separately be taken out from upper cell and lower battery, therefore series connection need not be obtained
The matching of generation current required for connecting-type concatenation type battery.
Also, due to the present invention solar cell manufacture method be apply so-called " fitting " technology, and in 400 DEG C with
It is lower to carry out " fitting " of upper cell and lower battery, therefore hydrogen will not occur and depart from from hydrogenated amorphous silicon layer and reduce film quality
Situation, also will not to crystallizing silicon layer produce it is new the defects of, therefore, will not produce with concatenationization heterogeneous engaging battery it is bad
Change.
So far, the solar cell of the present invention is illustrated for the situation of series solar energy battery.However, this hair
Bright solar cell is not necessarily intended to as concatenation type, or does not possess lower battery, in being provided with the upper cell on matrix
Solar cell.That is, above-mentioned " lower battery " is not necessarily intended to play a role as solar cell.
In the situation for not by " lower battery " as solar cell being so-called matrix, solar cell of the invention
It is characterised by：Upper cell located at matrix interarea on, the upper cell be with from light incident side sequentially with transparent
Conductive layer, the 1st conductivity type amorphous silicon material layer, the 2nd conductivity type crystallizing silicon layer opposite with the 1st conductivity type, the 2nd conductivity type are non-
The lamination construction of crystal silicon layer, and the surface of the upper cell is provided with smooth surface electrode, the matrix is provided with backplate,
The thickness of 2nd conductivity type crystallizing silicon layer of the upper cell is less than 30 μm.
As matrix in this case, such as monocrystalline silicon can be used.In addition, situation about being made up of in matrix monocrystalline silicon,
It can be the form between upper cell and matrix with the layer being made up of tin indium oxide (ITO).
Also, the matrix is alternatively in surface region formed with donor concentrations 2nd conductive layer high compared with blocks, and in
The form of the conduction type silicon crystalline substrate of secondary the 2nd of insulating properties transparent passivating layer is provided with 2nd conductive layer.
In this case, when the manufacture of solar cell, also (after fitting, the 1st n-type can be removed in step S303
The crystalline portion of the rear side of silicon crystalline substrate, it is thinned to below 30 μm of thickness, forms the n-type crystallizing silicon layer 130 of upper cell
The step of) after, possess and the 1st conductivity type non-crystalline silicon opposite with the 2nd conductivity type is formed in the top of the 2nd conductivity type crystallizing silicon layer
The step of material layer.
In addition, the form of nano wire and nm wall can be also arranged with using the construction of upper cell as array.By being set to this
Kind nanometer construction, can improve quantum effect, improve the photoelectric transformation efficiency of solar cell.
Possesses the solar cell of the upper cell of this kind construction, for the solar cell with following construction, i.e. tool
There are transparency conducting layer, the 1st conductivity type amorphous silicon material layer, the 2nd conductivity type crystallizing silicon layer, the 2nd that the upper cell possesses conductive
The lamination construction of type amorphous silicon layer, when observing the solar cell from top, has with a plurality of of predetermined distance two-dimensional arrangements
Nano wire or wall are aligned in set direction and are divided into the battle array of the nm wall of multiple wall-like of predetermined distance two-dimensional arrangements
Row construction, the thickness of the diameter of the nano wire or the nm wall, be in be 10nm on the position of the 2nd conductivity type crystallizing silicon layer with
Under.
In using in the case of the form, with the nano wire or the nm wall to adjoin each other, be by insulating properties material every
From to be preferable.
In addition, when the upper cell constructed as nanometer, formed and the 2nd in the top of the 2nd conductivity type crystallizing silicon layer
In the step of conductivity type opposite the 1st conductivity type amorphous silicon material layer, preferably possess in the 1st conductivity type amorphous silicon material layer
Before formation, the 2nd conductivity type crystallizing silicon layer is divided into the secondary step of nano wire or nm wall, wherein the nano wire is with set
Every a plurality of nano wire for carrying out two-dimensional arrangements, and in a diameter of below 10nm on the position of the 2nd conductivity type crystallizing silicon layer, this is received
Rice wall is that wall is aligned in set direction and the nm wall of multiple wall-like of two-dimensional arrangements is carried out with predetermined distance and is led in the 2nd
Thickness is below 10nm on the position of electric type crystallizing silicon layer.
Fig. 8 is for illustrating that upper cell is to be divided into the nanometer for multiple wall-like that two-dimensional arrangements are carried out with predetermined distance
The schematic perspective view of the composition of the series solar energy battery of the situation of the array structure of wall.
The band gap of known silicon is 1.1eV or so in blocks, but in the case of as nano level wall and line, if its
Size is small compared with 10nm, can become big.Also, by the size of change nm wall and nano wire (width), it can be entered by quantum blocking effect
Row band gap controls.That is, by upper cell is set to make the nm wall of this kind of size or nano wire carry out the construction of two-dimensional arrangements, product
Polar region utilizes quantum blocking effect, can improve the performance as solar cell.
It is assumed that nm wall, if the thickness of wall is contracted into 2nm in theory, the band gap of actual effect is about 1.6eV, more block
The band gap (about 1.1eV) of the silicon of body expands 45% or so band gap, so as to expect high efficiency.
Fig. 9 is the battle array of nm wall of the observation with the silicon for being divided into multiple wall-like that two-dimensional arrangements are carried out with predetermined distance
Arrange the transmission electron microscope image of a part for the upper cell of construction.The size of nm wall is below 10nm, in the figure
It is about 2nm in shown example.In addition, insulating properties material (SiO is embedded to each other in nm wall2Or Al2O3)。
Figure 10 is the reflectivity for the array structure (A) that display is divided into nm wall and is embedded to each other absolutely in nm wall
Edge material is SiO2Array structure (B) reflectivity wavelength dependency figure.
It can be seen that because nm wall is embedded to insulating properties material each other, reflectivity is suppressed relatively low, can be improved too
The utilization ratio of sunlight.
This kind of nm wall can for example be made by following processes.First, by the pattern using immersion liquid lithographic printing
Reason forms the wall of tens of nm width.Thus, such as 1 μm or so width 75nm or so, height of wall can be formed.Furthermore if it is provided as
Interarea for the silicon of base material is (1,1,0) face, such as (1, -1,1) face is moved directly to (1,1,0) face, thus can be by wall
The wall in (1, -1,1) face is vertically formed in interarea.Then, by repeatedly carrying out oxidation processes and etching process, forming width is
Number nm nm wall.
Furthermore certainly needless to say, even if substituting above-mentioned wall and being set to be divided into a plurality of of predetermined distance two-dimensional arrangements
The array structure of nano wire, and the diameter of nano wire is set to below 10nm size, it can also obtain same quantum effects.
Industrial applicability
According to the present invention, there is provided a kind of silicon solar cell and its manufacture method, wherein, by the crystallizing silicon layer of upper cell
It is thinned, suppresses the auger recombination in crystallizing silicon layer, and will not also makes thin crystallization silicon layer damaged in manufacturing step, and opto-electronic conversion
Efficiency high.
Symbol description
10 the 1st n-type silicon crystalline substrate
20 the 2nd n-type silicon crystalline substrate
100 upper cells
110 transparency conducting layers
120 p-type amorphous silicon layers
130 n-type crystallizing silicon layers
140 n-type amorphous silicon layers
150 the 2nd transparency conducting layers
160 insulating properties transparent passivating layers
200 lower batteries
210 n-type regions
220 p-type area as emitter layer
The high n-layer of 230 donor concentrations
The 2nd high n-layer of 240 donor concentrations
250 insulating films
260 the 1st backplates
270 the 2nd backplates
280 conductive materials
300 solar cells.
Claims (13)
- A kind of 1. solar cell, it is characterised in that：Upper cell is located on the interarea of single crystal silicon substrate,The upper cell constructs including lamination, and lamination construction sequentially has from light incident side：1st transparency conducting layer；Have The amorphous silicon material layer of 1st conductivity type；Thickness is 3 μm~30 μm of monocrystalline silicon layer, and it has opposite with the 1st conductivity type the 2 conductivity types；With the 2nd conductivity type amorphous silicon layer；And the 2nd transparency conducting layer,The single crystal silicon substrate is the lower battery of back contacts type crystalline silicon cell structure, and the upper cell side of the lower battery has Insulating properties transparent passivating layer,2nd transparency conducting layer of the upper cell engages with the insulating properties transparent passivating layer of the lower battery, to be gone here and there Connect,The upper cell possesses i type amorphous silicon materials between amorphous silicon material layer and the monocrystalline silicon layer with the 1st conductivity type Layer, meanwhile,Possess i type amorphous silicon layers between monocrystalline silicon layer with the 2nd conductivity type and the amorphous silicon layer with the 2nd conductivity type.
- 2. solar cell as claimed in claim 1, wherein, the insulating properties transparent passivating layer is by Si oxide or alumina The layer that thing is formed.
- 3. solar cell as claimed in claim 1, wherein, the 2nd transparency conducting layer that the upper cell has is by indium oxide Tin (ITO) is formed.
- 4. solar cell as claimed in claim 1, wherein, when observing the upper cell from top, the 2nd transparency conducting layer Surface in comb teeth-shaped and expose, have bus portion and from the bus portion extension multiple finger sections.
- 5. solar cell as claimed in claim 1, wherein, it is provided with the surface of the upper cell：It is electrically connected to the 1st The smooth surface electrode of 1st comb teeth-shaped of transparency conducting layer and be electrically connected to the 2nd transparency conducting layer the 2nd comb teeth-shaped light Face electrode.
- 6. the solar cell as any one of claim 1 to 5, wherein, in the lower battery rear side formed with 1st conductive area and the 2nd conductive area, the 1st conductive area are formed as comb teeth-shaped, have bus portion and from the bus Multiple finger sections of portion's extension, the 2nd conductive area are formed as comb teeth-shaped, have bus portion and extend from the bus portion more Individual finger section, and donor concentrations are high compared with the blocks portion of the single crystal silicon substrate, the finger section and the 2nd of the 1st conductive area The finger section of conductive area is interacted with predetermined distance and configured,The back side of the lower battery is provided with the backplate and electricity of the 1st comb teeth-shaped for being electrically connected to the 1st conductive area It is connected to the backplate of the 2nd comb teeth-shaped of the 2nd conductive area.
- 7. solar cell as claimed in claim 6, wherein, when observing the solar cell from top, the 1st comb teeth-shaped The bus portion of smooth surface electrode be located at parallel position in a side with the bus portion of the backplate of the 2nd comb teeth-shaped, should The bus portion of the smooth surface electrode of 2nd comb teeth-shaped and the bus portion of the backplate of the 1st comb teeth-shaped are located in another side to be put down Capable position.
- 8. the solar cell as any one of claim 1 to 5, wherein, the monocrystalline silicon layer of the upper cell is set Following thickness are calculated as, the thickness makes the upper cell identical with the generation current of the lower battery.
- 9. the solar cell as any one of claim 1 to 5, wherein, should when observing the solar cell from top The lamination that upper cell possesses is configured to array structure, and the lamination is constructed with the 1st transparency conducting layer, with the 1st conductivity type Amorphous silicon material layer, the monocrystalline silicon layer with the 2nd conductivity type, the amorphous silicon layer with the 2nd conductivity type, the array structure have quilt It is divided into and set direction is aligned in a plurality of nano wire or wall of predetermined distance two-dimensional arrangements and arranged with predetermined distance two dimension The nm wall of multiple wall-like of row, the thickness of the diameter of the nano wire or the nm wall, in being on the position of the monocrystalline silicon layer Below 10nm,The nano wire or the nm wall to adjoin each other is isolated by insulating properties material.
- 10. a kind of manufacture method of solar cell, it is in the system for the solar cell for possessing upper cell on single crystal silicon substrate Method is made, the manufacture method includes：1st step, monocrystalline silicon substrate and the 2nd monocrystalline silicon substrate to the 1st are handled extremely with plasma treatment or ozone each other Few one performs surface activation process, and is bonded with less than 400 DEG C of temperature, and the 1st monocrystalline silicon substrate is in surface region shape Into there is an amorphous silicon layer, and in being provided with transparency conducting layer on the amorphous silicon layer, the 2nd monocrystalline silicon substrate forms back contacts type knot The lower battery of crystal silicon battery structure, the 2nd monocrystalline silicon substrate surface region formed with transparency conducting layer or insulating properties Transparent passivating layer；AndSecond step, the 1st silicon crystalline substrate is thinned to below 30 μm of thickness by it from the back side, the list as the upper cell Crystal silicon layer.
- 11. the manufacture method of solar cell as claimed in claim 10, wherein, the transparency conducting layer is tin indium oxide (ITO), the insulating properties transparent passivating layer is the layer being made up of Si oxide or aluminum oxide.
- 12. the manufacture method of solar cell as claimed in claim 10, wherein, possess the 3rd step after the second step Suddenly, in this third step, the tool opposite with the 1st monocrystalline silicon substrate is formed in the top of the monocrystalline silicon layer of the upper cell There is the amorphous silicon material layer of conductivity type.
- 13. the manufacture method of solar cell as claimed in claim 12, wherein, the third step possesses in the non-crystalline silicon material Before the formation of the bed of material, the monocrystalline silicon layer is divided into the secondary step of nano wire or nm wall, the wherein nano wire is with set Every a plurality of nano wire of two-dimensional arrangements, and in a diameter of below 10nm on the position of the monocrystalline silicon layer, the nm wall is wall pair Set directions of Qi Yu and with the nm wall of multiple wall-like of predetermined distance two-dimensional arrangements, and in thickness on the position of the monocrystalline silicon layer For below 10nm.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2014-073369 | 2014-03-31 | ||
| JP2014073369 | 2014-03-31 | ||
| PCT/JP2015/001413 WO2015151422A1 (en) | 2014-03-31 | 2015-03-13 | Solar battery and solar battery production method |
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| CN106165120A CN106165120A (en) | 2016-11-23 |
| CN106165120B true CN106165120B (en) | 2018-01-30 |
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| CN201580017041.4A Expired - Fee Related CN106165120B (en) | 2014-03-31 | 2015-03-13 | The manufacture method of solar cell and solar cell |
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| Country | Link |
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| JP (1) | JP6188921B2 (en) |
| CN (1) | CN106165120B (en) |
| TW (1) | TWI597857B (en) |
| WO (1) | WO2015151422A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3016148A1 (en) * | 2014-10-28 | 2016-05-04 | Sol Voltaics AB | Dual layer photovoltaic device |
| FR3044827B1 (en) * | 2015-12-04 | 2018-03-16 | Centre National De La Recherche Scientifique - Cnrs - | PHOTOVOLTAIC CELL |
| KR20190079622A (en) * | 2016-11-07 | 2019-07-05 | 신에쓰 가가꾸 고교 가부시끼가이샤 | Method for manufacturing high photoelectric conversion efficiency solar cell and high photoelectric conversion efficiency solar cell |
| KR20200075640A (en) * | 2018-12-18 | 2020-06-26 | 엘지전자 주식회사 | Tandem solar cell |
| CN115498071B (en) * | 2022-09-20 | 2024-05-14 | 通威太阳能（成都）有限公司 | Battery preparation method, battery and electronic product |
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- 2015-03-13 JP JP2016511357A patent/JP6188921B2/en not_active Expired - Fee Related
- 2015-03-13 WO PCT/JP2015/001413 patent/WO2015151422A1/en active Application Filing
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Also Published As
| Publication number | Publication date |
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| JP6188921B2 (en) | 2017-08-30 |
| WO2015151422A1 (en) | 2015-10-08 |
| TWI597857B (en) | 2017-09-01 |
| TW201539774A (en) | 2015-10-16 |
| CN106165120A (en) | 2016-11-23 |
| JPWO2015151422A1 (en) | 2017-04-13 |
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