CN210723045U - High-efficient crystal silicon photovoltaic cell structure - Google Patents
High-efficient crystal silicon photovoltaic cell structure Download PDFInfo
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- CN210723045U CN210723045U CN201921510439.3U CN201921510439U CN210723045U CN 210723045 U CN210723045 U CN 210723045U CN 201921510439 U CN201921510439 U CN 201921510439U CN 210723045 U CN210723045 U CN 210723045U
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Abstract
The utility model discloses a high-efficiency crystalline silicon photovoltaic cell structure, which comprises a silicon substrate, wherein the front side of the silicon substrate is provided with a passivation film, and the back side of the silicon substrate sequentially comprises a tunneling dielectric film or an intrinsic silicon film, a graphical semiconductor film, a passivation film and a graphical electrode from top to bottom; the semiconductor thin film comprises a P-type semiconductor thin film and an N-type semiconductor thin film, and the electrode comprises a positive electrode and a negative electrode; the positive electrode penetrates through the passivation film and the P-type semiconductor film to form ohmic contact, and the negative electrode penetrates through the passivation film and the N-type semiconductor film to form ohmic contact. The utility model discloses can greatly reduce the shading loss, improve the current output ability of battery.
Description
Technical Field
The utility model relates to a photovoltaic cell technical field, concretely relates to high-efficient crystal silicon photovoltaic cell structure.
Background
The front (light receiving) surface of the crystalline silicon solar cell is often provided with electrodes which shield part of sunlight to reduce the photoelectric conversion efficiency of the cell. The full back electrode cell structure avoids the above problems, but such cells require patterned doping on the back side of the cell. At present, the preparation scheme of the battery is a mask doping scheme, the process is complex, and the cost is high.
SUMMERY OF THE UTILITY MODEL
Utility model purpose: the utility model aims to provide a high-efficient crystal silicon photovoltaic cell structure and preparation method thereof to prior art's not enough, can greatly reduce the shading loss, improve the current output ability (Isc) of battery.
The technical scheme is as follows: the utility model relates to a high-efficiency crystalline silicon photovoltaic cell structure, which comprises a silicon substrate, wherein the front side of the silicon substrate is provided with a passivation film, and the back side of the silicon substrate sequentially comprises a tunneling dielectric film or an intrinsic silicon film, a graphical semiconductor film, a passivation film and a graphical electrode from top to bottom; the semiconductor thin film comprises a P-type semiconductor thin film and an N-type semiconductor thin film, and the electrode comprises a positive electrode and a negative electrode; the positive electrode penetrates through the passivation film and the P-type semiconductor film to form ohmic contact, and the negative electrode penetrates through the passivation film and the N-type semiconductor film to form ohmic contact.
Preferably, the tunneling dielectric film is selected from SiO2、Al2O3And SiC.
Preferably, the thickness of the tunneling dielectric film is 1-5 nm.
Preferably, the thickness of the tunneling dielectric film is 1-2 nm.
Preferably, the P-type semiconductor film is selected from P-Si, P-NiO and P-Cu2And O is one of the compounds.
Preferably, the thickness of the P-type semiconductor thin film is 5-200 nm.
Preferably, the thickness of the P-type semiconductor thin film is 20-100 nm.
Preferably, the resistivity of the P-type semiconductor thin film is between 1E-1 and 1E-4 Ω CM.
Preferably, the N-type semiconductor film is selected from N-Si, N-ZnO and N-TiO2One kind of (1).
Preferably, the thickness of the N-type semiconductor thin film is 5-200 nm.
Preferably, the thickness of the N-type semiconductor thin film is 20-100 nm.
Preferably, the resistivity of the N-type semiconductor thin film is between 1E-1 and 1E-4 Ω CM.
Preferably, the N-type semiconductor film and the P-type semiconductor film do not intersect.
Preferably, the thickness of the intrinsic silicon thin film is 2-20 nm.
Preferably, the thickness of the intrinsic silicon thin film is 5-10 nm.
Preferably, the intrinsic silicon thin film is provided to be patterned, and the patterned intrinsic silicon thin film corresponds to a patterned P-type semiconductor thin film and/or an N-type semiconductor thin film.
Preferably, the passivation film is SiNx or SixOyNz, and the thickness of the passivation film is 60 to 200 nm.
Preferably, the thickness of the passivation film is 70 to 120 nm.
Preferably, the pattern is a line pattern, and the width of the line pattern is 20-500 μm.
Preferably, the width of the line pattern is 50 to 100 μm.
The utility model also provides a preparation method of high-efficient crystal silicon photovoltaic cell structure, the method is as follows: preparing a tunneling dielectric film or an intrinsic silicon film on the reverse surface of the silicon substrate, preparing a patterned semiconductor film on the surface of the tunneling dielectric film or the intrinsic silicon film by adopting a G-CVD technology, annealing, preparing a passivation film, covering the tunneling dielectric film or the intrinsic silicon film and the semiconductor film, and preparing a patterned electrode.
Preferably, the G-CVD includes a programmable jet head that can control pattern growth.
Preferably, the injector head controls a gas phase chemical, which is a source of CVD.
Preferably, the injector head controls a gas phase chemical, which is a catalyst for CVD.
Preferably, the injector head controls an energy source for CVD, the energy source being a plasma power source.
Preferably, the energy source is an alternating electromagnetic field.
Preferably, the injector head controls an energy source for CVD, which is a high energy plasma.
Preferably, the energy source is an Ar plasma.
Preferably, the injector head controls an energy source for CVD, the energy source being a high energy gas.
Preferably, the energy source is N2Or Ar.
Preferably, the ejection head controls an energy source for CVD, which is a high energy light source.
Preferably, the energy source is a laser.
Preferably, the annealing temperature is 600-.
Preferably, the annealing temperature is 750-.
Compared with the prior art, the beneficial effects of the utility model are that:
the utility model discloses the battery openly does not have the electrode, can greatly reduce shading loss, improves the current output ability (Isc) of battery, improves the photoelectric conversion efficiency of battery, in addition, the utility model discloses stopped the direct contact of metal electrode and silicon substrate, can reduce the complex of metal electrode, increased the open circuit voltage (Voc) of battery, further improved the photoelectric conversion efficiency of the utility model; in addition, a semiconductor thin film having low resistivity is preferable, and the photoelectric conversion efficiency of the present invention can be further improved. The utility model discloses a preparation is carried out to graphical chemical vapor deposition (G-CVD) technique, and the production technology route is short, can reduce manufacturing cost.
Drawings
Fig. 1 is a structural diagram of embodiment 1 of the present invention.
Fig. 2 is a structural diagram of embodiment 2 of the present invention.
Fig. 3 is a structural diagram of embodiment 3 of the present invention.
In the attached figure, a 1-silicon substrate, a 2-passivation film, a 3-tunneling dielectric film, a 4-P type semiconductor film, a 5-N type semiconductor film, a 6-positive electrode, a 7-negative electrode and an 8-intrinsic silicon film.
Detailed Description
The technical solution of the present invention is described in detail below with reference to the specific embodiments and the attached drawings, but the scope of the present invention is not limited to the embodiments.
Example 1
A high-efficiency crystalline silicon photovoltaic cell structure is disclosed, referring to fig. 1, and comprises a silicon substrate 1, wherein a passivation film 2 is arranged on the front surface of the silicon substrate 1, and the back surface of the silicon substrate 1 sequentially comprises a tunneling dielectric film 3, a patterned semiconductor film, a passivation film 2 and a patterned electrode from top to bottom; the semiconductor thin films comprise a P-type semiconductor thin film 4 and an N-type semiconductor thin film 5, and the electrodes comprise a positive electrode 6 and a negative electrode 7; the positive electrode 6 forms an ohmic contact through the passivation film 2 and the P-type semiconductor thin film 4, and the negative electrode 7 forms an ohmic contact through the passivation film 2 and the N-type semiconductor thin film 5.
Wherein the tunneling dielectric film 3 is SiO2The thickness of the tunneling dielectric film 3 is 2 nm.
Wherein the P-type semiconductor thin film 4 is P-Si, the thickness of the P-type semiconductor thin film 4 is 200nm, and the resistivity of the P-type semiconductor thin film 4 is 1E-1 Ω CM.
Wherein the N-type semiconductor film 5 is N-Si, the thickness of the N-type semiconductor film 5 is 100nm, and the resistivity of the N-type semiconductor film 5 is 1E-1 omega CM.
Wherein the N-type semiconductor thin film 5 and the P-type semiconductor thin film 4 do not intersect.
Wherein, the passive film 2 is SiNx, and the thickness of the passive film 2 is 70 nm.
Wherein the pattern is in the shape of a line, and the width of the line pattern is 50 μm.
The preparation method of the high-efficiency crystalline silicon photovoltaic cell structure comprises the following steps: preparing a tunneling dielectric film 3 on the reverse surface of the silicon substrate, preparing a patterned semiconductor film on the surface of the tunneling dielectric film 3 by adopting a G-CVD technology, annealing at 600 ℃, preparing a passivation film 2, covering the tunneling dielectric film 3 and the semiconductor film, and preparing a patterned electrode.
Wherein the G-CVD includes a programmable injector head that controls the growth of the pattern, the injector head controlling a vapor phase chemical that is a source of the CVD.
The front surface of the battery is not provided with an electrode, so that shading loss can be greatly reduced, the current output capacity of the battery is improved, and the photoelectric conversion efficiency of the battery is improved; further, by selecting a semiconductor thin film having low resistivity, the photoelectric conversion efficiency of this embodiment can be further improved.
Example 2
A high-efficiency crystalline silicon photovoltaic cell structure is disclosed, referring to fig. 2, and comprises a silicon substrate 1, wherein a passivation film 2 is arranged on the front surface of the silicon substrate 1, and the back surface of the silicon substrate 1 sequentially comprises an intrinsic silicon film 8, a patterned semiconductor film, a passivation film 2 and a patterned electrode from top to bottom; the semiconductor thin films comprise a P-type semiconductor thin film 4 and an N-type semiconductor thin film 5, and the electrodes comprise a positive electrode 6 and a negative electrode 7; the positive electrode 6 forms an ohmic contact through the passivation film 2 and the P-type semiconductor thin film 4, and the negative electrode 7 forms an ohmic contact through the passivation film 2 and the N-type semiconductor thin film 5.
Wherein the P-type semiconductor film 4 is P-NiO, the thickness of the P-type semiconductor film 4 is 100nm, and the resistivity of the P-type semiconductor film 4 is between 1E and 4 Ω CM.
Wherein the N-type semiconductor film 5 is N-ZnO, the thickness of the N-type semiconductor film 5 is 20nm, and the resistivity of the N-type semiconductor film 5 is 1E-4 omega CM.
Wherein the N-type semiconductor thin film 5 and the P-type semiconductor thin film 4 do not intersect.
Wherein the thickness of the intrinsic silicon thin film is 5 nm.
Wherein the passivation film 2 is SixOyNz, and the thickness of the passivation film 2 is 120 nm.
The pattern is in the shape of a line, and the width of the line-shaped pattern is 100 micrometers.
The preparation method of the high-efficiency crystalline silicon photovoltaic cell structure comprises the following steps: preparing an intrinsic silicon film 8 on the reverse surface of the silicon substrate, preparing a patterned semiconductor film on the surface of the intrinsic silicon film 8 by adopting a G-CVD technology, annealing at 750 ℃, preparing a passivation film, covering the intrinsic silicon film 8 and the semiconductor film, and preparing a patterned electrode.
Wherein the spray head controls an energy source for CVD, and the energy source is an alternating electromagnetic field.
The front surface of the battery is not provided with an electrode, so that shading loss can be greatly reduced, the current output capacity of the battery is improved, and the photoelectric conversion efficiency of the battery is improved; further, by selecting a semiconductor thin film having low resistivity, the photoelectric conversion efficiency of this embodiment can be further improved.
Example 3
A high-efficiency crystalline silicon photovoltaic cell structure is disclosed, referring to fig. 3, and comprises a silicon substrate 1, wherein a passivation film 2 is arranged on the front surface of the silicon substrate 1, and the back surface of the silicon substrate 1 sequentially comprises an intrinsic silicon film 8, a patterned semiconductor film, a passivation film 2 and a patterned electrode from top to bottom; the semiconductor thin films comprise a P-type semiconductor thin film 4 and an N-type semiconductor thin film 5, and the electrodes comprise a positive electrode 6 and a negative electrode 7; the positive electrode 6 forms an ohmic contact through the passivation film 2 and the P-type semiconductor thin film 4, and the negative electrode 7 forms an ohmic contact through the passivation film 2 and the N-type semiconductor thin film 5.
Wherein the P-type semiconductor film 4 is P-Cu2O, the thickness of the P-type semiconductor thin film 4 is 20nm, and the resistivity of the P-type semiconductor thin film 4 is 1E-2 Ω CM.
Wherein the N-type semiconductor film 5 is N-TiO2The thickness of the N-type semiconductor thin film 5 is 5nm, and the resistivity of the N-type semiconductor thin film 5 is 1E-2 Ω CM.
Wherein the N-type semiconductor thin film 5 and the P-type semiconductor thin film 4 do not intersect.
The thickness of the intrinsic silicon thin film is 10nm, the intrinsic silicon thin film is set to be graphical, and the graphical intrinsic silicon thin film corresponds to the graphical P-type semiconductor thin film and the graphical N-type semiconductor thin film relatively.
Wherein, the passive film 2 is SiNx, and the thickness of the passive film 2 is 200 nm.
Wherein the pattern is in the shape of a line, and the width of the line pattern is 500 μm.
The preparation method of the high-efficiency crystalline silicon photovoltaic cell structure comprises the following steps: preparing an intrinsic silicon film 8 on the reverse surface of the silicon substrate, preparing a patterned semiconductor film on the surface of the intrinsic silicon film 8 by adopting a G-CVD technology, annealing at 850 ℃, preparing a passivation film 2, covering the intrinsic silicon film 8 and the semiconductor film, and preparing a patterned electrode.
Wherein the injector head controls an energy source for CVD, and the energy source is Ar plasma.
The front surface of the battery is not provided with an electrode, so that shading loss can be greatly reduced, the current output capacity of the battery is improved, and the photoelectric conversion efficiency of the battery is improved; further, by selecting a semiconductor thin film having low resistivity, the photoelectric conversion efficiency of this embodiment can be further improved.
As mentioned above, although the present invention has been shown and described with reference to certain preferred embodiments, it should not be construed as limiting the invention itself. Various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (20)
1. A high-efficiency crystalline silicon photovoltaic cell structure is characterized by comprising a silicon substrate, wherein a passivation film is arranged on the front surface of the silicon substrate, and the back surface of the silicon substrate sequentially comprises a tunneling dielectric film or an intrinsic silicon film, a patterned semiconductor film, a passivation film and a patterned electrode from top to bottom; the semiconductor thin film comprises a P-type semiconductor thin film and an N-type semiconductor thin film, and the electrode comprises a positive electrode and a negative electrode; the positive electrode penetrates through the passivation film and the P-type semiconductor film to form ohmic contact, and the negative electrode penetrates through the passivation film and the N-type semiconductor film to form ohmic contact.
2. The structure of claim 1 wherein said tunneling dielectric film is selected from the group consisting of SiO2、Al2O3And SiC.
3. The structure of claim 1, wherein the tunneling dielectric film has a thickness of 1-5 nm.
4. The structure of claim 1 wherein said P-type semiconductor film is selected from the group consisting of P-Si, P-NiO, P-Cu2And O is one of the compounds.
5. The structure of claim 1, wherein the P-type semiconductor thin film has a thickness of 5-200 nm.
6. The structure of claim 1, wherein the resistivity of the P-type semiconductor thin film is between 1E-1 and 1E-4 Ω CM.
7. The structure of claim 1, wherein the N-type semiconductor thin film is selected from the group consisting of N-Si, N-ZnO, N-TiO2One kind of (1).
8. The structure of claim 1, wherein the N-type semiconductor thin film has a thickness of 5-200 nm.
9. The structure of claim 1, wherein the N-type semiconductor thin film has a resistivity between 1E-1 and 1E-4 Ω CM.
10. The structure of claim 1, wherein the N-type semiconductor film and the P-type semiconductor film do not cross.
11. The structure of claim 1 wherein the intrinsic silicon thin film has a thickness of 2-20 nm.
12. The structure of claim 1, wherein the intrinsic silicon thin film is provided as a patterned, and the patterned intrinsic silicon thin film corresponds to a patterned P-type semiconductor thin film and/or an N-type semiconductor thin film.
13. The structure of claim 1, wherein the passivation film is SiNx or SixOyNz, and the passivation film has a thickness of 60 to 200 nm.
14. The structure of claim 1, wherein the pattern is a line pattern, and the width of the line pattern is 20-500 μm.
15. The structure of claim 3, wherein the tunneling dielectric film has a thickness of 1-2 nm.
16. The structure of claim 5, wherein the P-type semiconductor film has a thickness of 20-100 nm.
17. The structure of claim 8, wherein the thickness of the N-type semiconductor thin film is 20-100 nm.
18. The structure of claim 11 wherein the intrinsic silicon thin film has a thickness of 5-10 nm.
19. The structure of claim 13, wherein the passivation film has a thickness of 70-120 nm.
20. The structure of claim 14, wherein the width of the line pattern is 50-100 μm.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201921510439.3U CN210723045U (en) | 2019-09-11 | 2019-09-11 | High-efficient crystal silicon photovoltaic cell structure |
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| CN201921510439.3U CN210723045U (en) | 2019-09-11 | 2019-09-11 | High-efficient crystal silicon photovoltaic cell structure |
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