CN106160766A - A kind of DC offset correction method and apparatus of zero intermediate frequency reciver - Google Patents
A kind of DC offset correction method and apparatus of zero intermediate frequency reciver Download PDFInfo
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- CN106160766A CN106160766A CN201510176259.6A CN201510176259A CN106160766A CN 106160766 A CN106160766 A CN 106160766A CN 201510176259 A CN201510176259 A CN 201510176259A CN 106160766 A CN106160766 A CN 106160766A
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Abstract
The present invention relates to a kind of DC offset correction method of zero intermediate frequency reciver, comprising the following steps: during electricity initializes on the receiver, successive approximation algorithm digital signal processing module completes direct current offset detection and stores the I measured, Q component DC offset value to correction result memory element；When receiver enters reception every time, automatically take out DC offset value from correction result memory element, be converted to analog voltage signal through DAC and feed back to the input of analogue amplifier, thus complete DC offset correction.Device includes the analogue amplifier being linked in sequence, analog-digital converter, successive approximation algorithm digital signal processing module, switch K, digital to analog converter and the correction result memory element being connected with digital to analog converter；The present invention is by the main DC side-play amount of receiver, disposably detect in receiver chip power up initialization process and stored, when entering reception, it is automatically loaded the most stored DC offset value every time, before direct current enters amplifier and ADC, it is corrected for.
Description
Technical field
The invention belongs to the communications field, particularly relate to the DC offset correction in a kind of zero intermediate frequency radio-frequency transmitter
Method and apparatus.
Background technology
Zero intermediate frequency reciver technology is for traditional double conversion technology, and it is only with once becoming
Frequently.Aerial signal is through antenna, low-noise amplifier, and a frequency mixer, directly by under the radiofrequency signal in band
Frequency conversion is baseband analog I/Q signal, is then passed through ADC and is converted to digital I/Q signal, is demodulated decoding the most again
Etc. Base-Band Processing；It is little that zero intermediate frequency reciver has volume, low cost and be prone to single chip integrated feature, becomes
For a kind of structure of competitiveness great in radio-frequency transmitter, it is widely applied in the field of wireless communication.
But DC shift signal is the major defect of zero-if architecture receiver, the generation of DC shift signal and coming
Mainly there is the following aspects in source:
1. circuit or domain itself are due to design, and manufacturing process etc. causes that mixer output is asymmetric to be caused
Common mode direct current offset, it is inherently present in each individual reception movement sheet；
2. local oscillator self-mixing, owing to local oscillation signal is identical with the frequency of carrier signal of receiving terminal, can cause local oscillator
Signals leakiness is to the input of receiver, thus forms the most mixed of local oscillation signal, produces bigger direct current offset,
And this direct current offset is bigger with the change fluctuation range of rear class amplifier gain and local frequency；This direct current is inclined
Shifting is the main cause that zero intermediate frequency reciver exists direct current offset；
3. the DC shift caused due to environment, such as temperature, becomes from environment such as the environment noises of antenna end introducing
Change the DC shift that causes, in this respect direct current relative to 1, described in 2 direct current offset much smaller, because receiving
SAW filter after the temperature compensation circuit of machine chip internal existence and duplexer is by the impact of this Partial DC
It is minimized.
Foregoing describe zero intermediate frequency reciver and produce three reasons of direct current offset, all these direct current offset meetings
It is superimposed upon on useful signal by whole reception passage, and these direct current offsets often making an uproar than radio-frequency front-end
Sound is much greater, on the one hand makes signal to noise ratio be deteriorated, and after these big direct current offsets are also possible to make frequency mixer
Amplifier and ADC saturated, thus can not effectively amplify useful signal.
In prior art, in order to simplify direct current offset detection and calibration circuit, all use Digital Way, i.e.
In digital baseband or digital filter circuit, reception data are carried out sampling processing, thus obtain direct current biasing；
But through frequency mixer output direct current and useful signal be to be superimposed to be input to amplifier, then through ADC change
For digital signal, when direct current offset exists, and when direct current is bigger, will directly limit amplifier with
ADC can the bound of input signal amplitude, i.e. amplifier or ADC can be excessive and saturated because of input signal,
Producing non-linear distortion, thus limit the dynamic range of whole receiver, this will directly influence receiver
And sensitivity, thus deteriorate the performance of whole receiver；In order to tackle bigger direct current offset, it is necessary to
During design, increasing amplifier and the dynamic range of ADC, this will be greatly increased the design difficulty of amplifier and ADC
And dynamic power consumption；But, the most not yet propose to consider that the zero intermediate frequency direct current of amplifier and ADC dynamic range is inclined
Move calibration program.
Summary of the invention
For above-mentioned technical deficiency, the present invention proposes the method and apparatus of a kind of closed-loop direct correction, its purpose
Being to provide a kind of direct current offset calibration program, to solve amplifier in prior art, ADC dynamic range is damaged
The problem lost.
The technical solution adopted for the present invention to solve the technical problems is: the direct current of a kind of zero intermediate frequency reciver is inclined
Shift correction method, comprises the following steps:
During electricity initializes on the receiver, switch K Guan Bi, successive approximation algorithm digital signal processing module completes
Direct current offset detects, and is stored by the DC offset value of the I detected, Q component to correction result memory element
In；Then, switch K disconnects；
When receiver enters reception every time, automatically from correction result memory element, take out this DC offset value,
Be converted to analog voltage signal through digital to analog converter and feed back to the input of analogue amplifier, thus complete direct current
Offset correction.
Described successive approximation algorithm digital signal processing module completes direct current offset detection, and I, Q of detecting is divided
Amount DC offset value store to correction result memory element comprise the following steps:
Digital I, Q component that analog-digital converter is exported by successive approximation algorithm digital signal processing module pass through gradually to force
Nearly algorithm obtains the DC offset value of I, Q component, and stores in correction result memory element.
The DC drift correction apparatus of a kind of zero intermediate frequency reciver, including the analogue amplifier being linked in sequence, mould
Number converter, successive approximation algorithm digital signal processing module, switch K, digital to analog converter and and digital to analog converter
The correction result memory element connected；Described digital to analog converter is connected with the input of analogue amplifier；
Numeral I, Q component are detected during initializing by described successive approximation algorithm digital signal processing module,
And the I of detection acquisition, Q component DC offset value are stored to correction result memory element；
Described correction result memory element, for when receiver enters reception every time, exports this direct current inclined automatically
Shifting value realizes DC offset correction for the input being fed back to analogue amplifier by analog-digital converter.
Described analogue amplifier, analog-digital converter, successive approximation algorithm digital signal processing module, switch K, digital-to-analogue
Transducer constitutes close loop negative feedback circuit.
The invention have the advantages that and advantage:
1. the DC drift correction apparatus with close loop negative feedback of the present invention, by the main DC of receiver
Side-play amount, has disposably detected in receiver chip power up initialization process and has stored, every time
When entering reception, it is automatically loaded the most stored DC offset value, right before direct current enters amplifier and ADC
It is corrected for.
2. the present invention before amplifier and ADC, just eliminate receiver chip main circuit Parameters variation and
The direct-flow offset weight produced and receiver chip is individual divides because of the direct current offset that production technology deviation is intrinsic
Amount, compensated in advance amplifier and the ADC self impact on direct current offset simultaneously, effectively prevent amplification
Device and ADC because bigger direct current offset and the non-linear distortion of saturated generation, reduce amplifier and ADC
Design difficulty.
3. the present invention completes the DC offset correction of receiver inside radio-frequency transmitter, it is not necessary to Base-Band Processing
Participate in, save the hardware of Base-Band Processing, software resource and process time；
Accompanying drawing explanation
Fig. 1 is the zero intermediate frequency digital interface radio frequency receiver structure schematic diagram of the present invention；
Wherein, LNA is low-noise amplifier, and ADC is analog-digital converter, and I is in-phase component, and Q is orthogonal
Component, LO is local oscillator, and DAC is D-A converter.
Detailed description of the invention
Below in conjunction with embodiment, the present invention is described in further detail.
The present invention uses a kind of DC offset correction method of close loop negative feedback, to directly before amplifier and ADC
Stream skew is corrected, it is to avoid make amplifier or ADC saturated and produce non-linear distortion because direct current is excessive
Problem.
This device is integrated on receiver chip, including the analogue amplifier 3 being linked in sequence, analog-digital converter
4, successive approximation algorithm digital signal processing module 5, switch K, digital to analog converter 6 and with digital to analog converter 6 even
The correction result memory element 7 connect；Described analogue amplifier 3 input is connected with frequency mixer 2 outfan, by
Secondary approximate algorithm digital signal processing module 5 outfan is connected with baseband processing unit input.
Described successive approximation algorithm digital signal processing module 5 input is connected with analog-digital converter 4, and outfan leads to
Cross switch K to be connected with digital to analog converter 6, correction result memory element 7；The output of described digital to analog converter 6
End is connected with the input of analogue amplifier 3, input is connected with correction result memory element 7.
Wherein, successive approximation algorithm word processing module 5 is digital circuit.Inside is loaded with successive approximation algorithm,
For calculating numeral I, the DC offset value of Q component and exporting to correction result memory element 7, simultaneously by direct current
Digital I, Q orthogonal signalling after offset correction export to baseband processing unit.
Correction result memory element 7 is digital circuit, uses the mode of depositor to realize, when being used for initializing
The DC offset value of storage successive approximation algorithm digital signal processing module 5 output, and after initialization terminates just
Export this DC offset value when often receiving, feed back to analogue amplifier 3 by digital to analog converter 6.
The present embodiment is as a example by five bits, and specific implementation process is as follows:
During receiver chip power-up initializing, switch K Guan Bi, analogue amplifier 3, analog-digital converter 4,
The close loop negative feedback electricity that successive approximation algorithm digital signal processing module 5, digital to analog converter 6 are formed together with switch K
Road complete direct current offset detection, and the DC offset value of the I detected, Q component is stored to correction result deposit
In storage unit 7；
After having detected, switch K disconnects this close loop negative feedback circuit and normally receives not affect.
When receiver enters reception every time, automatically from correction result memory element 7, take out corresponding direct current
Deviant, is converted to analog voltage signal through digital to analog converter 6 and feeds back to the input of analogue amplifier, from
And complete DC offset correction.
DC offset correction only does once when receiver chip power-up initializing；Detailed process and step are as follows:
The most as shown in Figure 1: when receiver chip powers on, radio-frequency antenna switch is set and is in emission state,
Due to the buffer action of switch, radio frequency reception end is in the state that input is zero；
2. switch K Guan Bi, analogue amplifier (module 3), ADC (module 4), successive approximation algorithm number
Word processing module (module 5), switch K and a five bit DAC (module 6) form close loop negative feedback loop；
3. in receiver chip initialization procedure, start DC offset correction, i.e. start above-mentioned closed loop negative anti-
It is fed back to road, uses successive approximation algorithm, utilize successive approximation algorithm digital signal processing module (module 5) to ADC
The output of the digital I of (module 4), Q component carries out adding up and average respectively, and the sign bit of its average result is certainly
The direction of fixed every bit Approach by inchmeal and result, until five bit Approaching Results all obtain, just complete direct current
Offset detection, and the five bit Approaching Results (final output valve) of the digital I obtained, Q component are made respectively
Store in correction result memory element (module 7) for numeral I, the DC offset value i.e. testing result of Q component；
4. disconnect switch K, appeal close loop negative feedback loop is disconnected；
When normally receiving, in correction result memory element (module 7), automatically take out DC offset value, this
DC offset value RXDC_I [4:0] (numeral I road direct-flow offset weight) and RXDC_Q [4:0] (numeral Q
Road direct-flow offset weight) be converted to analog voltage signal through five bit DAC (module 6), then directly input
To the input (place shown in A point arrow in Fig. 1) of analogue amplifier (module 3), frequency mixer 2 output
I, Q component respectively with feedback I, Q analog voltage signal make after the recovery, as correction after I, Q component defeated
Enter to analogue amplifier.So, before analogue amplifier and ADC, receiver chip is just eliminated the most electric
Road Parameters variation and the direct-flow offset weight that produces and receiver chip individual because of production technology deviation institute intrinsic
Direct-flow offset weight, compensated in advance amplifier and the ADC self impact on direct current offset simultaneously, effectively
Prevent amplifier and ADC because bigger direct current offset and the non-linear distortion of saturated generation.
Claims (4)
1. the DC offset correction method of a zero intermediate frequency reciver, it is characterised in that comprise the following steps:
During electricity initializes on the receiver, switch K Guan Bi, successive approximation algorithm digital signal processing module (5)
Complete direct current offset detection, and the DC offset value of the I detected, Q component is stored to correction result storage
In unit (7)；Then, switch K disconnects；
When receiver enters reception every time, from correction result memory element (7), automatically take out this direct current inclined
Shifting value, is converted to analog voltage signal through digital to analog converter (6) and feeds back to the input of analogue amplifier (3)
End, thus complete DC offset correction.
The DC offset correction method and apparatus of a kind of zero intermediate frequency reciver the most according to claim 1, it is special
Levy and be that described successive approximation algorithm digital signal processing module (5) completes direct current offset detection, and will detect
I, the DC offset value of Q component store to correction result memory element (7) comprise the following steps:
Digital I that analog-digital converter (4) is exported by successive approximation algorithm digital signal processing module (5), Q component
Obtained the DC offset value of I, Q component by successive approximation algorithm, and store correction result memory element (7)
In.
3. the DC drift correction apparatus of a zero intermediate frequency reciver, it is characterised in that include that the simulation being linked in sequence is put
Big device (3), analog-digital converter (4), successive approximation algorithm digital signal processing module (5), switch K, digital-to-analogue turn
Parallel operation (6) and correction result memory element (7) being connected with digital to analog converter (6)；Described digital-to-analogue turns
Parallel operation (6) is connected with the input of analogue amplifier (3)；
Numeral I, Q component are entered during initializing by described successive approximation algorithm digital signal processing module (5)
Row detection, and the I of detection acquisition, Q component DC offset value are stored to correction result memory element (7)
In；
Described correction result memory element (7), for when receiver enters reception every time, exports this straight automatically
Stream deviant realizes direct current for the input being fed back to analogue amplifier (3) by analog-digital converter (4)
Offset correction.
The DC drift correction apparatus of a kind of zero intermediate frequency reciver the most according to claim 1, it is characterised in that
Described analogue amplifier (3), analog-digital converter (4), successive approximation algorithm digital signal processing module (5), open
Close K, digital to analog converter (6) constitutes close loop negative feedback circuit.
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| CN201510176259.6A CN106160766A (en) | 2015-04-15 | 2015-04-15 | A kind of DC offset correction method and apparatus of zero intermediate frequency reciver |
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI627840B (en) * | 2016-12-09 | 2018-06-21 | Nat Chung Shan Inst Science & Tech | Array antenna detection correction method |
| CN108667466A (en) * | 2018-04-09 | 2018-10-16 | 成都泰格微波技术股份有限公司 | A kind of multichannel survey phase system and method based on RF transceiver chip |
| CN108736913A (en) * | 2018-05-11 | 2018-11-02 | 深圳国人通信股份有限公司 | The calibration method and system of the DC component of zero intermediate frequency transceiving chip |
| CN109560825A (en) * | 2018-12-06 | 2019-04-02 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Zero intermediate frequency reciver quadrature error bearing calibration |
| CN110113067A (en) * | 2019-04-22 | 2019-08-09 | 智为博程电子科技(苏州)有限公司 | A kind of IQ disequilibrium regulating device and method for zero intermediate frequency reciver |
| CN110879402A (en) * | 2019-11-28 | 2020-03-13 | 中国科学院国家空间科学中心 | System and method for eliminating direct current component in GNSS interference measurement of high and medium altitudes |
| CN111211785A (en) * | 2018-11-22 | 2020-05-29 | 瑞昱半导体股份有限公司 | Correction method applied to digital-to-analog converter and related circuit |
| CN112737610A (en) * | 2020-12-29 | 2021-04-30 | 芯翼信息科技(上海)有限公司 | Method and device for estimating and calibrating direct current offset |
| CN113497625A (en) * | 2020-04-02 | 2021-10-12 | 意法半导体股份有限公司 | Converter circuit, corresponding device and offset compensation method |
| CN113670357A (en) * | 2021-08-03 | 2021-11-19 | 深圳市汇川技术股份有限公司 | Signal processing method and circuit |
| CN114337699A (en) * | 2021-12-14 | 2022-04-12 | 中国电子科技集团公司第三十八研究所 | Self-adaptive carrier cancellation device and method of zero-intermediate-frequency transmitter |
| CN113670357B (en) * | 2021-08-03 | 2024-06-21 | 深圳市汇川技术股份有限公司 | Signal processing method and circuit |
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| CN104811404A (en) * | 2015-04-14 | 2015-07-29 | 华南理工大学 | DC deviation correcting method and device |
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- 2015-04-15 CN CN201510176259.6A patent/CN106160766A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104811404A (en) * | 2015-04-14 | 2015-07-29 | 华南理工大学 | DC deviation correcting method and device |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI627840B (en) * | 2016-12-09 | 2018-06-21 | Nat Chung Shan Inst Science & Tech | Array antenna detection correction method |
| CN108667466A (en) * | 2018-04-09 | 2018-10-16 | 成都泰格微波技术股份有限公司 | A kind of multichannel survey phase system and method based on RF transceiver chip |
| CN108667466B (en) * | 2018-04-09 | 2019-12-03 | 成都泰格微波技术股份有限公司 | A kind of multichannel survey phase system and method based on RF transceiver chip |
| CN108736913A (en) * | 2018-05-11 | 2018-11-02 | 深圳国人通信股份有限公司 | The calibration method and system of the DC component of zero intermediate frequency transceiving chip |
| CN111211785B (en) * | 2018-11-22 | 2023-04-07 | 瑞昱半导体股份有限公司 | Correction method applied to digital-to-analog converter and related circuit |
| CN111211785A (en) * | 2018-11-22 | 2020-05-29 | 瑞昱半导体股份有限公司 | Correction method applied to digital-to-analog converter and related circuit |
| CN109560825A (en) * | 2018-12-06 | 2019-04-02 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Zero intermediate frequency reciver quadrature error bearing calibration |
| CN110113067A (en) * | 2019-04-22 | 2019-08-09 | 智为博程电子科技(苏州)有限公司 | A kind of IQ disequilibrium regulating device and method for zero intermediate frequency reciver |
| CN110879402A (en) * | 2019-11-28 | 2020-03-13 | 中国科学院国家空间科学中心 | System and method for eliminating direct current component in GNSS interference measurement of high and medium altitudes |
| CN113497625A (en) * | 2020-04-02 | 2021-10-12 | 意法半导体股份有限公司 | Converter circuit, corresponding device and offset compensation method |
| CN112737610A (en) * | 2020-12-29 | 2021-04-30 | 芯翼信息科技(上海)有限公司 | Method and device for estimating and calibrating direct current offset |
| CN113670357A (en) * | 2021-08-03 | 2021-11-19 | 深圳市汇川技术股份有限公司 | Signal processing method and circuit |
| CN113670357B (en) * | 2021-08-03 | 2024-06-21 | 深圳市汇川技术股份有限公司 | Signal processing method and circuit |
| CN114337699A (en) * | 2021-12-14 | 2022-04-12 | 中国电子科技集团公司第三十八研究所 | Self-adaptive carrier cancellation device and method of zero-intermediate-frequency transmitter |
| CN114337699B (en) * | 2021-12-14 | 2023-05-09 | 中国电子科技集团公司第三十八研究所 | Self-adaptive carrier cancellation device and method for zero intermediate frequency transmitter |
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