TWI627840B - Array antenna detection correction method - Google Patents

Abstract

The invention is an array antenna detection and correction method, which firstly analyzes the gain size through the signal analyzer to perform gain attenuation compensation, and then uses a DC offset generator to generate a set of known DC offsets to be added to the signal, thereby The signal is corrected at the receiving end by comparing the available phase offsets. This method is used to reduce the computational complexity and speed up the correction.

Description

Array antenna detection correction method

The invention relates to wireless communication technology, in particular to an array antenna detection and correction method for detecting antenna faults and corrections.

The array antenna is a commonly used device for modern wireless communication and radar technology, especially in the field of wireless communication. In order to meet the next-generation access system technology, the preliminary technical common points of the various national communication research institutions are all using the millimeter wave (Millimeter) frequency band above 30 GHz. , array antennas, massive multiple input multiple output (Massive MIMO) and beam steering (Beamsteering) technology solutions, will completely subvert the design thinking of existing radio frequency (RF) technology. For the array antenna, when the T/R module is aging or other reasons fail, it is usually impossible to return to the original factory for the far-field test system, in order to detect the fault first in the field condition and reduce the related detection and correction cost. Verifying the correlation between the reference antenna unit and the array antenna unit, thereby performing phase modulation correction on the system is a feasible correction method that can provide fast, simple, low cost and easy implementation.

In order to solve the shortcomings of the prior art, the present invention provides an array antenna detection and correction method, which first analyzes the gain magnitude through the signal analyzer to perform gain attenuation compensation, and then uses the DC offset generator to generate a set of known DCs. The offset is added to the signal, whereby the phase offset is compared with the original signal at the receiving end for antenna correction. This method is used to reduce the computational complexity and speed up the correction.

To achieve the above and other objects, the present invention provides an array antenna detection and correction method for detecting and correcting an array antenna having a plurality of antenna elements to be tested, the steps of which include: (A) a signal generator providing a gain test signal Up to the antenna unit to be tested, the antenna unit to be tested transmits the gain test signal to a reference antenna unit; (B) the reference antenna unit transmits the received gain test signal to a signal analyzer to perform the test The gain analysis of the antenna unit and establishing a gain correction table; (C) the signal generator provides a phase test signal, the phase test signal is added to the DC offset, and then transmitted together with the phase test signal without the DC offset added Up to the antenna unit to be tested; (D) the antenna unit to be tested transmits the phase test signal having a DC offset and no DC offset to the reference antenna unit, and the reference antenna unit transmits the received phase test signal Go to the signal analyzer to obtain a phase offset of the reference antenna unit and establish a phase correction table; (E) the signal generator generates a final measurement a signal, before the final test signal is transmitted by the antenna unit to be tested, performing compensation/attenuation gain on the antenna unit to be tested according to the gain correction table, and performing phase correction on the antenna unit to be tested according to the phase correction table; (F) Repeat steps (A) to (E) for the other antenna unit to be tested until all the antenna units to be tested complete the detection correction.

In an embodiment of the invention, an array of methods of the invention is applied The antenna detection and correction system has a signal generator, a DC offset generator, a signal analyzer, a one-liter/down-frequency circuit, a plurality of transmitting/receiving circuits, and an array antenna; the array antenna is composed of a plurality of samples to be tested An antenna unit, wherein the transmitting/receiving circuits have control chips, and each of the transmitting/receiving circuits respectively corresponds to an antenna unit to be tested to control the antenna units to be tested to transmit or receive signals; the transmitting/receiving circuit has a shift a phaser to change or correct the phase of the antenna unit to be tested.

In an embodiment of the present invention, the array antenna detection and correction system further includes a reference antenna unit, and the reference antenna unit is configured to receive signals sent by the antenna units to be tested and transmit the signals back to the signal analyzer to The performance of the antenna unit to be tested is detected and corrected.

In an embodiment of the present invention, the array antenna detection and correction system further includes a microprocessor for controlling the operation of each component of the array antenna detection correction system, and establishing the signal according to the received gain test signal. a gain correction table of the antenna unit to be tested, and a phase correction table of the antenna unit to be tested is established according to the received phase test signal.

In another embodiment of the present invention, the step of detecting the alignment method of the array antenna includes: the microprocessor sends an enable signal to one of the transmitting/receiving circuits, and turns on a group of antenna units to be tested and the reference antenna unit to prepare for Detecting the correction, and the remaining antenna units to be tested are turned off; the microprocessor controls the signal generator to generate m sets of gain test signals to the antenna unit to be tested, and the antenna unit to be tested transmits the m sets of gain test signals to the reference antenna unit ; reference After receiving the gain test signals, the antenna unit returns to the signal analyzer, and the signal analyzer performs gain analysis on the received signal and transmits the signal back to the microprocessor, and the microprocessor establishes the antenna unit to be tested. a gain correction table; the microprocessor controls the signal generator to generate n sets of phase test signals, and simultaneously transmits the n sets of phase test signals to the up/down circuit and the DC offset generator, the DC offset generation The n sets of phase test signals are added to the DC offset, and the phase test signals having the DC offset are transmitted to the up/down circuit; the rise/down circuits have DC offsets And a phase test signal with no DC offset is sent to the reference antenna unit via the antenna unit to be tested, and the antenna unit to be tested is compensated/attenuated according to the gain correction table; the reference antenna unit will receive the signal The phase test signals are transmitted to the signal analyzer to obtain two sets of I and Q values (both DC offset and no DC offset), and the microprocessor compares the two sets of I and Q values to obtain the antenna unit to be tested. Phase a bit offset, the phase correction table of the antenna unit to be tested is established; the microprocessor control signal generator outputs a final test signal to the antenna unit to be tested, and the rise/fall is performed before the antenna unit to be tested transmits a signal The frequency circuit performs a compensation/attenuation gain on the antenna unit to be tested according to the gain correction table, and the transmitting/receiving circuit performs phase correction on the antenna unit to be tested through the phase shifter according to the phase correction table, thereby completing the antenna to be tested. Correction action of the unit; after completing the correction of the antenna unit to be tested, the other antenna units to be tested are sequentially detected and corrected, and finally the correction of the entire antenna unit to be tested is completed.

In an embodiment of the invention, wherein m sets of gain test signals are The m range can be determined by a random distribution method such as a Gaussian probability distribution, or can be determined by the user according to the actual calibration speed and accuracy requirements.

In an embodiment of the present invention, the signal analyzer performs a gain analysis of the antenna unit to be tested according to the gain test signal received by the reference antenna unit, and calculates an average value to establish a gain correction table of the antenna unit to be tested. The method of averaging may be root mean square or other means.

In an embodiment of the present invention, the gain test signal received by the reference antenna unit is two sets of waveforms, and the peak value is subtracted to obtain the gain value, and is stored in the gain correction table.

In an embodiment of the invention, the DC offset generator is controlled by a controller to generate a specified DC offset; the DC offset generator is a voltage level shifter, a biaser or other type of voltage Offset device.

In an embodiment of the present invention, the n range of the n sets of calibration test signals may be determined by a random distribution method such as a Gaussian probability distribution, or may be determined by the user according to actual correction speed and accuracy requirements.

In an embodiment of the invention, the DC offset signal generated by the DC offset generator needs to be a digitally modulated signal, which may be QPSK, 8PSK, APSK or other kinds of digital modulated signals.

In an embodiment of the present invention, the reference antenna unit receives the phase test signal (including two phase test signals having a DC offset and no DC offset) transmitted by the antenna unit to be tested, and then transmits the phase test signal to the antenna test unit. The signal analyzer has two circles of the constellation, one of which has a DC offset and one of which has no. Then through the meter Calculate, a total of n sets of phase offsets can be obtained, and the average is taken, and then the phase offset is established to establish a phase correction table. The method of taking the average may be a weighted average or other means.

In an embodiment of the present invention, after the gain correction table and the phase correction table of the antenna unit to be tested are established, before the operation (transmitting signal) of the antenna unit to be tested is performed, according to the gain correction table and the phase correction table, The up/down circuit of the array antenna system performs gain attenuation/compensation on the antenna unit to be tested, and performs phase correction through the phase shifter in the transmitting/receiving circuit to complete the self-calibration of the antenna.

The above summary, the following detailed description and the accompanying drawings are intended to further illustrate the manner, the Other objects and advantages of the present invention will be described in the following description and drawings.

S01~S06‧‧‧ method steps

S11~S18‧‧‧ method steps

11‧‧‧Signal Generator

12‧‧‧DC offset generator

13‧‧‧Signal Analyzer

14‧‧‧L/D frequency circuit

15‧‧‧Microprocessor

16‧‧‧transmit/receive circuit

17‧‧‧Array antenna

21‧‧‧Multiplier

22‧‧‧Control wafer

23‧‧‧Digital Control Amplifier

24‧‧‧ Coupler

25‧‧‧Power Detector

31‧‧‧Control chip

32‧‧‧ antenna end

33‧‧‧Power splitter

41‧‧‧Array antenna

411‧‧‧ antenna to be tested

42‧‧‧Reference antenna

43‧‧‧transmit/receive circuit

44‧‧‧L/D frequency circuit

45‧‧‧DC offset generator

46‧‧‧Signal Generator

47‧‧‧Signal Analyzer

48‧‧‧ computer

1 is a step diagram of a method for detecting and correcting an array antenna of the present invention.

2 is a schematic structural diagram of an array antenna detection and correction system applied to the present invention.

3 is a flow chart showing another embodiment of the array antenna detection and correction method of the present invention.

4 is a configuration diagram of an embodiment of a rising/downsizing circuit of the present invention.

FIG. 5 is a configuration diagram of an embodiment of a transmitting/receiving circuit of the present invention.

FIG. 6 is a constellation diagram of an embodiment of the array antenna detection and correction method of the present invention.

7 is an array antenna inspection using the array antenna detection and correction method of the present invention. A schematic diagram of another embodiment of the calibration system.

FIG. 8 is a schematic diagram of comparison of an antenna correction table matrix (including the gain correction table and the phase correction table) and an array antenna according to the present invention.

The embodiments of the present invention are described below by way of specific examples, and those skilled in the art can readily appreciate other advantages and functions of the present invention from the disclosure herein.

The array antenna detection and correction method of the present invention is applied to an array antenna system for wireless communication, military and civilian radar, and is used for detecting and correcting an array antenna having a plurality of antenna units to be tested, and FIG. 1 is an array antenna detection and correction method of the present invention. The step diagram, as shown in the figure, includes: (A) a signal generator providing a gain test signal to an antenna unit to be tested, the antenna unit to be tested transmitting the gain test signal to a reference antenna unit S01; (B) The reference antenna unit transmits the received gain test signal to a signal analyzer for performing gain analysis of the antenna unit to be tested, and establishes a gain correction table S02; (C) the signal generator provides a phase test signal, The phase test signal is added with a DC offset, and then transmitted to the antenna unit S03 to be tested together with the phase test signal without the DC offset added; (D) the antenna unit to be tested transmits the DC offset and does not have a DC Offset phase test signal to the reference antenna unit, the reference antenna unit transmits the received phase test signal to the signal analyzer to obtain the reference day a phase shift amount of the line unit, and establishing a phase correction table S04; (E) the signal generator generates a final test signal, and the antenna unit to be tested transmits the Before the final test signal, the compensation/attenuation gain of the antenna unit to be tested is performed according to the gain correction table, and the antenna unit to be tested is subjected to phase correction S05 according to the phase correction table; (F) repeating steps for another antenna unit to be tested The action of (A)~(E) until all the antenna elements to be tested complete the detection correction S06.

In an embodiment of the present invention, a schematic diagram of an array antenna detection and correction system used in the present invention is shown in FIG. 2. The array antenna system has a signal generator 11, a DC offset generator 12, and a signal analyzer. 13. A liter/down circuit 14, a microprocessor 15, a plurality of transmitting/receiving circuits 16 and an array antenna 17; the array antenna is composed of a plurality of antenna units to be tested, and the transmitting/receiving circuits have Controlling the chip, each of the transmitting/receiving circuits respectively corresponding to an antenna unit to be tested to control the transmitting or receiving signals of the antenna unit to be tested; the transmitting/receiving circuit has a phase shifter (not shown) to change or correct the The phase of the antenna unit to be tested. The array antenna system to which the present invention is applied further includes a reference antenna unit (not shown) for receiving signals from the antenna units to be tested and transmitting back signals to the signal analyzer to The performance of the antenna unit is tested and corrected.

Another embodiment step of the array antenna detection and correction method of the present invention is shown in FIG. 3 (refer to FIG. 2 for the component composition relationship), and the step includes: the microprocessor sends an open signal to one of the transmitting/receiving circuits, and turns on. a set of antenna units to be tested and the reference antenna unit are ready for detection and correction, and the remaining antenna units to be tested are closed to S11; the microprocessor controls the signal generator to generate m sets of gain test signals to the antenna unit to be tested, The antenna unit transmits the m The group gain test signal is sent to the reference antenna unit S12; after receiving the gain test signals, the reference antenna unit returns to the signal analyzer, and the signal analyzer performs gain analysis on the received signal and returns the signal to the micro a processor, the microprocessor establishes a gain correction table S13 of the antenna unit to be tested; the microprocessor controls the signal generator to generate n sets of phase test signals, and simultaneously transmits the n sets of phase test signals to the up/down frequency a circuit and the DC offset generator, the DC offset generator adds the n sets of phase test signals to the DC offset, and transmits the DC offset phase test signals to the up/down circuit S14 The rising/downsizing circuit sends the phase test signal having the DC offset and the DC offset to the reference antenna unit via the antenna unit to be tested, and the antenna unit to be tested according to the gain correction table Performing a compensation/attenuation gain S15; the reference antenna unit transmits the received phase test signals to the signal analyzer to obtain two sets of I and Q values (both DC offset and no DC offset, respectively). The microprocessor compares the two sets of I and Q values to obtain a phase offset of the antenna unit to be tested, and establishes a phase correction table S16 of the antenna unit to be tested; the microprocessor control signal generator outputs a final test signal to the The antenna unit to be tested, before the signal to be tested transmits a signal, the up/down circuit performs a compensation/attenuation gain on the antenna unit to be tested according to the gain correction table, and the transmitting/receiving circuit transmits the signal according to the phase correction table. The phase shifter performs phase correction on the antenna unit to be tested, and thus completes the correcting action S17 of the antenna unit to be tested; after completing the correction of the antenna unit to be tested, the other antenna units to be tested are sequentially detected and corrected, and finally completed. Correction S18 for the entire antenna unit to be tested.

The array antenna detection and correction method of the present invention, in one embodiment, the configuration diagram of the embodiment of the up/down frequency circuit is as shown in FIG. 4, and the up/down circuit includes an oscillator to generate a reference clock. The reference clock is first up-converted by the frequency multiplier 21 to increase the frequency, and the up-clocked clock is divided into two paths by the power splitter. Each path is then amplified by an amplifier, and finally a local mixer is provided to provide a mixer for the transmit and receive paths. The transmit/receive circuit transmit and receive paths are transmitted by the control chip 22 inside the circuit to the switch switch. In the path of the transmission, the signal from the signal generator or DC offset generator (not shown) is first boosted by the amplifier and digitally controlled amplifier (DCA) 23, filtered by the bandpass filter, and then into the mixer. The local signals are combined and the RF signal is output via a series of driver amplifiers and power amplifiers. Finally, the RF signal is split into two paths through a coupler 24, the first path is transmitted to the switch and flows through the filter to the power splitter, and the second path first comes to the power detector (PD) 25 The signal is sized and passed back to the control chip 22 inside the up/down circuit to adjust the gain of the digital control amplifier output based on the transmit signal gain and power strength requirements. In the receiving path, the RF signal received from the power splitter sequentially flows through the filter and the switch, and then amplifies the signal through a plurality of serially connected low noise amplifiers, and the gain is controlled by a programmable gain amplifier (VGA). The mixer combines with the local signal to remove the carrier and finally restores the original signal through a bandpass filter and amplifier. The signal is split into two paths through the coupler 24, the first path directly transmits the signal to the signal analyzer (not shown), and the second path first comes to the power detector. The (PD) 25 measures the signal size and passes the message back to the control chip inside the up/down circuit to adjust the gain of the programmable gain amplifier output based on the received signal gain and power strength requirements.

Array Antenna Detection Correction Method of the Present Invention In one embodiment, the configuration architecture diagram of the transmit/receive circuit embodiment is as shown in FIG. 5, and the transmit/receive circuit is divided into three paths: a common path, a transmit path, and a receive path. The transmitting and receiving circuit includes a control chip 31 integrated with three paths, and the internal two sets of switching circuits are respectively located at the transmitting path and the receiving path connecting the antenna end 32 and the common path to perform function switching of transmitting or receiving. One end of the common path is connected to the power splitter 33, and the other end is connected to the transmit path and the receive path. The common path includes a phase shifter and an attenuator. The maximum phase shift angle and resolution of the phase shifter can be combined according to requirements. The maximum attenuation range and resolution of the attenuator can also be selected according to requirements. In the detecting or correcting mode, the microprocessor (not shown) of the present invention sends a signal to the control chip 31 inside the transmitting/receiving circuit, and sends a control signal to control the phase shifter and the attenuator to adjust the phase and gain size; Control the corresponding antenna (the antenna unit to be tested) to be turned on or off. The transmit path is a combination of multi-stage amplifiers (including driver amplifiers and power amplifiers) that can be cascaded in different quantities depending on gain and power requirements. The receive path uses low noise amplifiers and bandpass filters for high gain and low noise. The receiving path and the transmitting path are connected to the conversion circuit for circuit matching, and are connected to the antenna end to transmit or receive signals.

An embodiment of the array antenna detection and correction method of the present invention After the signal analyzer receives the phase test signal transmitted by the antenna unit to be tested through the reference antenna unit, the Y-axis coordinate value of the mesh node is calculated, and the gain size can be detected, and the I can be extracted. The Q coordinate value can be obtained by calculating the chart.

In an embodiment of the present invention, the phase correction table obtains an offset caused by aging of the antenna element by a known DC offset to perform phase correction of the antenna. First, the antenna unit to be tested transmits an original signal (ie, a phase test signal without a DC offset), and a phase test signal with a known DC offset inserted therein, and the reference antenna unit first compensates by using a gain correction table. / Attenuate its gain, and then analyze it through the signal analyzer, two circles are obtained in the I and Q constellation diagrams, and the phase angles of the two circles are respectively , . The array antenna detection and correction method of the present invention is shown in FIG. 6 for the constellation diagram of an embodiment. The difference between the two phase angles is determined by the relative offset caused by the known DC ( ), there will be a known DC offset signal phase angle Phase angle with original signal (no DC offset, no gain compensation attenuation) Relative offset between Subtracting the relative offset caused by the known DC, the offset caused by the antenna element can be obtained ( ), the last offset Stored in the phase correction table for subsequent calibration.

FIG. 7 is a schematic diagram of another embodiment of an array antenna detection and correction system for applying the array antenna detection and correction method of the present invention. As shown in the figure, the embodiment includes: an array antenna 41, which is composed of a plurality of antennas 411 to be tested; a reference antenna 42; a complex transmit/receive circuit 43 for individually connecting one to be tested An antenna; a liter/down circuit 44 is coupled to the transmit/receive circuits; a DC offset generator 45; a signal generator 46 (i.e., the signal generator described above); a signal analyzer 47 (ie, The signal analyzer described above; and a computer 48 (i.e., the microprocessor described above). The operation flow of the embodiment is: the computer sends a control signal to all the transmitting/receiving circuits, only the antenna unit to be tested is turned on, and the rest are turned off; the m-group gain test signal is generated by the signal generator through the rising/lowering circuit The antenna to be tested is transmitted to the reference antenna via the antenna to be tested, and then transmitted back to the signal analyzer for gain analysis, and a gain correction table is established; the signal generator generates n sets of phase test signals to the antenna to be tested, wherein the phase test signal The transmission path is divided into two paths, one channel is directly transmitted to the up/down circuit, and the other path is first passed through the DC offset generator, and the DC offset is added to the phase test signal of the path, and then transmitted to the up/down circuit. The antenna to be tested transmits the phase test signals of the two paths to the reference antenna, and simultaneously compensates or attenuates the antenna to be tested according to the gain correction table through the up/down circuit; the reference antenna receives the two phase test signals. Passed to the signal analyzer, you can get two sets of I and Q values, compare the two sets of I and Q values to draw the constellation of the antenna to be tested, and the constellation map can obtain the test day. Phase offset amount, thereby establishing a phase correction table of the antenna; after completing the gain correction table and the phase correction table of all the antennas to be tested according to the above steps, before the signal is transmitted through the array antenna, the gain correction table is used to raise/lower The frequency circuit performs compensation or attenuation gain, and phase corrects the antenna through the phase shifter in the transmitting/receiving circuit according to the phase correction table, and finally completes the detection and correction operation of the array antenna.

In an embodiment of the present invention, the gain correction table and the phase correction table format are both a matrix. Please refer to the antenna correction table matrix of the present invention in FIG. 8 (including the gain correction table and the phase). A comparison of the calibration table with the array antenna. It can be seen from the figure that each set of values in the matrix corresponds to an individual antenna in the array antenna, and the user can calculate and analyze the correction table through a microprocessor, and perform gain control and phase control on the individual antennas according to the same.

In summary, the array antenna detection and correction method of the present invention can be applied to an array antenna system for wireless communication and military and civilian radars for detecting and correcting an array antenna having a plurality of antenna units to be tested, so that the antenna transmits signals. It can automatically correct the gain and phase error caused by long-term component aging or other internal and external factors. The gain correction table and the phase correction table established by the invention can correct the gain and phase error of the array antenna in real time, and can also store the calibration table as a detection record in the microprocessor to provide a reference for the user during operation and maintenance. data. The operation and correction method used in the invention is simple, and based on the inherent architecture design of the array antenna system, the effect of the immediate detection and correction of the array antenna system in use can be achieved by requiring a small number of additional components or no additional components.

The above-described embodiments are merely illustrative of the features and functions of the present invention, and are not intended to limit the scope of the technical scope of the present invention. Modifications and variations of the above-described embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention, It should be listed in the scope of patent application as described later.

Claims (6)

An array antenna detection and correction method for detecting and correcting an array antenna having a plurality of antenna elements to be tested, wherein the step of detecting the correction method of the array antenna comprises: (A) a signal generator providing a gain test signal to an antenna to be tested a unit, the antenna unit to be tested transmits the gain test signal to a reference antenna unit; (B) the reference antenna unit transmits the received gain test signal to a signal analyzer to perform gain analysis of the antenna unit to be tested And establishing a gain correction table; (C) the signal generator provides a phase test signal, adding the phase test signal to the DC offset, and transmitting the phase test signal to the antenna to be tested together with the phase test signal without the DC offset added thereto a unit (D) transmitting the phase test signal having a DC offset and a DC offset to the reference antenna unit, the reference antenna unit transmitting the received phase test signal to the signal analyzer Obtaining a phase offset of the reference antenna element and establishing a phase correction table; (E) the signal generator generates a final test signal, where Before the antenna unit transmits the final test signal, the compensation/attenuation gain of the antenna unit to be tested is performed according to the gain correction table, and then analyzed by the signal analyzer, and two circles are obtained in an I and Q constellation diagram. The phase angles of the circles are , Find the difference between the two phase angles to obtain the relative offset caused by the known DC ), there will be a known DC offset signal phase angle Phase angle with the original signal Relative offset between Subtracting the relative offset caused by the known DC, the offset caused by the antenna element can be obtained ( ), the last offset Depositing in the phase correction table, performing phase correction on the antenna unit to be tested according to the phase correction table; (F) repeating steps (A) to (E) to another antenna unit to be tested until all antennas to be tested are performed The unit completes the detection correction. An array antenna detection and correction method for detecting and correcting an array antenna having a plurality of antenna units to be tested, wherein the step of detecting the correction method of the array antenna comprises: a microprocessor issuing an enable signal to turn on a group of antenna units to be tested and the Referring to the antenna unit, the remaining antenna unit to be tested is turned off; the microprocessor controls a signal generator to generate a gain test signal to the antenna unit to be tested, and the antenna unit to be tested transmits the gain test signal to the reference antenna unit; After receiving the gain test signals, the antenna unit returns to a signal analyzer, and the signal analyzer performs gain analysis on the received gain test signal and returns the data to the microprocessor, and the microprocessor establishes the test to be tested. a gain correction table of the antenna unit; the microprocessor controls the signal generator to generate a phase test signal, and simultaneously transmits the phase test signal to a one-liter/down-frequency circuit and a DC offset generator, and the DC offset generator The phase test signal is added with a DC offset, and the phase test signals having the DC offset are transmitted to the rise/fall a circuit for transmitting a phase test signal having a DC offset and a DC offset without the DC offset to the reference antenna unit, and the antenna to be tested according to the gain correction table The unit performs compensation/attenuation gain; the reference antenna unit transmits the received phase test signals to the signal analyzer to obtain two sets of I and Q values (both DC offset and no DC offset), the micro The processor compares the two sets of I and Q values to obtain a phase offset of the antenna unit to be tested, establishes a phase correction table of the antenna unit to be tested, and analyzes the signal through the signal analyzer, in an I and Q constellation diagram. Two circles, the phase angles of the two circles are , Find the difference between the two phase angles to obtain the relative offset caused by the known DC ), there will be a known DC offset signal phase angle Phase angle with the original signal Relative offset between Subtracting the relative offset caused by the known DC, the offset caused by the antenna element can be obtained ( ), the last offset Deposited in the phase correction table; the microprocessor controls the signal generator to generate a final test signal to the antenna unit to be tested, and the up/down circuit according to the gain correction table before the antenna unit to be tested transmits a signal Performing compensation/attenuation gain on the antenna unit to be tested, and a transmitting/receiving circuit performs phase correction on the antenna unit to be tested through the phase shifter according to the phase correction table, thereby completing the correcting action of the antenna unit to be tested; After the antenna unit to be tested is corrected, the other antenna units to be tested are detected and corrected in sequence, and finally the correction of the entire antenna unit to be tested is completed. The array antenna detection correction method according to claim 1 or 2, wherein the gain correction table is in a matrix format. The array antenna detection correction method according to claim 1 or 2, wherein the phase correction table is in a matrix format. The array antenna detection and correction method of claim 2, wherein the DC offset generator is a voltage level shifter, a biaser or other type of voltage offset device. The array antenna detection and correction method of claim 2, wherein the DC offset signal generated by the DC offset generator needs to be a digitally modulated signal, which may be QPSK, 8PSK, APSK or other kinds of digital modulation signals. .