CN103326735A - Direct current offset correcting method of wireless medium-frequency receiving circuit system - Google Patents
Direct current offset correcting method of wireless medium-frequency receiving circuit system Download PDFInfo
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- CN103326735A CN103326735A CN201310255477XA CN201310255477A CN103326735A CN 103326735 A CN103326735 A CN 103326735A CN 201310255477X A CN201310255477X A CN 201310255477XA CN 201310255477 A CN201310255477 A CN 201310255477A CN 103326735 A CN103326735 A CN 103326735A
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Abstract
The invention discloses a direct current offset correcting method of a wireless medium-frequency receiving circuit system. In a medium-frequency receiving circuit, after wireless radio-frequency signals are received by an antenna, the wireless radio-frequency signals are amplified through a low-noise amplifier. Then frequency mixing is conducted by a frequency mixer and an oscillator so that medium-frequency signals with low frequency are generated. A direct current offset portion generated by the low-noise amplifier and the frequency mixer enters and an amplifier a complex band pass filter through a channel I and a channel Q and then enters an equal module of a complex band pass analog-digital converter, and digital signals are output to a base band. A whole correcting flow is stable and high in reliability. The direct current offset of all circuit modules to an output end on a medium-frequency circuit signal route until the base belt portion is reduced to a level approaching zero, so that the influence on the medium-frequency circuit by the direct current offset is eliminated and the dynamic range for the wireless system to receive the signals is improved.
Description
Technical field
The present invention relates to intermediate frequency (IF) the receiving circuit system in semiconductor technology and circuit design technique, particularly radio frequency (RF) circuit in the electronic engineering, and the complex bandpass filters that comprises and amplifier circuit module.
Background technology
Generally include antenna (Antenna) in radio frequency (RF) receiving circuit, low noise amplifier (LNA), frequency mixer (Mixer), low pass filter (LPF), signal amplifier (VGA), the modules such as analog to digital converter (ADC).If take the mode of direct conversion (Direct Conversion), receive the leakage that easily intercouples of signal path and oscillator (LO) clock path in the frequency mixer stage, cause so self-mixing and produce DC deviation.For fear of this problem, the modes of intermediate frequency (IF) circuit have been adopted in a lot of designs, namely are divided into two stages to isolate original signal from the RF signal.Phase I uses the frequency slightly be lower than emission LO clock to carry out mixing at frequency mixer, at this moment will use complex bandpass filters (BPF) and amplifier (VGA) to replace low pass filter (LPF) and amplifier (VGA) in direct conversion (Direct Conversion) circuit; Second stage decodes original signal in base band with digital form.The DC deviation that causes of the frequency mixer of medium-frequency IF circuit reduces greatly like this, and the main source of DC deviation no longer is the self-mixing of mixer module, but other factors are asymmetric such as difference channel, it is especially obvious when the gain of process deviation etc., particularly circuit is large.
The difficult point that the DC deviation of medium-frequency IF receiving circuit is proofreaied and correct is: be Complex frequency because intermediate-frequency circuit processes, so I passage and Q channel circuit have the interaction feedback effect.For the I passage or the Q passage that separate, owing to there not being the existence of feedback loop, then the DC deviation timing output direct current biasing of only need sampling carries out disposable current compensation and just direct current biasing can be dropped to very low level.But for the interaction feedback of I passage and Q channel circuit, even behind the I channel correcting, in the process of proofreading and correct the Q passage, may allow the direct current biasing of I passage get back to very poor level.Even to I passage and Q passage recirculation correction, the direct current biasing of output may not restrained, be difficult to be reduced to desirable level.This situation in high-gain is especially obvious, because at this moment the sensitivity of circuit is larger.
At present a lot of medium-frequency IF receiving circuits still adopt the I passage of complex bandpass filters (BPF) and amplifier (VGA) and the recirculation correction of Q passage, then obtain (80mv-100mv) till the DC deviation of less, meeting is so that the rear one-level analog to digital converter (ADC) of if bandpas filter (BPF) and amplifier (VGA) is easy to saturated like this, dynamic range of signals reduces, thereby reduces the performance of system; And this mode be owing to can not guarantee DC deviation to minimum value, thus under the poorest situation of technique, can cause great DC deviation, so also can cause the decline of chip yield (Yield).
Although some mode solves the DC deviation that I passage and Q passage cause and interferes with each other problem, US Patent No. 2011/0037506A1 in 2011 such as high pass (Qualcomm), having increased switch in the path of I passage and the coupling of Q passage controls to separate the direct current biasing of sampling I passage and Q passage and proofread and correct, but this method has a hypothesis, be exactly the direct current biasing level that produces when the amplifier of I passage and Q passage when identical, adopt this mode direct current biasing can be dropped to extremely low-level.The mechanism ability of band pass filter direct current biasing is exactly because some random factors, the physical dimension that causes such as technique departs from, symmetry is inadequate etc., so although this mode can reduce direct current biasing in most of situations, but be not a kind of reliable method.When the direct current biasing level of I passage and Q passage different or even polarity when opposite, the result that this mode is proofreaied and correct is just undesirable.
Summary of the invention
Based at present for intermediate frequency receiver circuit, the integrity problem that comprises the dc bias circuit existence of complex bandpass filters and amplifier, the present invention is on the basis of strict theory analysis, the DC deviation bearing calibration of a kind of wireless intermediate frequency receiver circuit system has been proposed, it is characterized in that, comprise the steps:
A. design of circuit system;
B. baseband digitized DC deviation sample averaging module;
C. DC deviation sampling correction circuit;
D. the fixing correction of intermediate frequency acceptor circuit DC deviation.
Preferably, described design of circuit system comprises:
A. when intermediate frequency reception and complex bandpass filters system, use decay feedback resistance R and the coupling frequency displacement resistance R 0 of same resistance;
B. DC deviation correcting current compensation point has three places: Ii2 to access before I passage input resistance Ri, comes from the DC deviation of previous stage frequency mixer I passage output with elimination; Iq2 accessed before Q passage input resistance Ri, came from the DC deviation of previous stage frequency mixer I passage output with elimination; Iq1 is access after passage input resistance Ri, comes from the DC deviation of Q channel operation amplifier in elimination;
C. why the DC deviation of I channel operation amplifier in does not need compensation (not having current source Ii1) to be because use decay feedback resistance R and the coupling frequency displacement resistance R 0 of same resistance in claim 2a, is zero so the effect that produces at output in I channel operation amplifier DC deviation has been offseted.
Preferably, described baseband digitized DC deviation sample averaging functions of modules comprises: continuously the I passage of analog to digital converter and the numeral output of Q passage are taken a sample, basis at a plurality of samples averages, thereby obtains the mean value of the DC deviation of I passage and Q passage; This mean value is digital two complemented lattice formulas, when highest order is 1 interval scale negative value, and highest order be 0 interval scale on the occasion of.
Preferably, described DC deviation sample circuit comprises:
A.I passage and the digitlization of Q passage DC deviation mean value are judged;
B. successive approximation register algorithm logic and accordingly register;
C. multidigit high precision digital-to-analog converter;
D. controlled current source.
Preferably, the fixing aligning step of described intermediate frequency acceptor circuit DC deviation comprises:
A. chip power, system initialization is so register is established initial value 0; And with the positive-negative input end short circuit of low noise amplifier;
B. disconnect I passage and Q channel signal input end switch, regulate Iq1 compensating current element amplitude by sampling feedback circuit;
C. regulate the bit number that Iq1 compensating current element amplitude number of times depends on multidigit high precision digital-to-analog converter in the DC deviation sample circuit, until the DC deviation mean value of base-band digital part I passage and Q passage is reduced to simultaneously close to zero;
D. disconnect Q channel signal input end switch, connect I passage input end switch, regulate Ii2 compensating current element amplitude by sampling feedback circuit;
E. regulate the bit number that Ii2 compensating current element amplitude number of times depends on multidigit high precision digital-to-analog converter in the DC deviation sample circuit, until the DC deviation mean value of base-band digital part I passage and Q passage is reduced to simultaneously close to zero;
F. connect I passage and Q passage input end switch, regulate Iq2 compensating current element amplitude by sampling feedback circuit;
G. regulate Iq2 compensating current element amplitude number of times and depend on multidigit high precision digital-to-analog converter in the DC deviation sample circuit) bit number, until the DC deviation mean value of base-band digital part I passage and Q passage is reduced to simultaneously close to zero;
H. the positive-negative input end short circuit with low noise amplifier disconnects; Intermediate frequency acceptor circuit DC deviation trimming process finishes.
Preferably, described I passage and the digitlization of Q passage DC deviation mean value judge, when base band DC deviation mean value is output as 1 greater than zero the time; When base band DC deviation mean value is output as 0 less than zero the time.
Preferably, described successive approximation register algorithm logic and corresponding register generate the bit of controlling current source in the following order:
All bits all are made as zero when a. initial;
B. for the first time highest order is switched to 1 from zero, then register control digital to analog converter generates the input that corresponding offset current is delivered to complex bandpass filters, and next voltage comparator is exported according to complex bandpass filters and taken a sample, and generates comparative result; If comparator is output as 1, then highest order is left 1; Comparator is output as 0 else if, and then to be reset to be 0 to highest order;
C. the step that repeats b determines the bit value from the second highest order to lowest order successively, and after LSB finished, the value of register was exactly the last value of this compensating current element control bit; Preserve this bit value, when circuit works, use.
Preferably, the described digital to analog converter that mostly is is according to the corresponding control of the control bit position generation electric current of register; 1111111111 just to generate the DC offset compensation electric current of amplitude peak such as the control bit position; And be 0000000000 just to generate the DC offset compensation electric current of minimum radius such as the control bit position.
Preferably, described controlled current source represents DAC according to the electric current that the control bit position of register generates, and directly is linked into the I passage of plural bandwidth filter or the input of Q passage.
For the situation that I passage in complex bandpass filters and the amplifier and Q passage intercouple, the I passage in the DC deviation of filter output is:
Wherein
With
The Dc bias that I passage and Q passage complex bandpass filters and amplifier previous stage module produce, and
With
It then is this Dc bias in I passage and the generation of Q passage amplifier input of complex bandpass filters and amplifier.
Equally, the Q passage in the Dc bias of filter output is:
?
Based on above-mentioned analysis, the present invention's design is taked following mode to reduce and is offset the DC deviation that intermediate-frequency circuit produces:
A. design that R and R0 get that same resistance is come so that
The DC deviation that item generates is zero; This condition is easy to realize, because complex bandpass filters and amplifier circuit gain if R is fixed as the R0 value, can only change the purpose (VGA) that Ri reaches variable gain by the R/Ri decision;
B. increase I channel switch SWI, Ri was equivalent to ∞ when the SWI switch disconnected like this, thus so that DC deviation item
Be zero;
C. increase Q channel switch SWQ, Ri was equivalent to ∞ when the SWQ switch disconnected like this, thereby so that the DC deviation item be
Zero;
Based on above-mentioned analysis, the present invention's design takes following steps to realize that the Dc bias that reduces output arrives close to zero level:
A. when intermediate frequency reception and complex bandpass filters system, use decay feedback resistance R and the coupling frequency displacement resistance R 0 of same resistance; Like this so that in I passage and Q passage output DC deviation
The DC deviation that item generates is zero;
B. disconnect I passage and Q channel signal input end switch SWI and SWQ, so that the DC deviation item
With
All be zero; Utilize direct current biasing sampling feedback compensation circuit adjustment Iq1 current source amplitude to compensate bias current
And so that I passage and Q passage DC deviation be reduced to simultaneously close to zero;
C. disconnect Q channel signal input end switch so that
Be zero, connect I passage input end switch, regulate Ii2 current source amplitude by sampling feedback circuit and compensate bias current
And so that I passage and Q passage DC deviation be reduced to simultaneously close to zero;
D. connect I passage and Q passage input end switch, regulate Iq2 current source amplitude by sampling feedback circuit and compensate bias current
And so that I passage and Q passage DC deviation be reduced to simultaneously close to zero.
Based on above-mentioned analysis, because
With
Be respectively the DC deviation that I passage and Q passage produce in frequency mixer output, proofread and correct the DC deviation that is produced by low noise amplifier and frequency mixer so correcting mode of the present invention has comprised.
Based on above-mentioned analysis, because
With
Be respectively this Dc bias in I passage and the generation of Q passage amplifier input of complex bandpass filters and amplifier, proofread and correct the DC deviation that is produced by complex bandpass filters and amplifier so correcting mode of the present invention has comprised.
Based on above-mentioned analysis, the present invention adopts the sample averaging of baseband digitized direct current biasing at logical analog to digital converter (the Complex Band-pass ∑ ADC) digital output end of plural number band, calculate the mean value of the DC deviation of the I passage of last output and Q passage on the basis of repeatedly sampling (1000-2000 time), and pass through DC deviation feedback compensation circuit.So the result that the present invention proofreaies and correct is so that the output DC deviation of whole intermediate-frequency circuit is reduced to the level close to zero, has also comprised the DC deviation that is produced by the logical analog to digital converter (Complex Band-pass ∑ ADC) of plural number band.
Though clearly do not mention, current source compensation way of the present invention can be single-ended or differential compensation.The electrode input end of passage and negative input have compensating current element when differential compensation, and its amplitude equates but polarity is opposite.
The precision that the present invention proofreaies and correct the DC deviation of wireless intermediate frequency receiver circuit system is got the lowest order (LS less than digital to analog converter (DAC)
B) the DC deviation level of representative.So the precision of D AC is higher, the precision that final DC deviation is proofreaied and correct is also just higher.
Description of drawings
Fig. 1 is built-up circuit module and the signal path of medium-frequency IF receiving circuit;
Fig. 2 is the access way of circuit structure and the DC offset correction current source of complex bandpass filters;
Fig. 3 is the internal module figure of DC deviation sampling correction circuit;
Fig. 4 is the aligning step of intermediate frequency receiver circuit system DC deviation;
Fig. 5 is the output waveform of DC deviation correcting process.
Following embodiment describes in connection with accompanying drawing.
Embodiment
The intermediate frequency wireless receiving system that DC deviation correcting mode of the present invention is suitable for as shown in Figure 1.The RF signal is entered by antenna (101), through low noise amplifier (LNA, 102) minute two-way I passage and Q passage are sent into frequency mixer (Mixer after, 103 and 104), then pass through complex bandpass filters and amplifier (Complex BPF and VGA, 105), through becoming baseband signal behind the logical analog to digital converter (Complex Band-pass ∑ ADC, 107) of plural number band.Baseband digitized direct current biasing sample averaging module calculates the mean value of the DC deviation of the I passage of last output and Q passage on the basis of repeatedly sampling (1000-2000 time), and by DC deviation feedback compensation circuit, divide the output that then generates the control current source for three times to enter the input of complex bandpass filters and amplifier.Because in the middle of complex bandpass filters and amplifier are positioned at, so its direct current biasing also is subject to the impact of front frequency mixer and low noise amplifier.
Fig. 2 is the access way of circuit structure and the DC offset correction current source of complex bandpass filters.Design of circuit system partly comprises:
A. when intermediate frequency reception and filter system design, use decay feedback resistance R and the coupling frequency displacement resistance R 0 of same resistance;
B. DC deviation correcting current compensation point has three places: Ii2 to access before I passage input resistance Ri, comes from the DC deviation of previous stage frequency mixer I passage output with elimination; Iq2 accessed before Q passage input resistance Ri, came from the DC deviation of previous stage frequency mixer I passage output with elimination; Iq1 is access after passage input resistance Ri, comes from the DC deviation of Q channel operation amplifier in elimination;
C. why the DC deviation of I channel operation amplifier in does not need compensation (not having current source Ii1) to be because use decay feedback resistance R and the coupling frequency displacement resistance R 0 of same resistance in claim 2a, is zero so the effect that produces at output in I channel operation amplifier DC deviation has been offseted.
The module of DC deviation correcting circuit comprises in Fig. 3:
A. I passage and the digitlization of Q passage DC deviation mean value are judged
B. successive approximation register algorithm logic and accordingly register (SAR)
C. multidigit high precision digital-to-analog converter (DAC)
D. controlled current source
The aligning step that intermediate frequency receiving filter circuit DC deviation is fixed comprises as shown in Figure 4:
A. chip power, system initialization is so register is established initial value 0; Positive-negative input end short circuit with low noise amplifier (LNA);
B. disconnect I passage and Q channel signal input end switch, regulate Iq1 compensating current element amplitude by sampling feedback circuit;
C. regulate the bit number that Iq1 compensating current element amplitude number of times depends on multidigit high precision digital-to-analog converter (DAC) in the DC deviation sample circuit, until the DC deviation mean value of base-band digital part I passage and Q passage is reduced to simultaneously close to zero;
D. disconnect Q channel signal input end switch, connect I passage input end switch, regulate Ii2 compensating current element amplitude by sampling feedback circuit;
E. regulate the bit number that Ii2 compensating current element amplitude number of times depends on multidigit high precision digital-to-analog converter (DAC) in the DC deviation sample circuit, until the DC deviation mean value of base-band digital part I passage and Q passage is reduced to simultaneously close to zero;
F. connect I passage and Q passage input end switch, regulate Iq2 compensating current element amplitude by sampling feedback circuit;
G. regulate the bit number that Iq2 compensating current element amplitude number of times depends on multidigit high precision digital-to-analog converter (DAC) in the DC deviation sample circuit, until the DC deviation mean value of base-band digital part I passage and Q passage is reduced to simultaneously close to zero;
H. the positive-negative input end short circuit with low noise amplifier (LNA) disconnects; Intermediate frequency receiving filter circuit DC deviation trimming process finishes.
Fig. 5 is the oscillogram of DC deviation in continuous three trimming processes.The DC deviation of proofreading and correct each time I and Q passage all is reduced to almost nil simultaneously.But when switching over, the DC deviation of I passage and Q passage is variation again, so correction is reduced to DC deviation again almost nil next time.At last when all switches are opened, correcting process is reduced to direct current biasing when almost nil, and at this moment the state of switch also is the state of circuit normal operation, so during normal operation, the DC deviation of the circuit after overcorrect is also almost nil.
Current source compensation way of the present invention can be single-ended or differential compensation.The electrode input end of passage and negative input have compensating current element when differential compensation, and its amplitude equates but polarity is opposite.
More than be depicted as the specific embodiment of the present invention, but protection scope of the present invention is not limited to this.Any professional and technical personnel who is familiar with the art is in technical scope disclosed by the invention, and the variation of being expected easily or replacement all should be encompassed within protection scope of the present invention.
Claims (9)
1. the DC deviation bearing calibration of a wireless intermediate frequency receiver circuit system is characterized in that, comprises the steps:
A. design of circuit system;
B. baseband digitized DC deviation sample averaging module;
C. DC deviation sampling correction circuit;
D. the fixing correction of intermediate frequency acceptor circuit DC deviation.
2. the according to claim 1 DC deviation bearing calibration of described a kind of wireless intermediate frequency receiver circuit system is characterized in that, described design of circuit system comprises:
A. when intermediate frequency reception and complex bandpass filters system, use decay feedback resistance R and the coupling frequency displacement resistance R 0 of same resistance;
B. DC deviation correcting current compensation point has three places: Ii2 to access before I passage input resistance Ri, comes from the DC deviation of previous stage frequency mixer I passage output with elimination; Iq2 accessed before Q passage input resistance Ri, came from the DC deviation of previous stage frequency mixer I passage output with elimination; Iq1 is access after passage input resistance Ri, comes from the DC deviation of Q channel operation amplifier in elimination;
C. why the DC deviation of I channel operation amplifier in does not need compensation (not having current source Ii1) to be because use decay feedback resistance R and the coupling frequency displacement resistance R 0 of same resistance in claim 2a, is zero so the effect that produces at output in I channel operation amplifier DC deviation has been offseted.
3. the according to claim 2 DC deviation bearing calibration of described a kind of wireless intermediate frequency receiver circuit system, it is characterized in that, described baseband digitized DC deviation sample averaging functions of modules comprises: continuously the I passage of analog to digital converter and the numeral output of Q passage are taken a sample, basis at a plurality of samples averages, thereby obtains the mean value of the DC deviation of I passage and Q passage; This mean value is digital two complemented lattice formulas, when highest order is 1 interval scale negative value, and highest order be 0 interval scale on the occasion of.
4. the according to claim 2 DC deviation bearing calibration of described a kind of wireless intermediate frequency receiver circuit system is characterized in that, described DC deviation sample circuit comprises:
A.I passage and the digitlization of Q passage DC deviation mean value are judged;
B. successive approximation register algorithm logic and accordingly register;
C. multidigit high precision digital-to-analog converter;
D. controlled current source.
5. the according to claim 4 DC deviation bearing calibration of described a kind of wireless intermediate frequency receiver circuit system is characterized in that, the fixing aligning step of described intermediate frequency acceptor circuit DC deviation comprises:
A. chip power, system initialization is so register is established initial value 0; And with the positive-negative input end short circuit of low noise amplifier;
B. disconnect I passage and Q channel signal input end switch, regulate Iq1 compensating current element amplitude by sampling feedback circuit;
C. regulate the bit number that Iq1 compensating current element amplitude number of times depends on multidigit high precision digital-to-analog converter in the DC deviation sample circuit, until the DC deviation mean value of base-band digital part I passage and Q passage is reduced to simultaneously close to zero;
D. disconnect Q channel signal input end switch, connect I passage input end switch, regulate Ii2 compensating current element amplitude by sampling feedback circuit;
E. regulate the bit number that Ii2 compensating current element amplitude number of times depends on multidigit high precision digital-to-analog converter in the DC deviation sample circuit, until the DC deviation mean value of base-band digital part I passage and Q passage is reduced to simultaneously close to zero;
F. connect I passage and Q passage input end switch, regulate Iq2 compensating current element amplitude by sampling feedback circuit;
G. regulate Iq2 compensating current element amplitude number of times and depend on multidigit high precision digital-to-analog converter in the DC deviation sample circuit) bit number, until the DC deviation mean value of base-band digital part I passage and Q passage is reduced to simultaneously close to zero;
H. the positive-negative input end short circuit with low noise amplifier disconnects; Intermediate frequency acceptor circuit DC deviation trimming process finishes.
6. the according to claim 4 DC deviation bearing calibration of described a kind of wireless intermediate frequency receiver circuit system is characterized in that, described I passage and the digitlization of Q passage DC deviation mean value judge, when base band DC deviation mean value is output as 1 greater than zero the time; When base band DC deviation mean value is output as 0 less than zero the time.
7. the according to claim 4 DC deviation bearing calibration of described a kind of wireless intermediate frequency receiver circuit system is characterized in that, described successive approximation register algorithm logic and corresponding register generate the bit of control current source in the following order:
All bits all are made as zero when a. initial;
B. for the first time highest order is switched to 1 from zero, then register control digital to analog converter generates the input that corresponding offset current is delivered to complex bandpass filters, and next voltage comparator is exported according to complex bandpass filters and taken a sample, and generates comparative result; If comparator is output as 1, then highest order is left 1; Comparator is output as 0 else if, and then to be reset to be 0 to highest order;
C. the step that repeats b determines the bit value from the second highest order to lowest order successively, and after LSB finished, the value of register was exactly the last value of this compensating current element control bit; Preserve this bit value, when circuit works, use.
8. the according to claim 4 DC deviation bearing calibration of described a kind of wireless intermediate frequency receiver circuit system is characterized in that, the described digital to analog converter that mostly is generates corresponding control electric current according to the control bit position of register; 1111111111 just to generate the DC offset compensation electric current of amplitude peak such as the control bit position; And be 0000000000 just to generate the DC offset compensation electric current of minimum radius such as the control bit position.
9. the according to claim 4 DC deviation bearing calibration of described a kind of wireless intermediate frequency receiver circuit system, it is characterized in that, described controlled current source represents DAC according to the electric current that the control bit position of register generates, and directly is linked into the I passage of plural bandwidth filter or the input of Q passage.
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| CN108234369A (en) * | 2016-12-14 | 2018-06-29 | 奉加微电子（上海）有限公司 | A kind of method and device of cancellation of DC offset |
| CN109274618A (en) * | 2018-10-17 | 2019-01-25 | 珠海市杰理科技股份有限公司 | Radio-frequency transmitter DC offset calibration method, computer equipment and storage medium |
| CN109361417A (en) * | 2018-11-29 | 2019-02-19 | 中电科仪器仪表有限公司 | A kind of signal processing method and system for zero intermediate frequency receiver direct current offset |
| WO2022006862A1 (en) * | 2020-07-10 | 2022-01-13 | 深圳市速腾聚创科技有限公司 | Laser receiving circuit and laser radar |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108234369A (en) * | 2016-12-14 | 2018-06-29 | 奉加微电子（上海）有限公司 | A kind of method and device of cancellation of DC offset |
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| CN109274618B (en) * | 2018-10-17 | 2021-08-13 | 珠海市杰理科技股份有限公司 | Radio frequency receiver DC offset calibration method, computer device and storage medium |
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| WO2022006862A1 (en) * | 2020-07-10 | 2022-01-13 | 深圳市速腾聚创科技有限公司 | Laser receiving circuit and laser radar |
| CN114341667A (en) * | 2020-07-10 | 2022-04-12 | 深圳市速腾聚创科技有限公司 | Laser receiving circuit and laser radar |
| CN114341667B (en) * | 2020-07-10 | 2023-08-04 | 深圳市速腾聚创科技有限公司 | Laser receiving circuit and laser radar |
| US11835650B2 (en) | 2020-07-10 | 2023-12-05 | Suteng Innovation Technology Co., Ltd. | Laser receiving circuit and LiDAR wherein the reverse DC voltage signals from a DC bias circuit and the AC voltage signals from an amplifier circuit are superimposed |
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