CN103326735A - Direct current offset correcting method of wireless medium-frequency receiving circuit system - Google Patents

Direct current offset correcting method of wireless medium-frequency receiving circuit system Download PDF

Info

Publication number
CN103326735A
CN103326735A CN201310255477XA CN201310255477A CN103326735A CN 103326735 A CN103326735 A CN 103326735A CN 201310255477X A CN201310255477X A CN 201310255477XA CN 201310255477 A CN201310255477 A CN 201310255477A CN 103326735 A CN103326735 A CN 103326735A
Authority
CN
China
Prior art keywords
dc offset
channel
circuit
frequency
digital
Prior art date
Application number
CN201310255477XA
Other languages
Chinese (zh)
Other versions
CN103326735B (en
Inventor
杨俊杰
杨柳
Original Assignee
杨俊杰
杨柳
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 杨俊杰, 杨柳 filed Critical 杨俊杰
Priority to CN201310255477.XA priority Critical patent/CN103326735B/en
Publication of CN103326735A publication Critical patent/CN103326735A/en
Application granted granted Critical
Publication of CN103326735B publication Critical patent/CN103326735B/en

Links

Abstract

The invention discloses a direct current offset correcting method of a wireless medium-frequency receiving circuit system. In a medium-frequency receiving circuit, after wireless radio-frequency signals are received by an antenna, the wireless radio-frequency signals are amplified through a low-noise amplifier. Then frequency mixing is conducted by a frequency mixer and an oscillator so that medium-frequency signals with low frequency are generated. A direct current offset portion generated by the low-noise amplifier and the frequency mixer enters and an amplifier a complex band pass filter through a channel I and a channel Q and then enters an equal module of a complex band pass analog-digital converter, and digital signals are output to a base band. A whole correcting flow is stable and high in reliability. The direct current offset of all circuit modules to an output end on a medium-frequency circuit signal route until the base belt portion is reduced to a level approaching zero, so that the influence on the medium-frequency circuit by the direct current offset is eliminated and the dynamic range for the wireless system to receive the signals is improved.

Description

无线中频接收电路系统的直流偏差校正方法 Wireless IF receiver circuitry DC offset correction method

技术领域 FIELD

[0001] 本发明涉及电子工程中的半导体エ艺和电路设计技术,特别是射频(RF)电路中的中频(IF)接收电路系统,以及所包含的复数带通滤波器和放大器电路模块。 [0001] The present invention relates to semiconductor processes and circuit design techniques Ester electrical engineering, in particular radio frequency (RF) circuitry in an intermediate frequency (IF) receiver circuit system, and contains a plurality of bandpass filter and amplifier circuit modules.

背景技术 Background technique

[0002] 射频(RF)接收电路中通常包括天线(Antenna),低噪声放大器(LNA),混频器(Mixer),低通滤波器(LPF),信号放大器(VGA),模数转换器(ADC)等模块。 [0002] Radio Frequency (RF) receiver circuit typically includes an antenna (Antenna), a low noise amplifier (LNA), a mixer (Mixer), a low pass filter (LPF), a signal amplifier (VGA), analog to digital converter ( ADC) modules. 如果采取直接转换(Direct Conversion)的方式,在混频器阶段接收信号路径和振荡器(LO)时钟路径容易相互耦合泄露,这样造成自我混频而产生直流偏差。 If take the form of a direct conversion (Direct Conversion), the received signal path and an oscillator (LO) clock at the mixer stages coupled to each other easily leak path, so that self-mixing caused by the DC offset is generated. 为了避免这个问题,很多设计采用了中频(IF)电路的方式,即分成两个阶段来从RF信号中分离出原来信号。 To avoid this problem, many design uses an intermediate frequency (IF) circuit manner, i.e. in two stages to separate out the original signal from the RF signal. 第一阶段在混频器使用稍低于发射LO时钟的频率进行混频,这时就会使用复数带通滤波器(BPF)和放大器(VGA)来取代直接转换(Direct Conversion)电路中的低通滤波器(LPF)和放大器(VGA);第二阶段在基带用数字方式解码出原来的信号。 The first stage in the mixer LO frequency is slightly lower than the emission clock mixes, then it will use the complex bandpass filter (BPF) and amplifier (VGA) circuit instead of a direct conversion low (Direct Conversion) pass filter (LPF) and an amplifier (VGA); the second phase of the original signal decoded digitally at baseband. 这样中频IF电路的混频器造成的直流偏差大大降低,而直流偏差的主要来源不再是混频器模块的自我混频,而是其他因素,如差分电路不对称,エ艺偏差等,特别是电路的增益大的时候尤其明显。 Such an intermediate frequency mixer DC offset caused by IF circuit greatly reduced, and the main sources of DC offset is no longer self-mixing mixer module, but other factors such as the differential circuit asymmetry, deviation Ester arts, particularly the gain is large when the circuit is particularly evident.

[0003] 中频IF接收电路的直流偏差校正的难点在于:由于中频电路处理的是复数频率,所以I通道和Q通道电路有交互反馈作用。 [0003] The DC offset correction circuit receiving intermediate frequency IF difficulties that: due to the intermediate frequency circuit dealing with a complex frequency, the I and Q channels interact with a feedback circuit. 对于分离的I通道或Q通道,由于没有反馈回路的存在,直流偏差校正时只需采样输出直流偏置然后进行一次性电流补偿就可以将直流偏置降到很低的水平。 For the separation of the I-channel or Q channel, since there is no presence of the feedback loop, the sampled output DC bias only when the DC offset correction and one-time compensation for DC bias current can be reduced to very low levels. 但对于I通道和Q通道电路的交互反馈,即使I通道校正后,在校正Q通道的过程中可能会让I通道的直流偏置回到很差的水平。 However, for interactive feedback circuits I and Q channels, even if the I-channel correction in the correction process may make the Q channel DC offset I-channel level back poor. 而且即使对I通道和Q通道反复循环校正,输出端的直流偏置可能根本不收敛,难以降低到理想的水平。 And even if repeated cycles of correcting I and Q channels, the DC offset at the output might not converge, it is difficult to reduce to a desired level. 这在高増益的情形尤其明显,由于这时电路的灵敏度更大。 This is particularly evident in the case of a high enlargement of benefits, due to the greater sensitivity of the circuit at this time.

[0004]目前很多中频IF接收电路还是采用对复数带通滤波器(BPF)和放大器(VGA)的I通道和Q通道的反复循环校正,然后取得相对较小的直流偏差为止(SOmv-lOOmv),这样会使得中频带通滤波器(BPF)和放大器(VGA)的后一级模数转换器(ADC)很容易饱和,信号动态范围减小,从而降低系统的性能;而且这种方式由于不能确保直流偏差到最小值,所以在エ艺最差情形下会造成极大的直流偏差,所以也会造成芯片成品率(Yield)的下降。 [0004] At present, many intermediate frequency IF receiver circuit or the use of repeated cycles of the corrected complex bandpass filter (BPF) and amplifier (VGA) of the I and Q channels, then takes up a relatively small DC offset (SOmv-lOOmv) , this will make the band-pass filter (BPF) and amplifier (VGA) after an analog to digital converter (ADC) is easily saturated, the dynamic range of the signal is reduced, thereby reducing the performance of the system; and in this manner because it is not ensure that the DC bias to a minimum, so in the worst case Ester Arts will cause great DC offset, it will also cause a decline in chip yield (yield) of.

[0005] 虽然有些方式来解决I通道和Q通道造成的直流偏差互相干扰问题,如高通(Qualcomm)的2011年美国专利US2011/0037506A1,在I通道和Q通道耦合的路径中增添了开关控制来分离取样I通道和Q通道的直流偏置并进行校正,但这个方法有个假设,就是当I通道和Q通道的运放产生的直流偏置水平相同时,采用这种方式能将直流偏置降到极低水平。 [0005] Although some ways to solve the DC offset of I and Q channels due to interference with each other, such as a high-pass (Qualcomm) 2011 U.S. Patent US2011 / 0037506A1, in the path I and Q channels coupling the added switching control to isolated DC bias sampling I and Q channels and corrected, but this method has a hypothesis, that is, when the DC bias level amplifier I and Q channels generated by the same, in this way can the DC bias reduced to very low levels. 可是带通滤波器直流偏置的机理本事就是由于一些随机的因素,如エ艺造成的几何尺寸偏离,対称性不够等,所以虽然这种方式在大多数情形可以将直流偏置降低,但还是不是ー种可靠的方法。 But the mechanism of skill bandpass filter DC bias is due to some random factors, such as Ester Arts deviation caused by the geometry, says Dui not enough and so on, so although this approach can reduce the DC offset in most cases, but still not the kind ー reliable method. 当I通道和Q通道的直流偏置水平不同或甚至极性相反时,该方式校正的结果就不理想。 When different DC bias level of the I and Q channels to polar or even reversed, the mode correction result is not ideal. 发明内容 SUMMARY

[0006] 基于目前对于中频接收电路,包括复数带通滤波器和放大器的直流偏置电路存在的可靠性问题,本发明在严格理论分析的基础上,提出了一种无线中频接收电路系统的直流偏差校正方法,其特征在于,包括如下步骤: [0006] Based on the reliability of the current to the IF receiver circuit comprising a plurality of band-pass filter and an amplifier DC bias circuit of the present, the present invention is based on strict theoretical analysis, direct current is proposed for a wireless IF receiver circuitry bias correction method, comprising the steps of:

a.电路系统设计; . A circuit design;

b.基带数字化直流偏差取样平均模块; . B baseband digital samples of the DC offset averaging module;

c.直流偏差取样校正电路; . C sampling DC offset correction circuit;

d.中频接收器电路直流偏差固定的校正。 D. IF receiver circuit fixed DC offset correction.

[0007] 优选的,所述电路系统设计包括: [0007] Preferably, the circuit design system comprising:

a.在中频接收和复数带通滤波器系统设计时使用同样阻值的衰减反馈电阻R和耦合频移电阻RO ; . A complex intermediate frequency band-pass filter and the receiving system using the same resistance R, and feedback resistor coupled attenuation frequency shift resistor RO design;

b.直流偏差校正电流补偿点有三处:Ii2是在I通道输入电阻Ri之前接入,以消除来自于前一级混频器I通道输出的直流偏差;Iq2是在Q通道输入电阻Ri之前接入,以消除来自于前一级混频器I通道输出的直流偏差;Iql是在通道输入电阻Ri之后接入,以消除来自于Q通道运算放大器输入端的直流偏差; . B DC offset correction current compensation point has three: Ii2 is prior to the access I channel input resistance Ri to eliminate the DC offset from the I channel before a mixer output; and Iq2 Q channel is connected prior to the input resistance Ri in, in order to eliminate the DC offset from the I channel before a mixer output; Iql is the input resistance Ri after an access channel, to remove the DC offset from the Q-channel input terminal of the operational amplifier;

c.之所以I通道运算放大器输入端的直流偏差不需要补偿(没有电流源Iil)是因为在权利要求2a中使用同样阻值的衰减反馈电阻R和耦合频移电阻R0,所以在I通道运算放大器直流偏差在输出端产生的效应已经抵销为零。 c. The reason why the I-channel DC offset input of the operational amplifier need to compensate (no current source Iil) because the feedback resistor R is coupled to the same resistance value and attenuation 2a claims frequency shift resistor R0, so I Op Amp effect of DC offset generated at the output has zero offset.

[0008] 优选的,所述基带数字化直流偏差取样平均模块功能包括:连续对模数转换器的I通道和Q通道的数字输出取样,在多个样本的基础上进行平均,从而获得I通道和Q通道的直流偏差的平均值;该平均值为数字ニ补格式,当最高位为I时代表负值,而最高位为0时代表正值。 [0008] Preferably, the digitized baseband DC offset averaging module sampling function comprising: a continuous analog to digital converter samples the digital output of the I and Q channels, on the basis of averaging a plurality of samples on the I channel and to obtain Q channel DC deviation average; the average number of Ni complement format, representative of a negative value when the highest bit is I, the highest value is 0 representatives.

[0009] 优选的,所述直流偏差取样电路包括: [0009] Preferably, the DC offset of the sampling circuit comprises:

a.1通道和Q通道直流偏差平均值数字化判定; a.1 channel and Q channel digital DC offset mean value determination;

b.逐次逼近型寄存器算法逻辑和相应的寄存器; . B successive approximation register and arithmetic logic corresponding registers;

c.多位高精度数模转换器; . C Many precision DAC;

d.受控电流源。 D. controlled current source.

[0010] 优选的,所述中频接收器电路直流偏差固定的校正步骤包括: [0010] Preferably, the IF receiver circuit fixed DC offset correcting step comprises:

a.芯片上电,系统初始化,所以寄存器设初始值0 ;并将低噪声放大器的正负输入端短 . A chip power, system initialization, the register initial value is 0; short positive and negative inputs and a low noise amplifier

接; Access;

b.断开I通道和Q通道信号输入端开关,通过取样反馈电路调节Iql补偿电流源幅度; . B Disconnect the I channel and Q channel input signal switching, Iql adjusted by sampling the amplitude of the compensation current source feedback circuit;

c.调节Iql补偿电流源幅度次数取决于直流偏差取样电路内多位高精度数模转换器的比特数,直到基带数字部分I通道和Q通道的直流偏差平均值同时减小到接近于零; . C Iql adjusted compensating current source frequency and amplitude depending on the number of bits multi-bit DC offset circuit within the sampling precision DAC, until the DC portion baseband digital I and Q channels while reducing the average difference value close to zero;

d.断开Q通道信号输入端开关,接通I通道输入端开关,通过取样反馈电路调节Ii2补偿电流源幅度; . D OFF switch Q channel signal input, the I-channel input terminal of the switch is turned on, the amplitude adjustment Ii2 compensating current source by sampling the feedback circuit;

e.调节Ii2补偿电流源幅度次数取决于直流偏差取样电路内多位高精度数模转换器的比特数,直到基带数字部分I通道和Q通道的直流偏差平均值同时减小到接近于零; . E Ii2 adjustment frequency and amplitude of the compensation current source circuit depends on the number of bits in DAC precision than the DC offset sampling portion until the DC baseband digital I and Q channels while reducing the average difference value close to zero;

f.接通I通道和Q通道输入端开关,通过取样反馈电路调节Iq2补偿电流源幅度; . F I and Q channels switched input of the switch, Iq2 adjusted by sampling the amplitude of the compensation current source feedback circuit;

g.调节Iq2补偿电流源幅度次数取决于直流偏差取样电路内多位高精度数模转换器)的比特数,直到基带数字部分I通道和Q通道的直流偏差平均值同时减小到接近于零; g. adjusting the frequency and amplitude Iq2 compensating current source circuit depends on the number of bits of multi-bit precision digital to analog converter) the DC offset of the sampling, the average value of the DC offset until the baseband digital part I and Q channels at the same time reduced to close to zero ;

h.将低噪声放大器的正负输入端短接断开;中频接收器电路直流偏差校正过程结束。 . H The negative input of the low noise amplifier disconnect shorted; End IF receiver circuitry DC offset correction procedure.

[0011] 优选的,所述I通道和Q通道直流偏差平均值数字化判定,当基带直流偏差平均值大于零时输出为I;当基带直流偏差平均值小于零时输出为O。 [0011] Preferably, the I channel and Q channel digital average DC offset determination, when the average value of a baseband DC offset output I is greater than zero; when the base band output is less than zero average value of the DC offset is O.

[0012] 优选的,所述逐次逼近型寄存器算法逻辑和相应的寄存器,按如下顺序来生成控制电流源的比特位: [0012] Preferably, the successive approximation register and arithmetic logic corresponding registers in the following order bits to generate a control current source:

a.初始时所有比特位都设为零; . A all bits are initially set to zero;

b.第一次将最高位从零切換到1,然后寄存器控制数模转换器生成相应的补偿电流送到复数带通滤波器的输入端,接下来电压比较器根据复数带通滤波器输出进行取样,生成比较结果;如果比较器输出为1,则最高位保留为I ;否则如果比较器输出为0,则最高位重设为为0 ; b. The first most significant bit is switched from zero to 1, and digital to analog converter generating the control register corresponding compensation current to the input terminal of the complex band-pass filter, then the voltage comparator according to a complex band pass filter output sampling, generating a comparison result; if the output is 1, then the most significant bit is reserved I; otherwise, if the comparator output is 0, the most significant bit is reset to 0;

c.重复b的步骤依次决定从第二最高位到最低位的比特值,当LSB结束后,寄存器的值就是该补偿电流源控制比特的最后值;保存该比特值,在电路正常工作时使用。 . C Repeat steps b determined from the second highest order bit to the least significant bit value, when the end of the LSB, the value of the register is the last value of the compensation current source control bits; the bits stored value is used when the circuit is working properly .

[0013] 优选的,所述多为数模转换器,根据寄存器的控制比特位生成相应的控制电流;如控制比特位是1111111111就生成最大幅度的直流偏差补偿电流;而如控制比特位是0000000000就生成最小幅度的直流偏差补偿电流。 [0013] Preferably, the plurality of digital to analog converter to generate a corresponding control current according to a control register bits; control bit is the most significant 1111111111 generates DC offset compensation current; and a control bit 0000000000 DC offset compensation current is generated in the minimum magnitude.

优选的,所述受控电流源代表DAC根据寄存器的控制比特位所生成的电流,直接接入到复数带宽滤波器的I通道或Q通道的输入端。 Preferably, the current DAC representative of the controlled current source according to a control register bits generated, direct access to the complex to the input bandwidth of the filter to the I-channel or Q channel.

[0014] 对于复数带通滤波器和放大器中I通道和Q通道相互耦合的情形,I通道在滤波器输出端的直流偏差为: [0014] For the case of the complex band pass filter and amplifier I and Q channels are coupled to each other, the I-channel DC offset in the output of the filter is:

Figure CN103326735AD00061

其中AM,,和AAf5是I通道和Q通道复数带通滤波器和放大器前ー级模块产生的直流偏压,而AR和-¾则是复数带通滤波器和放大器本身在I通道和Q通道运放输入端产生的直流偏压。 AM ,, and wherein the DC bias is AAf5 I channel and Q channel complex bandpass filter and amplifier stage module before ー generated, and the AR is -¾ complex band-pass filter and the amplifier itself in the I and Q channels DC bias input of the operational amplifier is generated.

[0015] 同样,Q通道在滤波器输出端的直流偏压为: [0015] Similarly, Q-channel DC bias output of the filter is:

Figure CN103326735AD00062

基于上述分析,本发明设计釆取如下方式来减小和抵消中频电路所产生的直流偏差: Based on the above analysis, the present invention is designed to preclude taking a manner to reduce and cancel the DC offset generated by the intermediate frequency circuit:

a.设计R和RO取同样阻值来使得 a. R and RO designed to take the same resistance that

Figure CN103326735AD00063

项生成的直流偏差为零;这个条件易 Generating a DC offset term to zero; this condition easy to

于实现,因为复数带通滤波器和放大器电路增益由R/Ri决定,如果R固定为RO值,可以只改变Ri来达到可变增益的目的(VGA); To achieve, because the complex band-pass filter and the amplifier circuit gain is determined by the R / Ri, if RO is a fixed value R, Ri can be changed only to achieve the purpose of the variable gain (VGA);

b.増加I通道开关SWI,这样SWI开关断开时Ri相当于⑴,从而使得直流偏差项 b. to increase in I channel switch SWI, so that when the switch is turned off SWI Ri corresponds ⑴, so that the DC offset term

Figure CN103326735AD00064

为零; Zero;

c.増加Q通道开关SWQ,这样SWQ开关断开时Ri相当于⑴,从而使得直流偏差项为 c. SWQ switch to increase in the Q channel, so that when Ri of the equivalent of ⑴ SWQ switch is turned off, so that the DC offset term is

Figure CN103326735AD00071

零; zero;

基于上述分析,本发明设计采取如下步骤来实现降低输出端的直流偏压到接近于零的水平: Based on the above analysis, the present invention is designed to take the following steps to achieve a reduction in the output of the DC bias level to near zero:

a.在中频接收和复数带通滤波器系统设计时使用同样阻值的衰减反馈电阻R和耦合频移电阻RO ;这样使得在I通道和Q通道输出直流偏差中 . A feedback resistor R and resistance of the coupling attenuation same intermediate frequency band-pass filter and the plural receiving system design resistance of the RO frequency shift; so that the I and Q channels in the output DC offset

Figure CN103326735AD00072

项生成的直流偏差为零; Generating a DC offset term to zero;

b.断开I通道和Q通道信号输入端开关SWI和SWQ,使得直流偏差项 b. Disconnect I channel and Q channel input signal switches SWI and SWQ, so that the DC offset term

Figure CN103326735AD00073

with

Figure CN103326735AD00074

都为零;利用直流偏置取样反馈校正电路调节Iql电流源幅度来补偿偏置电流 They are zero; DC offset using a feedback correction circuit adjusts sampling Iql current source to compensate for the bias current magnitude

Figure CN103326735AD00075

而使得I通道和Q通道直流偏差同时减小到接近于零; Such that I and Q channels while reducing the DC offset close to zero;

c.断开Q通道信号输入端开关使得 c. Disconnect Q-channel signal input of the switch such that

Figure CN103326735AD00076

为零,接通I通道输入端开关,通过取样反 Zero, the I-channel input terminal of the switch is turned on, by sampling trans

馈电路调节Ii2电流源幅度来补偿偏置电流 Ii2 current source feedback circuit regulating the amplitude of the bias current to compensate

Figure CN103326735AD00077

而使得I通道和Q通道直流偏差同时减小到接近于零; Such that I and Q channels while reducing the DC offset close to zero;

d.接通I通道和Q通道输入端开关,通过取样反馈电路调节Iq2电流源幅度来补偿偏置电流 d. Turn the I channel and Q channel input of the switch, the current source Iq2 adjusted amplitude by sampling the feedback circuit to compensate for the bias current

Figure CN103326735AD00078

而使得I通道和q通道直流偏差同时减小到接近于零。 Such that q and I-channel DC offset channels simultaneously reduced to close to zero.

[0016] 基于上述分析,由于ΔM1,和ΔMg分别是I通道和Q通道在混频器输出所产生的直流偏差,所以本发明的校正方式包括了校正由低噪声放大器和混频器所产生的直流偏差。 [0016] Based on the above analysis, since AM1, and the DC offset are ΔMg I and Q channels at the mixer output generated, the correction of the present invention includes a correction generated by the low noise amplifier and mixer DC offset.

[0017] 基于上述分析,由于ΔV1和ΔVQ分别是复数带通滤波器和放大器本身在I通道和Q通道运放输入端产生的直流偏压,所以本发明的校正方式包括了校正由复数带通滤波器和放大器产生的直流偏差。 [0017] Based on the above analysis, since ΔV1 and ΔVQ are complex bandpass filter and an amplifier DC bias input of the discharge itself generated in the I and Q channels transport, the correction of the present invention comprises a plurality of bandpass correction DC offset generated by the amplifier and filter.

[0018] 基于上述分析,本发明在复数带通模数转换器(Complex Band-pass AE ADC)数字输出端采用基带数字化直流偏置取样平均,在多次取样(1000-2000次)的基础上计算出最后输出的I通道和Q通道的直流偏差的平均值,并通过直流偏差反馈校正电路。 [0018] Based on the above analysis, the present invention is a complex bandpass analog to digital converter (Complex Band-pass AE ADC) using the digital output of digital baseband sample average DC offset, multiple sampling base (1000-2000 Ci) on the calculates an average value of the final output current I channel and Q channel of the deviation, and the feedback correction by the DC offset circuit. 所以本发明校正的结果是使得整个中频电路的输出直流偏差降低到接近于零的水平,也包括了由复数带通模数转换器(Complex Band-pass AE ADC)产生的直流偏差。 Therefore, the present invention is such that the overall result is a correction of the intermediate frequency circuit to reduce the DC offset output level close to zero, also comprising a DC offset generated by a complex band pass digital converter (Complex Band-pass AE ADC).

[0019] 虽未明确提及,本发明电流源补偿方式可以为单端或差分补偿。 [0019] Although not explicitly mentioned, compensation current source of the present invention may be a single-ended or differential compensation. 在差分补偿时通道的正极输入端和负极输入端都有补偿电流源,其幅值相等但极性相反。 When a difference in the compensation of the positive electrode and the negative input terminal of the input channels are compensated current source, equal in magnitude but opposite in polarity.

[0020] 本发明对无线中频接收电路系统的直流偏差校正的精度取小于数模转换器(DAC)的最低位(LSB)所代表的直流偏差水平。 [0020] The wireless IF receiver DC offset correction circuitry of the present invention takes less than a precision level of DC offset digital to analog converter (DAC) of the least significant bit (LSB) represents. 所以D AC的精度越高,最终直流偏差校正的精度也就越高。 Therefore, the higher the accuracy of D AC, the higher the accuracy of the final DC offset correction.

附图说明 BRIEF DESCRIPTION

[0021] 图1是中频IF接收电路的组成电路模块和信号路径; [0021] FIG. 1 is a circuit block composition, and an intermediate frequency IF signal path of a receiving circuit;

图2是复数带通滤波器的电路结构和直流偏置校正电流源的接入方式; 图3是直流偏差取样校正电路的内部模块图; FIG 2 is a circuit configuration of a plurality of access mode band-pass filter and the DC-offset correction current source; FIG. 3 is an internal block diagram showing the DC offset correction circuit of sampling;

图4是中频接收电路系统直流偏差的校正步骤; FIG 4 is a system IF receiver circuit DC deviation correction step;

图5是直流偏差校正流程的输出波形。 FIG 5 is a flow of the DC offset corrected output waveform.

[0022] 如下具体实施方式将结合附图进行说明。 [0022] The following detailed description will be described in conjunction with the accompanying drawings.

具体实施方式 Detailed ways

[0023] 本发明直流偏差校正方式所适用的中频无线接收系统如图1所示。 [0023] The DC offset correction of the present invention applies an intermediate frequency radio receiver system shown in Figure 1. RF信号由天线(101)进入,经过低噪声放大器(LNA,102)后分两路I通道和Q通道送入混频器(Mixer,103和104),然后经过复数带通滤波器和放大器(Complex BPF和VGA,105),经过复数带通模数转换器(Complex Band-pass AE ADC, 107)后变成基带信号。 Incoming RF signal by an antenna (101) through a low noise amplifier (LNA, 102) after the two routes I and Q channels into a mixer (Mixer, 103 and 104), then through a complex bandpass filter and amplifier ( complex BPF and VGA, 105), through complex bandpass analog to digital converter (complex band-pass AE ADC, after 107) into a baseband signal. 基带数字化直流偏置取样平均模块在多次取样(1000-2000次)的基础上计算出最后输出的I通道和Q通道的直流偏差的平均值,并通过直流偏差反馈校正电路,分三次然后生成控制电流源的输出进入复数带通滤波器和放大器的输入端。 Calculated average DC offset output from the I channel and Q channel final basis baseband digital samples of the average DC offset in the multiple sampling module (1000-2000 Ci) on, and a feedback circuit by the DC offset correction, and then generates three times controls the current source output into the input of the complex band-pass filters and amplifiers. 由于复数带通滤波器和放大器位于中间,所以它的直流偏置也受到前面混频器和低噪声放大器的影响。 Because of the complex band pass filter and an amplifier in the middle, it is also affected by the DC bias in front of the mixer and the low noise amplifier.

[0024] 图2是复数带通滤波器的电路结构和直流偏置校正电流源的接入方式。 [0024] FIG. 2 is a circuit configuration with a complex and DC offset correction current source access pass filter. 电路系统设计部分包括: The circuit design portion comprises:

a.在中频接收和滤波器系统设计时使用同样阻值的衰减反馈电阻R和耦合频移电阻 Feedback resistor R and a coupling attenuation a. Using the same resistance value, and a filter in the IF receiver system design frequency shift resistor

RO ; RO;

b.直流偏差校正电流补偿点有三处:Ii2是在I通道输入电阻Ri之前接入,以消除来自于前一级混频器I通道输出的直流偏差;Iq2是在Q通道输入电阻Ri之前接入,以消除来自于前一级混频器I通道输出的直流偏差;Iql是在通道输入电阻Ri之后接入,以消除来自于Q通道运算放大器输入端的直流偏差; . B DC offset correction current compensation point has three: Ii2 is prior to the access I channel input resistance Ri to eliminate the DC offset from the I channel before a mixer output; and Iq2 Q channel is connected prior to the input resistance Ri in, in order to eliminate the DC offset from the I channel before a mixer output; Iql is the input resistance Ri after an access channel, to remove the DC offset from the Q-channel input terminal of the operational amplifier;

c.之所以I通道运算放大器输入端的直流偏差不需要补偿(没有电流源Iil)是因为在权利要求2a中使用同样阻值的衰减反馈电阻R和耦合频移电阻R0,所以在I通道运算放大器直流偏差在输出端产生的效应已经抵销为零。 c. The reason why the I-channel DC offset input of the operational amplifier need to compensate (no current source Iil) because the feedback resistor R is coupled to the same resistance value and attenuation 2a claims frequency shift resistor R0, so I Op Amp effect of DC offset generated at the output has zero offset.

[0025] 在图3中直流偏差校正电路的模块包括: [0025] In the DC offset correction circuit 3, a block diagram comprising:

a.1通道和Q通道直流偏差平均值数字化判定 a.1 channel and Q channel digital DC offset determines the average

b.逐次逼近型寄存器算法逻辑和相应的寄存器(SAR) b. successive approximation register and arithmetic logic corresponding register (SAR)

c.多位高精度数模转换器(DAC) c. Many precision digital to analog converter (DAC)

d.受控电流源 d. controlled current source

中频接收滤波器电路直流偏差固定的校正步骤如图4所示,包括: IF filter circuit receiving the DC offset correcting step of fixing shown in Figure 4, comprising:

a.芯片上电,系统初始化,所以寄存器设初始值0 ;将低噪声放大器(LNA)的正负输入端短接; . A chip power, system initialization, the register initial value is 0; low-noise amplifier (LNA) of the positive and negative inputs shorted;

b.断开I通道和Q通道信号输入端开关,通过取样反馈电路调节Iql补偿电流源幅度; . B Disconnect the I channel and Q channel input signal switching, Iql adjusted by sampling the amplitude of the compensation current source feedback circuit;

c.调节Iql补偿电流源幅度次数取决于直流偏差取样电路内多位高精度数模转换器(DAC)的比特数,直到基带数字部分I通道和Q通道的直流偏差平均值同时减小到接近于零; c. Iql adjustment frequency and amplitude compensating current source circuit depends on the number of bits of multi-bit precision digital to analog converter (DAC) of the DC offset sampling portion until the DC baseband digital I and Q channels at the same time the average deviation reduced to near to zero;

d.断开Q通道信号输入端开关,接通I通道输入端开关,通过取样反馈电路调节Ii2补偿电流源幅度; e.调节Ii2补偿电流源幅度次数取决于直流偏差取样电路内多位高精度数模转换器(DAC)的比特数,直到基带数字部分I通道和Q通道的直流偏差平均值同时减小到接近于零; . D OFF switch Q channel signal input, the I-channel input terminal of the switch is turned on, the amplitude adjustment Ii2 compensating current source by sampling the feedback circuit; E Ii2 adjusted compensating current source depends on the frequency and amplitude of the DC offset with high accuracy than the sampling circuit. number of bits of digital to analog converter (DAC) until the DC baseband digital part of the I and Q channels while reducing the average difference value close to zero;

f.接通I通道和Q通道输入端开关,通过取样反馈电路调节Iq2补偿电流源幅度; . F I and Q channels switched input of the switch, Iq2 adjusted by sampling the amplitude of the compensation current source feedback circuit;

g.调节Iq2补偿电流源幅度次数取决于直流偏差取样电路内多位高精度数模转换器(DAC)的比特数,直到基带数字部分I通道和Q通道的直流偏差平均值同时减小到接近于零; g. adjusting the frequency and amplitude Iq2 compensating current source circuit depends on the number of bits of multi-bit precision digital to analog converter (DAC) of the DC offset sampling portion until the DC baseband digital I and Q channels at the same time the average deviation reduced to near to zero;

h.将低噪声放大器(LNA)的正负输入端短接断开;中频接收滤波器电路直流偏差校正过程结束。 . H The negative input of the low noise amplifier (LNA) shorting disconnected; end of the receiving filter circuit IF DC offset correction procedure.

[0026] 图5是连续三次校正过程中直流偏差的波形图。 [0026] FIG. 5 is a waveform diagram during three consecutive correction of DC offset. 每一次校正I和Q通道的直流偏差都同时减小到几乎为零。 Each I and Q channels of correcting the DC offset are simultaneously reduced to almost zero. 但当开关切换吋,I通道和Q通道的直流偏差又变差,所以下一次校正又将直流偏差减小到几乎为零。 But switching inch, the DC offset of the I and Q channels and deteriorated, so the next time the DC offset correction in turn is reduced to almost zero. 最后当所有开关开通时,校正流程将直流偏置减小到几乎为零时,这时开关的状态也是电路正常工作的状态,所以正常工作时,经过校正后的电路的直流偏差也几乎为零。 Finally, when all of the switches open, the DC offset correction process is reduced to almost zero, the state is the state at this time the switch circuit is operating normally, the normal operation after the DC offset correction circuit is almost zero after .

[0027] 本发明电流源补偿方式可以为单端或差分补偿。 [0027] The present invention compensation current source may be a single-ended or differential compensation. 在差分补偿时通道的正极输入端和负极输入端都有补偿电流源,其幅值相等但极性相反。 When a difference in the compensation of the positive electrode and the negative input terminal of the input channels are compensated current source, equal in magnitude but opposite in polarity.

[0028] 以上所示为本发明的具体实施方式,但本发明的保护范围并不局限于此。 DETAILED embodiment of the present invention shown in Embodiment [0028] above, but the scope of the present invention is not limited thereto. 任何熟悉本技术领域的专业技术人员在本发明公开的技术范围内,所轻易想到的变化或替换,都应涵盖在本发明的保护范围之内。 Any professional skilled in the art in the art within the technical scope of the present disclosure, variations or replacements easily conceivable, shall fall within the protection scope of the present invention.

Claims (9)

1.一种无线中频接收电路系统的直流偏差校正方法,其特征在于,包括如下步骤: a.电路系统设计; b.基带数字化直流偏差取样平均模块; c.直流偏差取样校正电路; d.中频接收器电路直流偏差固定的校正。 DC offset correction method of wireless IF receiver circuitry, characterized by comprising the steps of:.... A system circuit design; B baseband digital DC offset sampling averaging module; C DC offset sampling correction circuit; D IF the receiver circuit fixed DC offset correction.
2.根据权利要求1所述ー种无线中频接收电路系统的直流偏差校正方法,其特征在于,所述电路系统设计包括: a.在中频接收和复数带通滤波器系统设计时使用同样阻值的衰减反馈电阻R和耦合频移电阻RO ; b.直流偏差校正电流补偿点有三处:Ii2是在I通道输入电阻Ri之前接入,以消除来自于前一级混频器I通道输出的直流偏差;Iq2是在Q通道输入电阻Ri之前接入,以消除来自于前一级混频器I通道输出的直流偏差;Iql是在通道输入电阻Ri之后接入,以消除来自于Q通道运算放大器输入端的直流偏差; c.之所以I通道运算放大器输入端的直流偏差不需要补偿(没有电流源Iil)是因为在权利要求2a中使用同样阻值的衰减反馈电阻R和耦合频移电阻R0,所以在I通道运算放大器直流偏差在输出端产生的效应已经抵销为零。 The DC offset correction method ー species wireless IF receiver circuitry of claim 1, wherein said circuit designing system comprising:. A resistance using the same intermediate frequency band-pass filter and the plural receiving system design the feedback resistor R and the coupling attenuation frequency shift resistor RO; b DC offset correction current compensation point has three:. Ii2 is prior to the input resistance Ri I channel access, to remove from the mixer before an I channel DC deviation; and Iq2 is prior to the input resistance Ri Q channel access, in order to eliminate the DC offset from the I channel before a mixer output; Iql is an access channel after the input resistance Ri to remove from the operational amplifier Q channel input DC offset;. c I-channel DC reason for the op amp inputs of the need to compensate the deviation (no current source Iil) because the feedback resistor R is coupled to the same resistance value and attenuation 2a claims frequency shift resistor R0, so has zero offset I-channel DC offset of the operational amplifier at the output of the effect produced.
3.根据权利要求2所述ー种无线中频接收电路系统的直流偏差校正方法,其特征在于,所述基带数字化直流偏差取样平均模块功能包括:连续对模数转换器的I通道和Q通道的数字输出取样,在多个样本的基础上进行平均,从而获得I通道和Q通道的直流偏差的平均值;该平均值为数字ニ补格式,当最高位为I时代表负值,而最高位为0时代表正值。 The DC offset correction method ー species wireless IF receiver circuitry of claim 2, wherein said digital baseband DC offset averaging module sampling function comprising: analog to digital converter for successive I-channel and Q-channel digital output samples, performed on the basis of a plurality of samples averaged to obtain an average value of the DC offset of the I and Q channels; the average number of Ni complement format, representative of a negative value when the highest bit is I, the highest when the representative value is 0.
4.根据权利要求2所述ー种无线中频接收电路系统的直流偏差校正方法,其特征在于,所述直流偏差取样电路包括: a.1通道和Q通道直流偏差平均值数字化判定; b.逐次逼近型寄存器算法逻辑和相应的寄存器; c.多位高精度数模转换器; d.受控电流源。 The DC offset correction method ー species wireless IF receiver circuitry of claim 2, wherein said DC offset circuit includes a sampling: a.1 channel and Q channel digital DC offset determines the average value; B sequentially. approximation register and arithmetic logic corresponding registers; C multiple precision digital to analog converter;.. D controlled current source.
5.根据权利要求4所述ー种无线中频接收电路系统的直流偏差校正方法,其特征在于,所述中频接收器电路直流偏差固定的校正步骤包括: a.芯片上电,系统初始化,所以寄存器设初始值0 ;并将低噪声放大器的正负输入端短接; b.断开I通道和Q通道信号输入端开关,通过取样反馈电路调节Iql补偿电流源幅度; c.调节Iql补偿电流源幅度次数取决于直流偏差取样电路内多位高精度数模转换器的比特数,直到基带数字部分I通道和Q通道的直流偏差平均值同时减小到接近于零; d.断开Q通道信号输入端开关,接通I通道输入端开关,通过取样反馈电路调节Ii2补偿电流源幅度; e.调节Ii2补偿电流源幅度次数取决于直流偏差取样电路内多位高精度数模转换器的比特数,直到基带数字部分I通道和Q通道的直流偏差平均值同时减小到接近于零; f.接通I通道和Q通道输入端开关 The DC offset correction method ー species wireless IF receiver circuitry of claim 4, wherein said intermediate frequency receiver circuit fixed DC offset correction step comprises:. A power, on-chip system initialization, the register initial value is 0; and the positive and negative inputs shorted low noise amplifier;. I-channel and B-channel disconnection signal input terminal Q switch, Iql adjusted by sampling the amplitude of the compensation current source feedback circuit; C Iql adjusted compensation current source. frequency and amplitude depending on the number of bits in DAC precision circuit than the DC offset sampling portion until the DC baseband digital I and Q channels while reducing the average difference value close to zero;. d OFF Q-channel signal input of the switch, the switch is turned on the I-channel input terminal, Ii2 adjusted by sampling the amplitude of the compensation current source feedback circuit;. e Ii2 adjusted compensating current source frequency and amplitude depend on the DC offset sampling circuit than the number of bits of precision DAC until the DC portion baseband digital I and Q channels while reducing the average difference value close to zero;. f I and Q channels switched input of the switch 通过取样反馈电路调节Iq2补偿电流源幅度; g.调节Iq2补偿电流源幅度次数取决于直流偏差取样电路内多位高精度数模转换器)的比特数,直到基带数字部分I通道和Q通道的直流偏差平均值同时减小到接近于零; h.将低噪声放大器的正负输入端短接断开;中频接收器电路直流偏差校正过程结束。 By sampling the feedback circuit adjusts the amplitude Iq2 compensation current source;. G Iq2 adjusted compensating current source depends on the frequency and amplitude of the DC offset sampling number of bits than the digital-analog converter circuit precision) until the baseband digital I and Q channels part of while reducing the average DC offset close to zero; H positive and negative input of the low noise amplifier turned off short; the end-IF receiver circuitry DC offset correction procedure.
6.根据权利要求4所述ー种无线中频接收电路系统的直流偏差校正方法,其特征在于,所述I通道和Q通道直流偏差平均值数字化判定,当基带直流偏差平均值大于零时输出为I ;当基带直流偏差平均值小于零时输出为O。 The DC offset correction method ー species wireless IF receiver circuitry of claim 4, wherein said I channel and Q channel digital DC offset mean value determination, when the average value of a baseband DC offset output is greater than zero I; baseband DC offset when the average is less than zero output is O.
7.根据权利要求4所述ー种无线中频接收电路系统的直流偏差校正方法,其特征在于,所述逐次逼近型寄存器算法逻辑和相应的寄存器,按如下顺序来生成控制电流源的比特位: a.初始时所有比特位都设为零; b.第一次将最高位从零切換到1,然后寄存器控制数模转换器生成相应的补偿电流送到复数带通滤波器的输入端,接下来电压比较器根据复数带通滤波器输出进行取样,生成比较结果;如果比较器输出为1,则最高位保留为I ;否则如果比较器输出为O,则最高位重设为为O ; c.重复b的步骤依次决定从第二最高位到最低位的比特值,当LSB结束后,寄存器的值就是该补偿电流源控制比特的最后值;保存该比特值,在电路正常工作时使用。 The DC offset correction method ー species wireless IF receiver circuitry of claim 4, wherein said successive approximation logic registers and arithmetic registers corresponding, in the following order bits to generate a control current source: . a all bits are initially set to zero; B first most significant bit is switched from zero to 1, and digital to analog converter generating the control register corresponding compensation current to the input of the complex band pass filter, connected. down voltage comparator according to a complex band pass filter output samples to generate a comparison result; if the output is 1, then the most significant bit is reserved I; else if the comparator output is O, the most significant bit is reset to O; c step b is repeated sequentially determined from the second highest bit to the least significant bit value, when the end of the LSB, the value of the register is the last value of the compensation current source control bits; the stored bit value used when the circuit is working properly.
8.根据权利要求4所述ー种无线中频接收电路系统的直流偏差校正方法,其特征在于,所述多为数模转换器,根据寄存器的控制比特位生成相应的控制电流;如控制比特位是1111111111就生成最大幅度的直流偏差补偿电流;而如控制比特位是0000000000就生成最小幅度的直流偏差补偿电流。 8. The method of correcting the DC offset ー species wireless IF receiver circuitry according to the claim 4, wherein said plurality of digital to analog converter to generate a corresponding control current according to a control register bits; control bits 1111111111 generates a maximum amplitude of the DC offset compensating current; control bits and generates the DC offset is compensated 0000000000 minimum current magnitude.
9.根据权利要求4所述ー种无线中频接收电路系统的直流偏差校正方法,其特征在于,所述受控电流源代表DAC根据寄存器的控制比特位所生成的电流,直接接入到复数带宽滤波器的I通道或Q通道的输入端。 9. The DC offset correction method of radio types ー the IF receiver circuitry according to claim 4, wherein said controlled current source according to the representative DAC control register bits generated, a plurality of direct access to the bandwidth input of the filter of the I-channel or Q channel.
CN201310255477.XA 2013-06-25 2013-06-25 DC offset correction method for a wireless IF receiver circuitry CN103326735B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310255477.XA CN103326735B (en) 2013-06-25 2013-06-25 DC offset correction method for a wireless IF receiver circuitry

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310255477.XA CN103326735B (en) 2013-06-25 2013-06-25 DC offset correction method for a wireless IF receiver circuitry

Publications (2)

Publication Number Publication Date
CN103326735A true CN103326735A (en) 2013-09-25
CN103326735B CN103326735B (en) 2017-03-15

Family

ID=49195298

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310255477.XA CN103326735B (en) 2013-06-25 2013-06-25 DC offset correction method for a wireless IF receiver circuitry

Country Status (1)

Country Link
CN (1) CN103326735B (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5422889A (en) * 1992-10-28 1995-06-06 Alcatel N.V. Offset correction circuit
CN1397108A (en) * 2000-11-23 2003-02-12 皇家菲利浦电子有限公司 DC-offset correction circuit having DC control loop and DC blocking circuit
CN1536770A (en) * 2003-05-15 2004-10-13 威盛电子股份有限公司 Direct conversion receiver with DC offset compensation function and its compensation method
US20110037506A1 (en) * 2009-08-11 2011-02-17 Qualcomm Incorporated Dc offset calibration for complex filters
CN102377707A (en) * 2010-08-11 2012-03-14 齐凌微电子科技(上海)有限公司 Direct current offset elimination method for zero intermediate frequency receiver

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5422889A (en) * 1992-10-28 1995-06-06 Alcatel N.V. Offset correction circuit
CN1397108A (en) * 2000-11-23 2003-02-12 皇家菲利浦电子有限公司 DC-offset correction circuit having DC control loop and DC blocking circuit
CN1536770A (en) * 2003-05-15 2004-10-13 威盛电子股份有限公司 Direct conversion receiver with DC offset compensation function and its compensation method
US20110037506A1 (en) * 2009-08-11 2011-02-17 Qualcomm Incorporated Dc offset calibration for complex filters
CN102377707A (en) * 2010-08-11 2012-03-14 齐凌微电子科技(上海)有限公司 Direct current offset elimination method for zero intermediate frequency receiver

Also Published As

Publication number Publication date
CN103326735B (en) 2017-03-15

Similar Documents

Publication Publication Date Title
US7002501B2 (en) Analog-to-digital converter having parametric configurablity
US6670901B2 (en) Dynamic range on demand receiver and method of varying same
US7420410B2 (en) Variable gain amplifier circuit, method of correcting DC offset of the variable gain amplifying circuit, and radio receiving apparatus
US6756924B2 (en) Circuit and method for DC offset calibration and signal processing apparatus using the same
US6560447B2 (en) DC offset correction scheme for wireless receivers
US8249535B2 (en) Radio receivers
Eloranta et al. A Multimode Transmitter in 0.13$\mu\hbox {m} $ CMOS Using Direct-Digital RF Modulator
EP1878184B1 (en) Power control system for a continuous time mobile transmitter
US6459889B1 (en) DC offset correction loop for radio receiver
EP1638204A1 (en) Power amplifier and transmitter
US6734817B2 (en) A/D converter, method of A/D conversion, and signal processing device
JP4264623B2 (en) Gain control amplifier, the receiving circuit and the wireless communication device
US7539462B2 (en) Configurable multi-mode modulation system and transmitter
US20040081256A1 (en) DC offset correcting in a direct conversion or very low if receiver
US7233206B2 (en) Semiconductor integrated circuit device and wireless communication system
US20030045243A1 (en) Method and arrangement for linearizing a radio receiver
US7933569B2 (en) Timing adjustment method for wireless communication apparatus
EP1428314B1 (en) Ping-pong amplifier with auto-zeroing and chopping
US20020113726A1 (en) Overcoming finite amplifier gain in a pipelined analog to digital converter
US8086208B2 (en) Passive wireless receiver
EP1055284A1 (en) Circuit comprising means for reducing the dc-offset and the noise produced by an amplifier
US6868128B1 (en) Method and apparatus for calibrating DC-offsets in a direct conversion receiver
US6757340B1 (en) Radio receiver and method for preloading an average DC-offset into a channel filter
US7376400B2 (en) System and method for digital radio receiver
US8519878B2 (en) Multi-mode analog-to-digital converter

Legal Events

Date Code Title Description
C06 Publication
C10 Entry into substantive examination
C14 Grant of patent or utility model