CN101213737A - Analog to digital converter with ping-pong architecture - Google Patents
Analog to digital converter with ping-pong architecture Download PDFInfo
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Abstract
The invention provides a receiver for use in a wireless communication system that substantially reduces mismatch between an in-phase (I) component and a quadrature (Q) component of a received signal. The receiver achieves this by sharing or ''ping-ponging'' an analog-to-digital converter (ADC) between the I and Q components. By sharing a single pipelined ADC between the I and Q components, both the I and Q components are processed by the same circuitry inside the pipelined ADC thereby eliminating many dominant sources of I-Q mismatch. The pipelined ADC operates at approximately twice the speed as other circuit components. Consequently, I-Q mismatch, which negatively affects performance, may be substantially reduced. At the same time, system complexity, cost, and power dissipation are reduced by eliminating an additional ADC typically used to process the I and Q components in parallel signal paths.
Description
Technical field
The present invention relates to be used for the analog to digital converter (ADC) of wireless communication system.
Background technology
Modern radio-frequency (RF) communication system adopts advanced signal modulation techniques with digital baseband signal carrier frequency to be modulated.These modulation techniques comprise for example phase shift keying modulation (PSK), binary phase shift keying modulation (BPSK), Quadrature Phase Shift Keying modulation (QPSK), frequency shift keying modulation (FSK) and Minimum Shift Keying Modulation (MSK).Digital modulation technique is compared with the analog-modulated technology, can improve systematic function, reduces cost, improves reliability, increase capacity and strengthen fail safe.Yet these improvement are cost to increase system complexity, particularly the complexity of radio frequency transceiver design.
Use digital modulation technique emission data demand at numeric field received data to be carried out demodulation subsequently.Like this, exist manyly during, can use ripe Digital Signal Processing (DSP) technology to improve Data Receiving as actual non-ideality such as multipath interference, intersymbol interference, decline.
For Data Receiving, antenna receives the RF signal that arrives, and it is amplified, converts to lower frequency, carries out filtering, is transformed into data field from analog domain then, with further processing and final demodulation.When frequency inverted became base band frequency, RX path was divided into two parallel paths.This step realizes by quadrature frequency conversion usually, the in-phase component (being commonly referred to the I channel) and the quadrature component (being commonly referred to the Q channel) of the data that obtain arriving.Subsequently, with two parallel coupling good signal paths I channel and Q channel are handled simultaneously.By with two parallel coupling good signal path processing signals, two channels when numeric field makes up once more, are not wished in frequency inverted or the down-conversion mixing that the content that occurs can be cancelled.Yet the effect of this counteracting measure is subjected to gain and phase mismatch (the being also referred to as the I-Q mismatch) quantitative limitation of two parallel signal path I and Q essentially.
Depend on the structure (for example heterodyne receiver, homodyne radio receiver or image signal cancellation receiver) of receiver, the I-Q mismatch can greatly influence systematic function.Permissible I-Q mismatch is different with receiver structure.Usually, image signal elimination system and homodyne system are more responsive than heterodyne system.In any case, the I-Q mismatch makes that all when numeric field reconfigured channel, image frequency can not be offset fully.The incomplete counteracting of image frequency has reduced the signal to noise ratio (snr) of desired frequency band, thereby causes the suboptimum receptivity.
The source of mismatch has multiple between channel I and the Q.For example, the gain of local oscillator and phase mismatch have been contributed mismatch term.In addition, the level of each in two signal paths all has contribution to overall mismatch.Some mismatch sources are static, and other mismatch sources then can change in time, thereby feasible tracking and compensation mismatch are more difficult.For example, may be difficult to especially compensate the mismatch that is caused by ADC, wherein reference voltage mismatch changes with working temperature.
Summary of the invention
Usually, the present invention is intended to propose the receiver that uses in a kind of wireless communication system.Receiver greatly reduces or has eliminated homophase (I) component of received signal and the mismatch between quadrature (Q) component.This realizes by share (or claiming back and forth conversion (ping-ponging)) analog to digital converter (ADC) between Simulation with I component and Q component.By between I component and Q component, sharing pipeline-type (pipelined) ADC,, thereby eliminated many significant I-Q mismatches source by same processing of circuit I component and the Q component among the pipelined ad C.Like this, can reduce greatly performance is produced dysgenic I component and Q component mismatch.Simultaneously, system complexity and cost are also reduced, because receiver is not to use ADC separately to handle I component and Q component, and are to use an ADC to handle I component and Q component.
For example, receiver comprises data converter, and the signal from analog territory that is used for receiving is transformed into numeric field, to carry out Digital Signal Processing and demodulation.Data converter comprises: first and second samplings and maintenance (S/H) circuit, and these two circuit are distinguished sampled I and Q component simultaneously; Handle the common flow pipeline type ADC of I component and Q component; And multiplexer, be used for one of output of S/H circuit being offered public ADC at given time.The reciprocal conversion of public ADC between I component and Q component realizes by the operation of multiplexer.Because receiver uses an ADC to handle I component and Q component, the operating rate of public ADC approximately is the twice of S/H circuit and multiplexer operating rate.Yet, greatly reduced the I-Q mismatch, because I component and Q component handle with the same circuit among the common flow pipeline type ADC, so can save about 50% area.In order further to reduce mismatch, the S/H circuit can be placed adjacent one another on circuit block.Can also connect up by simplifier clock,, do not need to control two clock skews between the independent ADC because clock path only needs local coupling.Like this, the present invention has improved systematic function, has reduced system complexity, cost, power consumption and die area simultaneously.
The present invention can also expand to four road ping-pong architectures and the ping-pong architecture of high-order more, for example 8 the tunnel back and forth changes, 12 tunnel back and forth conversions etc.Among some embodiment, can before ping-pong architecture, comprise handover network, to eliminate the mismatch effects of bringing owing to the mismatch of S/H circuit.For four road ping-pong architectures, which input signal handover network can be sampled to by the S/H circuit by turns.Handover network can be rotated input signal according to the STOCHASTIC CONTROL order.Like this, the output demodulation multiplexer is used same random sequence, to separate single signal flow.
In other embodiments, can calculate the highest significant position (MSB) of received signal with parallel signal path, and can calculate least significant bit (LSB) by being multiplexed into a streamline.In this case, first and second ADC that Simulation with I and Q component can be fed respectively calculate MSB simultaneously.The output of first and second ADC can be multiplexed into the common ADC that calculates LSB.Like this, can realize multiplexer in company with pipelined ad C according to the requirement of receiver.
Although describe the present invention with reference to wireless receiver in the disclosure, the present invention can be used for the good sampling ADC of needs coupling usually and uses with any receiver of digitlization parallel data path.Can make up the restriction of the clock frequency of the pipelined ad C that the channel quantity of (promptly multiplexing) only shared.
Among the embodiment, the present invention proposes a kind of method, comprising: received signal, this conversion of signals is become analog in-phase (I) component and simulation quadrature (Q) component, Simulation with I component and Q component are applied to common analog to digital converter (ADC).
Among another embodiment, the present invention proposes a kind of communicator, comprising: receiver is used for received signal; Low-converter, it becomes analog in-phase (I) component and simulation quadrature (Q) component with this conversion of signals; And common analog to digital converter (ADC), it converts the Simulation with I component digital I component to and will simulate Q component and converts digital Q component to.
Among another embodiment, the present invention proposes a kind of method, comprising: receive first signal; Receive secondary signal; First conversion of signals is become first analog in-phase (I) component and first simulation quadrature (Q) component; Convert secondary signal to second analog in-phase (I) component and second simulation quadrature (Q) component; First Simulation with I and Q component and second Simulation with I and Q component are applied to common analog to digital converter (ADC).
Among another embodiment, the present invention proposes a kind of equipment: comprising: the receiver that receives first signal and secondary signal; Low-converter, it becomes first analog in-phase (I) component and second simulation quadrature (Q) component with first conversion of signals, and converts secondary signal to second analog in-phase (I) component and second simulation quadrature (Q) component; And common analog to digital converter (ADC), it converts the first and second Simulation with I components to corresponding first and second digital I components, and converts the first and second simulation Q components to corresponding first and second digital Q components.
The present invention has one or more benefits.For example, different with the receiver that comprises the independent ADC that is used for each parallel signal, the invention provides the receiver that comprises the common ADC that is used for parallel signal.For the two-way ping-pong architecture, Simulation with I component and simulation Q component are multiplexed to common pipeline ADC.Thereby any mismatch in the pipeline components is common for I component and Q component, thereby, greatly eliminated many significant mismatch factors, comprise static mismatch factor and the time become the mismatch factor.Two S/H circuit can be placed adjacent one another on circuit board, minimizes further to make the I-Q mismatch.
In addition, receiver approximately can be saved 50% area, because eliminated extra ADC and relevant outer member.Thereby receiver can approximately reduce by 30～50% power consumption.In addition, because only needing local coupling, clock path need not control the clock skew between the independent ADC, so clock routing is simplified.
Receiver also can comprise closed loop calibration techniques involve, the gain before being used for proofreading and correct and the I-Q mismatch of filtering stage, and precision is improved, and correcting range is minimized.More specifically, because by common ADC the coupling of value I and Q component is increased, closed loop calibration techniques involve shows the improvement of precision and the reduction of correcting range.
The hereinafter with reference accompanying drawing is described details of the present invention and one or more embodiment.According to specification, accompanying drawing and claims, can know other features of the present invention, target and benefit.
Description of drawings
The block diagram of Fig. 1 illustrates example transmitter and the receiver in the wireless communication system.
The block diagram of Fig. 2 illustrates 2 * 1 reciprocal modulus of conversion number converters (ADC) of receiver.
Fig. 3 illustrates the back and forth timing waveform of conversion ADC of pipeline-type 2 * 1.
The block diagram of Fig. 4 illustrates the one-level of 2 * 1 reciprocal conversion ADC.
The block diagram of Fig. 5 illustrates 4 * 1 and back and forth changes ADC.
Fig. 6 illustrates the timing waveform of 4 * 1 reciprocal conversion ADC.
The block diagram of Fig. 7 illustrates 4 * 1 reciprocal conversion ADC with reciprocal switching network.
The block diagram of Fig. 8 illustrates to have and is embedded in more 2 * 1 reciprocal conversion ADC of the multiplex circuit of depths of ADC.
The flow chart of Fig. 9 illustrates the exemplary operations of the receiver that comprises reciprocal conversion ADC.
Embodiment
Usually, the present invention relates to be used for the receiver of wireless communication system.This receiver greatly reduces or has eliminated homophase (I) component of the wireless signal that receives and mismatch between quadrature (Q) component.This is by sharing between Simulation with I component and Q component or " back and forth conversion " analog to digital converter realization.By between I component and Q component, sharing pipelined ad C,, thereby eliminated many significant I-Q mismatches source by same processing of circuit I component and the Q component among the pipelined ad C.Like this, can reduce greatly performance is produced dysgenic I component and Q component mismatch.Simultaneously, system complexity and cost are also reduced, because receiver is not to use ADC separately to handle I component and Q component, and are to use an ADC to handle I component and Q component.
To utilize two parallel routes to convert Simulation with I component and Q component to digital I component different with Q component with ADC that common use separates, and the disclosure has been described and comprised the Simulation with I component is converted to digital I component and will simulate the receiver that Q component converts the common ADC of digital Q component to.Because by same processing of circuit I component and the Q component in the common ADC, so I component and the same undesirable situation of Q component experience.Thereby the digital I component and the mismatch between the Q component that are produced by common ADC can greatly be reduced or be eliminated.
In the work, receive wireless signal with antenna, amplify, convert lower frequency to, filtering is transformed into numeric field then with further processing and filtering.With the wireless signal conversion that receives or when being down-converted to lower frequency, RX path is divided into two parallel routes.Particularly, can use the quadrature frequency conversion conversion that signal is carried out down-conversion, conversion of signals is become the I component and the Q component of received signal.
For example, receiver comprises data converter, and the signal from analog territory that is used for receiving is transformed into numeric field, to carry out digital processing and demodulation.Data converter comprises first and second samplings and keeps (S/H) circuit, multiplexer, common ADC.The first and second S/H circuit are distinguished sampled I channel and Q channel simultaneously, and can be placed adjacent one another on circuit board, to reduce the mismatch between the S/H circuit.Particular moment, multiplexer is applied to common ADC with an output of S/H circuit,, on the basis of time interleaving, applies the output of S/H circuit that is.The reciprocal conversion of ADC between I component and Q component realizes by the operation of multiplexer like this, jointly.Common ADC comprises pipelined ad C, and it comprises a plurality of identical levels, and each level is carried out same operation.Because pipelined ad C handles I component and Q component, so the frequency of operation of pipelined ad C is the twice of S/H circuit and multiplexer frequency of operation.Yet, the I-Q mismatch is able to remarkable reduction, because with same processing of circuit I component and Q component on the common ADC, and, about 50% area be can save, another required extra ADC of common receiver and the outer member relevant used with extra ADC because eliminated.
Except reducing the I-Q mismatch greatly, the present invention can also the simplifier clock wiring.Particularly, because only needing local coupling, clock path need not control the clock skew between the independent ADC, so clock routing is simplified.Because eliminated extra ADC and relevant outer member, can also approximately reduce by 30～50% analog power consumption.Like this, the present invention has improved systematic function, has reduced system complexity, cost, power consumption and die area simultaneously.
The present invention can also expand to four road ping-pong architectures and the ping-pong architecture of high-order more.For four road ping-pong architectures, compare with the receiver that comprises four independent parallel ADC, the present invention saves about 75% area.The present invention can expand to higher stage structure, for example 8 the tunnel back and forth changes, 12 tunnel back and forth conversions etc.
Among some embodiment, can before ping-pong architecture, comprise handover network, to eliminate the mismatch effects of bringing owing to the mismatch of S/H circuit.For four road ping-pong architectures, handover network can by turns by which input signal of S/H circuit sampling.Handover network can be rotated input signal according to the STOCHASTIC CONTROL order.Like this, the output demodulation multiplexer is used same random sequence, to separate single signal flow.
In other embodiments, can calculate the highest significant position (MSB) of received signal with parallel signal path, and can calculate least significant bit (LSB) by being multiplexed into a streamline.In this case, first and second ADC that Simulation with I and Q component can be fed respectively calculate MSB simultaneously.The output of first and second ADC can be multiplexed into the common ADC that calculates LSB.Like this, can realize multiplexer in company with pipelined ad C according to the requirement of receiver.
Although describe the present invention with reference to wireless receiver in the disclosure, the present invention can be used for the good sampling ADC of needs coupling usually and uses with any receiver in digitlization panel data path.Can make up the restriction of the clock frequency of the pipelined ad C that the channel quantity of (promptly multiplexing) only shared.
The block diagram of Fig. 1 illustrates wireless communication system (10), and it reduces greatly or has eliminated homophase (I) component of the wireless signal that receives and mismatch between quadrature (Q) component.The reduction of mismatch is by sharing between two parallel signal paths or " back and forth conversion " analog to digital converter (ADC) realization.Though the present invention can be used for any application of the good sampling ADC of needs coupling with digitlization panel data path usually, the disclosure is described the present invention is used for wireless communication system, particularly the receiver that uses in the wireless communication system.
Particularly, amplifier 12 amplifies the loss of signal of the signal of reception with compensate for channel 4.The frequency lower than the frequency of received signal changed or be down-converted to local oscillator 14 with the output of amplifier 12.For example, local oscillator 14 can comprise the quadrature tunable oscillator of being transferred to fixed intermediate frequency or base band frequency.Thereby when frequency inverted (being quadrature frequency conversion), the signal of reception is divided into two parallel routes, the i.e. I component of the wireless signal of Jie Shouing and Q component.
Gain between I component and the Q component and phase mismatch are called the I-Q mismatch.The I-Q mismatch has a negative impact to the performance of system 10, particularly, influences receiver 6.Receiver structure is depended in the influence of I-Q mismatch usually, for example heterodyne receiver, homodyne radio receiver or image cancellation receiver.Receiver 6 can be realized with heterodyne receiver, homodyne radio receiver or image cancellation receiver.Usually, image signal elimination system and homodyne system are more responsive than heterodyne system.In any case, the I-Q mismatch makes that all when numeric field reconfigured channel, image frequency can not be offset fully.The incomplete counteracting of image frequency has reduced the signal to noise ratio (snr) of desired frequency band, thereby causes the suboptimum receptivity.
The source of mismatch has multiple between channel I and the Q.For example, the gain of local oscillator 14 and phase mismatch have been contributed mismatch term.Each level in two parallel signal paths among filter 16 and channel I and the Q all has contribution to the I-Q mismatch.Some I-Q mismatch sources are static, and other mismatch sources then can change in time, thereby feasible tracking and compensation mismatch are more difficult.For example, may be difficult to especially compensate the mismatch that is caused by ADC, wherein reference voltage mismatch changes with working temperature.
Different with the common wireless receiver of handling I channel and Q channel simultaneously with two parallel coupling good signal paths, receiver 6 is shared an ADC between I component and Q component.By between I component and Q component, sharing or back and forth changing ADC, greatly reduce or eliminated the I-Q mismatch.For the benefit of receiver 6 particularly of representation system 10 clearly, the operation to the typical radio receiver is described below, describes the operation of wireless receiver 6 subsequently.
Typical wireless receiver uses usually and comprises that the data converter of pipelined ad C carries out analog-to-digital conversion, because pipelined ad C can high speed operation, lower and other high-speed structures ratios of power consumption occupy less area simultaneously.Particularly, data converter generally includes sampling and keeps (S/H) circuit, pipelined ad C, timing controller.During operation, analog input is applied to the S/H circuit.Sampling clock driving timing controller, the timing of timing controller control sampling rate and S/H circuit.The output of S/H circuit is applied to pipelined ad C.Pipelined ad C comprises a plurality of identical utmost points, and each utmost point is carried out identical operations.The one-level of pipelined ad C comprises ADC, DAC, error summation circuit and amplifier.Usually, the first order of pipelined ad C receives and is applied to ADC and error summation circuit from the analog sampling of S/H circuit and with input.ADC exports k digit order number, and DAC converts digital output bit to the analog signal of conversion once more, to be applied to error summation circuit.The analog signal that error summation circuit will be changed once more deducts from the crude sampling analog signal, and to produce error signal, this error signal is applied to amplifier.The output of the next stage reception amplifier of simulation ADC is as input.
Because the signal that receives is converted into I component and Q component in converting the downconversion process of lower frequency to, needing independently, ADC comes each component of digitlization.Particularly, in order to handle I component and Q component simultaneously, typical receiver utilizes two parallel, coupling good signal paths.Each signal path comprises filter, comprises the data converter of pipelined ad C, DSP and demodulator circuit.Like this, when numeric field reconfigured two components, typical wireless receiver balanced out the byproduct that occurs of not wishing that frequency down-converts produced.Yet the effect of this counteracting structure is subjected to the I-Q mismatch quantitative limitation of two parallel signal paths essentially.In other words, there is the mismatch that each grade by frequency down-converts, filter and pipelined ad C brings in typical wireless receiver.
For example, mating two independently data converters, is problematic for two pipelined ad C of coupling particularly.This is because each data converter comprises complete system, it typically is an independent circuit block.Like this, need the sensitive analog piece that mates in the data converter, for example S/H circuit and amplifier usually can not placed adjacent.By two data transducers physically being staggeredly placed and the sensitive blocks placed adjacent having been eliminated mismatch between the data converter in fact.Yet physically staggered two data transducers have increased about twice or bigger with Butut and wiring complexity.
The other technologies of improving the I-Q mismatch of two independent data converters require to use bigger device area that device mismatch is minimized.Yet, consider desired high speed operation, it is infeasible using bigger device area in a path of data converter.
Can not utilize under the situation of bigger device area, can use closed loop calibration techniques involve to measure and compensate two gain and phase mismatch terms between the independent data converters.Yet this closed loop calibration techniques involve has increased complexity and control.In addition, most of closed loop calibration techniques involve has limited calibration range, only just is activated at idle mode usually.Like this, any variation of the operating point between the idle and normal mode does not all obtain calibration at data converter.
Different with common wireless receiver, receiver 6 is shared data transducers, particularly, shares an ADC between the I component of received signal and Q component.By between I component and Q component, sharing an ADC, by the same circuit in the data converter I component and Q component are handled, thereby eliminated many limiting factors of I-Q mismatch.Like this, wireless receiver can improve systematic function, reduces the outer member of system complexity, cost, power consumption and receiver 6 simultaneously.Yet these improve to require simulation pipeline ADCs and digital error correction circuit to double the S/H circuit in the data converter and the speed operation of multiplexer.
For example, the present invention can connect up by simplifier clock, need not to control two skews between the independent data converters because clock path only needs local coupling.In addition, it is about 50% that the present invention can reduce area, because receiver 6 comprises independently ADC of an ADC rather than two.Also eliminated and the extra relevant outer member of ADC.Among some embodiment, it is about 30～50% that receiver 6 can reduce analog power consumption, and this is because eliminated extra ADC and relevant outer member.
In addition, because the corporate data transducer has increased the I-Q coupling, among some embodiment, digital I component and Q component that the corporate data transducer produces can be used for the mismatch term of measured signal path middle and upper reaches more accurately.Like this, being used to of being realized before proofreading and correct filtering and the precision of the closed-loop corrected technology of the I-Q mismatch of gain stage can improve, and reduce correcting range.
The block diagram of Fig. 2 illustrates the data converter 30 with 2 * 1 ping-pong architectures.Data converter 30 can be similar to data converter 18, is applicable to that receiver 6 converts numeral output I and numeral output Q respectively to Simulation with I component and simulation Q component with received signal.Particularly, because data converter 30 treatment of simulated I components and simulation Q component, so can significantly reduce or eliminate the I component of numeral output and the I-Q mismatch of Q component.Fig. 3 shows the time waveform of data converter 30.
As shown in Figure 2, data converter 30 comprises reference voltage and bias voltage generator 32, S/ H circuit 34A and 34B (being referred to as S/H circuit 34), multiplexer (MUX) 36, pipelined ad C 38, digital error correction circuit 50, breech lock and demodulation multiplexer (DEMUX) circuit 42, timing controller 44.Reference voltage and bias voltage generator 32 apply reference voltage and bias voltage to S/H circuit 34 and pipelined ad C 38.Under the control of timing controller 44, apply Simulation with I component and simulation Q component to S/ H circuit 34A and 34B respectively.S/ H circuit 34A and 34B sample to Simulation with I component and simulation Q component simultaneously.By while sampled I component and Q component, make that the mismatch between the sampling minimizes.In order to reduce mismatch, can be with S/H circuit placed adjacent on circuit board.
At given time, MUX 36 optionally is applied to pipelined ad C with an output of S/H circuit, that is, and and on the basis of time interleaving.For example, a specific clock cycle, the output that MUX 36 can S/H 34A is applied to pipelined ad C 38, in the next clock cycle, the output of S/H 34B is applied to pipelined ad C 38.Usually, MUX36 alternately applies the output of S/H circuit in each clock cycle.Yet, the invention is not restricted to 2 * 1 ping-pong architectures.On the contrary, can make up or multiplexing channel quantity only is subjected to the restriction of the clock speed of pipelined ad C 38.Thereby, among some embodiment, can carry similar ping-pong architectures such as 4 * 1,8 * 1.For example, Fig. 5 and Fig. 6 show two different 4 * 1 ping-pong architectures of the data converter that can be used for receiver 6.
As previously mentioned, because between Simulation with I component and simulation Q component, share pipelined ad C 38, so because the undesirable situation that the element of each same stages in the pipelined ad C 38 causes is identical for the I channel with the Q channel.This comprise static and the time become undesirable situation.Particularly, I channel and Q channel all experience the identical undesirable situation that the temperature change by pipelined ad C 38 causes.Because I channel and Q Channel Sharing pipelined ad C, so the service speed of pipelined ad C 38 is the twice of the service speed of S/H circuit and MUX 36.Thereby the timing controller 44 shown in Fig. 2 is to double the speed drive pipelined ad C 38 of S/H circuit 34 and MUX 36.
Digital error correction circuit 40 applies error correction techniques to the output of pipelined ad C 38.For example, error correction techniques can be eliminated the undesirable situation that is caused by radio communication channel 4, for example multipath interference, intersymbol interference and decline.The service speed of digital error correction circuit also approximately doubles S/H circuit 34 and MUX 36.
DEMUX and latches block 42 outputs correspond respectively to the digital signal I and the digital signal Q of Simulation with I component and simulation Q component.Particularly, the DEMUX of piece 42 part is carried out demultiplexing to the output of digital error correction 40 circuit.Thereby the operation of the DEMUX of piece 42 is opposite with the operation of MUX 36.The latch portion of piece 42 is exported digital signal I and digital signal Q simultaneously.The operating rate of DEMUX and latches block 42 is identical with MUX 36 with S/H circuit 34.Like this, digital signal I and Q mate in fact well, can reconfigure at numeric field.Signal after reconfiguring can further be handled, and finally carries out demodulation.Because can reduce the mismatch between digital output signal I and the Q greatly, the performance of receiver 6 can improve greatly, because can eliminate image frequency more completely from the signal that receives.
Fig. 3 shows the example timing waveform of data converter 30.Timing waveform 50 illustrates the sampling clock that timing controller 44 applies to pipelined ad C 38 and digital error correction circuit 40.Timing waveform 51 illustrates the sampling clock that timing controller 44 applies to S/H circuit 34, MUX 36 and DEMUX and latches block 42.As previously mentioned, for each clock cycle of timing waveform 51, timing waveform 50 comprises about two clock cycle.Timing waveform 52 illustrates the waveform that timing controller 44 imposes on MUX 36 and DEMUX and latches block 42.
Timing waveform 53 and 54 illustrate respectively S/ H circuit 34A and 34B output.Timing waveform 53 and 54 each trailing edge along with clock cycle of timing waveform 51 change.Timing waveform 55 illustrates the output of the initial level of pipelined ad C 38.Timing waveform 55 changes with each rising edge of the clock cycle of sequential waveform 50.
Timing waveform 56 and 57 illustrates the digital output signal I and the Q of DEMUX and latches block 42 respectively.Timing waveform 56 and 57 changes simultaneously, and promptly each trailing edge corresponding to clock cycle of timing waveform 52 changes.Because MUX 36, pipelined ad C 38 and digital error correction circuit 40 need the output of three clock cycle treatment S/H circuit 34, so up to the 3rd clock cycle of timing waveform 52, timing waveform 56 and 57 just comprises sampling.
The block diagram of Fig. 4 illustrates the initial level of pipelined ad C 38.Usually, pipelined ad C 38 comprises a plurality of identical levels, and each grade carried out same operation.As directed example, the initial level of pipelined ad C 38 comprise ADC 60, DAC 62, error summation circuit 64 and amplifier 66.DAC 62, error summation circuit 64 and amplifier 66 can be realized with a circuit block.This piece is commonly referred to multiplication DAC or MDAC 68.
Because Fig. 4 shows the initial level of pipelined ad C 38, MUX 36 is with input signal, and promptly one of Simulation with I component and simulation Q component are applied to ADC 60 and error summation circuit.K digit order number of ADC 60 outputs is to digital error correction circuit 40, and wherein k is a positive integer.DAC 62 converts k digit order number the analog signal of conversion once more to and this analog signal of changing once more is applied to error summation circuit 64.The analog signal that error summation circuit 64 will be changed once more deducts from original sampled signal (being the output of MUX 36), to produce error signal.66 pairs of error signals of amplifier are amplified, and export the next stage of pipelined ad C 38 to.In other words, the output of the amplifier of other grades reception previous stage in the initial level downstream shown in being positioned at is as input.The output of the amplifier of afterbody can abandon.Perhaps, the afterbody of pipelined ad C 38 can include only ADC.
The block diagram of Fig. 5 illustrates the data converter 70 with 4 * 1 ping-pong architectures, wherein handles two varying input signals that comprise two couples of I and Q component by common ADC.Data converter 60 converts digital signal corresponding applicable to receiver to the signal (for example, two signals that different antennae receives) with two receptions.In showing example, the signal of each reception is converted into Simulation with I component and simulation Q component, obtains four analog signals and is input to data converter 70.Two different received signals are by the channel logo that receives signal, that is, and and channel A and channel B.Thereby channel A goes up the Simulation with I component and the simulation Q component of the signal that receives and uses analogue component IA and QA sign respectively.Similarly, channel B goes up the Simulation with I component of the signal that receives and simulates Q component respectively with analogue component IB and QB sign.
As shown in Figure 5, data converter 70 comprises reference voltage and bias voltage generator 72, S/H circuit 74A-74B (being referred to as S/H circuit 74), MUX76, pipelined ad C78, digital error correction circuit 80, DEMUX and latch circuit 82 and timing controller 84.Reference voltage and bias voltage generator 72 apply reference voltage and bias voltage to S/H circuit 74 and pipelined ad C 78.
Apply Simulation with I A component, simulation QA component, Simulation with I B component and simulation QB component to S/H circuit 74A-74D respectively.S/H circuit 74 is sampled to corresponding input simultaneously.Similar with S/H circuit 34, S/H circuit 74 can placed adjacent on circuit board, so that the mismatch minimum between the circuit.
At given time, MUX 76 optionally is applied to pipelined ad C 78 with an analogue component, that is, and and on the basis of time interleaving.For example, MUX 76 can select which analogue component is applied to pipelined ad C 78 according to control sequence.Usually, MUX 76 can apply analog input with any order with analog input, as long as per four clock cycle input to pipelined ad C 78 with each analogue component.Importantly, the DEMUX of DEMUX and latches block 82 partly is the reverse operating of MUX 76.
Among some embodiment, the data converter with 4 * 1 ping-pong architectures can comprise handover network and S/H circuit rather than four S/H circuit and MUX.Among this embodiment, handover network is rotated the S/H circuit with four inputs of sampling in turn.Another factor of I-Q mismatch of having used a S/H circuit for eliminating.Fig. 7 shows the data converter that uses a S/H circuit and handover network.
For Fig. 5, between analogue component IA, IB, QA and QB, share pipelined ad C78.Yet, as previously mentioned, can be similar to pipelined ad C 38 structure pipelined ad C 78.In other words, pipelined ad C 78 comprises multistage, and each level is carried out identical operations.Yet different with pipelined ad C 38, the service speed of pipelined ad C 78 is approximately four times of service speed of S/H circuit 74 and MUX 76.
The mode of operation of digital error correction circuit 80 is similar to the digital error correction circuit 40 of data converter 30, but service speed is approximately identical with pipelined ad C 78.In other words, digital error correction circuit 80 applies error correction techniques to proofread and correct the undesirable situation in the signal that receives to the output of pipelined ad C 78.
The DEMUX part of DEMUX and latches block 82 is carried out demultiplexing to the output of digital error correction circuit 80.The operation of DEMUX is opposite with the operation of MUX 76.The latch portion output of piece 42 corresponds respectively to output digital signal IA, IB, QA and the QB of analogue component IA, IB, QA and QB.Particularly, breech lock can be exported all digital signals simultaneously, can reconfigure digital signal IA and QA and digital signal IB and QB at numeric field like this.The speed of DEMUX and latches block 82 operations is approximately identical with the speed of MUX 76, that is, operate with the clock rate of twice, with to the digital signal release of an interleave.Behind the digital signal release of an interleave, the service speed of DEMUX and latches block 82 is identical with the service speed of S/H circuit 74, promptly operates with one times clock rate, to aim at digital signal again.
As shown in Figure 5, timing controller 84 applies suitable timing waveform to S/H circuit 74, MUX 76, pipelined ad C 78, digital error correction circuit 80 and DEMUX and latches block 82.(unshowned) sampling clock can driving timing controller 84.Usually, the present invention is not subjected to the restriction of input channel quantity.On the contrary, the present invention only is subjected to the restriction of pipelined ad C clock rate.In other words,, also must correspondingly increase the quantity of S/H circuit along with channel quantity increases, that is, as long as chip area is unrestricted.Yet along with channel quantity increases, the exercisable speed of pipelined ad C can become limited.
Fig. 6 shows the timing waveform of data converter 70.Timing waveform 90 illustrates the sampling clock that timing controller 84 applies to pipelined ad C 78 and digital error correction circuit 80.Timing waveform 91 illustrates the sampling clock that timing controller 84 applies to S/H circuit 74, MUX 76 and DEMUX and latches block 72.The clock rate of timing waveform 90 is approximately four times of clock rate of timing waveform 91.Timing waveform 92 illustrates the output of the S/H circuit of being selected by MUX 76 74.As shown in Figure 6, MUX 76 is according to the output of following selective sequential S/H circuit 74: S/H 74A, S/H 74B, S/H 74C, S/H 74D.MUX 76 selects the output of S/H circuit 74 corresponding to the rising edge of each clock cycle of timing waveform 90.
Timing waveform 93～96 illustrates the output of S/H circuit 74A-74D respectively.Timing waveform 93～96 illustrates S/H circuit 74A-74D and simultaneously their corresponding input is sampled.Particularly, timing waveform 93～96 is along with each trailing edge of the clock cycle of timing waveform 91 changes its value.
Timing waveform 97 illustrates the sampling of the input of pipelined ad C 78.As shown, because MUX 76 exports its current sampling through a clock cycle after receiving sampling, so the delay of a clock cycle is arranged between timing waveform 92 and 97.
The block diagram of Fig. 7 illustrates another transducer with 4 * 1 ping-pong architectures 100.Data converter 100 comprises handover network 106, S/H circuit 104, reference voltage and bias voltage generator 102, pipelined ad C 108, digital error correction circuit 110, DEMUX and latches block 112 and timing controller 114.As shown in Figure 7, data converter 100 is applicable to receiver 6, converts two digital signal corresponding to the signal (as the signal of two different antennae receptions) with two receptions.The analog signal component of Fig. 7 sign is identical with Fig. 5.Yet, different with the data converter 70 of Fig. 5, analogue component IA, QA, IB and QB are applied to handover network 106.Handover network 106 is selected which analogue component of S/H circuit sampling.Handover network 106 can be selected analogue component according to control sequence.Among some embodiment, control sequence can be with each analogue component of certain model selection.This pattern can be carried out repetition to certain clock cycle, with each analogue component of even selection.For example, per four clock cycle, control sequence can be selected analogue component: IA, QA, IB, QB by following order.In alternate embodiment, control sequence can be selected analogue component at random.In any case, the operation of the DEMUX of piece 112 part is the inverse operation of handover network 106.
Like this, the input that applies in the sampling of clock cycle of S/H circuit 104 and in next clock cycle output sampling.By removing a plurality of S/H circuit, data converter 100 is eliminated the I-Q mismatch that is caused by a plurality of S/H circuit effectively.Like this, for the receiver with a large amount of receivers footpath or channel, the design of data converter 100 is useful especially.
S/H circuit 104 is applied to pipelined ad C 108 with its output.The working method of the working method of pipelined ad C108, digital error correction circuit 110, DEMUX and latches block 112, reference voltage and bias voltage generator 102 and the pipelined ad C 78 of Fig. 5, digital error correction circuit 80, DEMUX and latches block 82 and reference voltage and bias voltage generator 72 is similar.Four times of the clock cycle that the clock cycle that timing controller 114 provides for pipelined ad C 108 and digital error correction circuit 110, approximately to be timing controller 114 provided to handover network 106 and S/H circuit 104.Same, can come driving timing controller 114 with the sampling clock (not shown).
With use four independently Parallel ADC come the typical receiver of the component of treatment of simulated input simultaneously IA, QA, IB, QB to compare, data converter 100 can be saved about 75% area, and this is because pipelined ad C 108 is included in an ADC who shares between the analogue component input.Yet, the invention is not restricted to 4 input channels.On the contrary, the present invention can expand to the channel of greater number, for example, and 8,10 and 12 channels.As previously mentioned, during operation, the present invention only is subjected to the restriction of the clock rate of fast pipeline type ADC 108.
The block diagram of Fig. 8 illustrates the data converter 120 that is applicable to receiver 6, and its application for the clock rate of having relatively high expectations is useful especially.Usually, data converter 120 usefulness parallel signal paths calculate the highest significant position (MSB) of received signal, and calculate least significant bit (LSB) by back and forth change a pipeline ADC between parallel signal path.In other words, data converter 120 can be considered as reciprocal switch process is moved into the more depths of pipelined ad C.In higher sampling rate, back and forth conversion pipelined ad C may make that the output of ping-pong architecture is unreliable between input.By using parallel signal path to calculate MSB, can calculate MSB reliably.By contrast, calculate the error that LSB may cause bigger quantity by between input, back and forth changing pipelined ad C.Yet some can accept the Errors Catastrophic among the LSB, especially in the time can saving bigger chip area in using.Thereby data converter 120 provides trading off between performance and system complexity, cost and the power consumption.
In the example shown, data converter 120 comprises reference voltage and bias voltage generator 122, S/H circuit 124A and 124B (being referred to as S/H circuit 124), pipelined ad C126, pipelined ad C 128, multiplexer 130, pipelined ad C 132, digital error correction circuit 134, DEMUX and latches block 136, timing controller 138 and controller 140.S/H circuit 124A and 124B sample respectively the Simulation with I component and the simulation Q component of the signal that receives.The sampling rate and the timing of clock controller 138 control S/H circuit 124.The output of S/H circuit 124A is applied to pipelined ad C 126, and the output of S/H circuit 124B is applied to pipelined ad C 128.As preceding at Fig. 1 at as described in the typical pipelined ad C, pipelined ad C 126 with 128 each comprise a plurality of identical levels, each level is carried out same operation.Like this, the front end of data converter 120 uses two good independent ADC of coupling to handle parallel signal path simultaneously.Thereby pipelined ad C 126 and 128 generates and can reconfigure, handles digital output bit I and the Q of also demodulation with the MSB of the signal of calculating reception.In order to illustrate, only show the output of pipelined ad C 126 and 128.But the circuit that pipelined ad C 126 and 128 output can be applied to other is to reconfigure, to handle and the signal of demodulate reception.
Except using two good parallel signal paths of coupling to calculate the MSB of the wireless signal that receives, data converter is by back and forth changing the LSB that pipelined ad C 132 calculates the signal of reception between Simulation with I and Q component.At first, data converter 120 determine when apply S/H circuit 124 export MUX 130 to.In the example that illustrates, controller 140 determine when apply S/H circuit 124 export MUX 130 to, rather than pipelined ad C 126 and 128 determines.For example, control 130 can comprise timer, and this timer triggers controller 140 after the clock cycle of predetermined number.
In any case, calculated after the MSB, the output of S/H circuit 124 has been applied to MUX 130.At given time, MUX 130 optionally is applied to pipelined ad C 132 with one of analog input component.The working method of pipelined ad C 132 can be similar with pipelined ad C 38.For Fig. 8, the operating rate of pipelined ad C 132 is the twice of position S/H circuit 124, pipelined ad C 126 and 128, MUX 130 and DEMUX and latches block 136 approximately.The operation of digital error correction circuit 134 can be similar to the operation of the digital error correction circuit 40 of Fig. 1.The output of DEMUX and 138 couples of pipeline-type ADC132 of latches block applies the digital error correction technology, and its class of operation is similar to the digital error correction circuit 40 of Fig. 1.DEMUX and latches block 138 generates output bit I and the Q of the LSB of the signal that can be used to calculate reception.
Timing controller 138 provides timing waveform to S/H circuit 124, pipelined ad C 126,128 and 132, MUX 130, digital error correction circuit 134 and DEMUX and latches block 136.Usually, the service speed of pipelined ad C 132 and digital error correction circuit 134 approximately is the twice of the service speed of S/H circuit 124, pipelined ad C 126 and 128, MUX 130 and DEMUX and latches block 136.
The flow chart of Fig. 9 illustrates the exemplary operations that is used for reducing greatly and eliminates the receiver of the I component of the wireless signal that receives and the mismatch between the Q component.In order to illustrate, the flow chart shown in Fig. 9 is to be described at the example structure shown in Fig. 2 (that is, data converter 30).At first, transmitter uses wireless-modulated technology emission wireless signal, as PSK, BPSK, QPSK, FSK and MSK.Receiver 6 receives wireless signal (150) and the conversion of signals that receives is become Simulation with I component and simulation Q component (152) by radio communication channel.For example, receiver 6 can use local oscillator that the signal that receives is down-converted to lower frequency.In downconversion process, wireless signal is converted into Simulation with I component and Q component.At this point, determine gain and phase mismatch (being I-Q) mismatch between Simulation with I component and the Q component by local oscillator.The I-Q mismatch depends on receiver structure to the influence of receiver 6, for example heterodyne receiver, homodyne radio receiver or image cancellation receiver.In any case, when numeric field reconfigured I component and Q component, the I-Q mismatch caused the incomplete counteracting of image frequency, thereby reduced the SNR of desired channel and cause the suboptimum receiver performance.
In order to reduce the I component of the signal that receives and the I-Q mismatch between the Q component greatly, receiver 6 comprises data converter 30, and data converter 30 converts Simulation with I component and Q component to corresponding digital I component and Q component.The digital I component of data converter 30 outputs and the I-Q mismatch in the Q component are eliminated greatly.Data converter 30 by to received signal Simulation with I component and Q component sample simultaneously (152) realize this effect.Particularly, timing controller 44 applies identical clock signal to S/H circuit 34A with 34B, so that 6 while of receiver sampled I component and Q component.S/H circuit 34 can be placed adjacent one another with further reduction I-Q mismatch on circuit board.
As previously mentioned, pipelined ad C 38 converts Simulation with I component and Q component to corresponding digital I component and Q component (158).Because handle I component and Q component with same circuit (being pipelined ad C38), so the I-Q mismatch between digital I component and the Q component is reduced greatly or is eliminated, thereby eliminated the many remarkable factor of I-Q mismatch, in addition, when combined digital I component and Q component, offset any undesirable situation that causes by pipelined ad C 38.
Thereby, owing between I component and Q component, share a pipelined ad C rather than use parallel signal path to handle I component and Q component simultaneously,, reduced system complexity, cost, power consumption simultaneously so receiver 6 has improved performance.
Each embodiment of the present invention has been described.Although this specification has been described the present invention at wireless receiver, the present invention can be common to needs any application of the good ADC of coupling with the digitlization parallel data path.In addition, the present invention is not subjected to the channel limited in number.
Various nextport hardware component NextPort described herein can comprise one or more processors, for example, one or more microprocessors, digital signal processor (DSP), application-specific integrated circuit (ASIC) (ASIC), field programmable gate array (FPGA) or other programmable logic circuit are perhaps used the combination of above assembly.
In addition, under the certain situation, these assemblies can be carried out the program command that is stored on the computer-readable medium, and this program command makes these assemblies carry out function as described herein.Thereby the form of some embodiment is the computer-readable medium that comprises instruction, and described instruction makes programmable processor carry out various function described herein.Computer-readable medium can be any electricity, magnetic or light medium, for example random-access memory (ram), read-only memory (ROM), CD-ROM, hard disc or floppy disc, electrically erasable ROM (EEPROM), flash memory etc.
Various embodiment of the present invention has been described.Yet, it should be appreciated by those skilled in the art, can carry out various modifications and increase to described embodiment and do not deviate from the present invention.These and other embodiment within the scope of the following claims.
Claims (38)
1. method comprises:
Received signal;
Described conversion of signals is become analog in-phase (I) component and simulation quadrature (Q) component;
Described Simulation with I component and Q component are applied to common analog to digital converter (ADC).
2. according to the process of claim 1 wherein that described signal is a wireless signal.
3. according to the method for claim 1, further comprise: convert described Simulation with I component to digital I component, and converting described simulation Q component to digital Q component, wherein said ADC converts described Simulation with I component and Q component to corresponding digital I component and Q component.
4. according to the process of claim 1 wherein that described ADC is pipelined ad C, it comprises a plurality of levels, and each level is carried out identical operations.
5. according to the method for claim 4, further comprise: in described each level, convert analog input to one or more digit order numbers, convert described digit order number to analog signal once more, described analog signal is deducted from described analog input to produce error signal, amplify described error signal, and the next stage that the error signal of described amplification is outputed to described ADC.
6. according to the method for claim 5, wherein said analog input comprises one of the error signal of described amplification of the previous stage of described Simulation with I component, described simulation Q component and described ADC.
7. apply described Simulation with I component and Q component comprises that multiplexing described Simulation with I component and Q component are to be applied to described ADC at given time with one of described Simulation with I component and Q component according to the process of claim 1 wherein.
8. according to the method for claim 1, wherein applying described Simulation with I component and Q component comprises: described Simulation with I component is applied to an ADC to convert described Simulation with I component to a plurality of highest significant positions (MSB), simultaneously described simulation Q component is applied to the 2nd ADC to convert described simulation Q component to a plurality of highest significant positions (MSB), and, the output of multiplexing described first and second ADC is to be applied to described common ADC at given time with one of described output, and wherein said common ADC produces the least significant bit of described Simulation with I component and Q component.
9. apply described Simulation with I component and Q component comprises according to the process of claim 1 wherein: sample simultaneously described Simulation with I component and Q component and on the basis of time interleaving, described Simulation with I component and Q component are applied to described common ADC.
10. use quadrature frequency conversion that described conversion of signals is become described Simulation with I component and Q component according to the process of claim 1 wherein that the described signal of conversion comprises, the frequency of the signal of the described reception of frequency ratio of described Simulation with I component and Q component is low.
11. according to the process of claim 1 wherein that receiving described signal comprises and amplifying and the described signal of filtering and described digital I component and Q component are applied to closed loop calibration techniques involve amplify and I-Q mismatch during the described signal of filtering to proofread and correct.
12. a communicator comprises:
Receiver is used for received signal;
Low-converter, it becomes analog in-phase (I) component and simulation quadrature (Q) component with described conversion of signals; And
Common analog to digital converter (ADC), it converts described Simulation with I component to digital I component, and converts described simulation Q component to digital Q component.
13. according to the device of claim 12, wherein said receiver is a wireless receiver, described signal is a wireless signal.
14. according to the device of claim 12, wherein said ADC is pipelined ad C, it comprises a plurality of levels, and each level is carried out identical operations.
15. according to the device of claim 12, wherein each level comprises: ADC is used for converting analog input to one or more digit order numbers; Digital to analog converter (DAC) is used for converting described digit order number to analog signal once more; Summation circuit is used for described analog signal is deducted to produce error signal from described analog input; And amplifier, be used to amplify described error signal, and the error signal of described amplification outputed to the next stage of described ADC.
16. according to the device of claim 15, wherein said analog input comprises one of the error signal of described amplification of the previous stage of described Simulation with I component, described simulation Q component and described ADC.
17. according to the device of claim 12, further comprise multiplexer, be used for one of described Simulation with I component and Q component being applied to described ADC at given time.
18. the device according to claim 12 further comprises: an ADC is used for converting described Simulation with I component to a plurality of highest significant positions (MSB); And the 2nd ADC, be used for converting described simulation Q component to a plurality of highest significant positions (MSB).
19. the device according to claim 12 further comprises:
The one ADC is used to produce the highest significant position (MSB) of described Simulation with I component;
The 2nd ADC is used for producing the MSB of described simulation Q component when a described ADC produces the MSB of described Simulation with I component; And
Multiplexer is used at given time one of described Simulation with I component and Q component being applied to described common ADC,
Wherein said common ADC produces the least significant bit (LSB) of described Simulation with I component and Q component.
20. the device according to claim 12 further comprises: first sampling and maintenance (S/H) circuit, described Simulation with I component is used to sample; The 2nd S/H circuit is used for the described simulation Q component of sampling in the described Simulation with I component of a described S/H circuit sampling.
21. according to the device of claim 20, the wherein said first and second S/H circuit are placed on circuit block adjacent to each other.
22. device according to claim 20, further comprise: timing controller, it controls the timing of the described first and second S/H circuit, multiplexer and common ADC, and the timing of wherein said common ADC approximately is the twice of the timing of described multiplexer and the described first and second S/H circuit.
23. according to the device of claim 12, wherein said low-converter uses quadrature frequency conversion that described conversion of signals is become Simulation with I component and Q component, the frequency of the signal of the described reception of frequency ratio of described Simulation with I component and Q component is low.
24. the device according to claim 12 further comprises:
Amplifier is used to amplify the signal of described reception; And
Filter is used for the image frequency of filtering frequency down-converts gained and exports described Simulation with I component and Q component.
25. according to the device of claim 22, further comprise closed loop circuit, be used to proofread and correct the I-Q mismatch of described amplifier and described filter.
26. a method comprises:
Receive first signal;
Receive secondary signal
Described first conversion of signals is become first analog in-phase (I) component and first simulation quadrature (Q) component;
Convert described secondary signal to second analog in-phase (I) component and second simulation quadrature (Q) component; And
The described first Simulation with I component and Q component and the described second Simulation with I component and Q component are applied to common analog to digital converter (ADC).
27. according to the method for claim 26, wherein said first and second signals are wireless signals.
28. method according to claim 26, further comprise: convert the described first and second Simulation with I components to corresponding first and second digital I components, convert the described first and second simulation Q components to corresponding first and second digital Q components, wherein said ADC converts described first and second Simulation with I components and described first and second Q components to corresponding first and second digital I component and Q components.
29. according to the method for claim 26, wherein said ADC is pipelined ad C, it comprises a plurality of levels, and each level is carried out identical operations.
30. method according to claim 29, wherein each level comprises: convert analog input to one or more digit order numbers, convert described digit order number to analog signal once more, described analog signal is deducted from described analog input to produce error signal, amplify described error signal, and the next stage that the error signal of described amplification is outputed to described ADC.
31. according to the method for claim 30, wherein said analog input comprises one of the error signal of described amplification of the previous stage of the described first Simulation with I component, the described second Simulation with I component, the described first simulation Q component, the described second simulation Q component and described ADC.
32., wherein apply described first and second Simulation with I components and Q component and comprise that multiplexing described first and second Simulation with I components and Q component are to be applied to described ADC at given time with one of the described first and second Simulation with I components and Q component according to the method for claim 26.
33., wherein apply described first and second Simulation with I components and Q component and comprise: sample simultaneously described first and second Simulation with I components and Q component and on the basis of time interleaving, described first and second Simulation with I components and Q component are applied to described common ADC according to the method for claim 26.
34., wherein apply described first and second Simulation with I components and Q component and be included in given time and select one of the described first and second Simulation with I components and Q component to sample, and described sampling is applied to described common ADC according to the method for claim 26.
35., wherein select one of the described first and second Simulation with I components and Q component to comprise and select one of the described first and second Simulation with I components and Q component according to predefined procedure according to the method for claim 34.
36., wherein select one of the described first and second Simulation with I components and Q component to comprise and select one of the described first and second Simulation with I components and Q component at random according to the method for claim 34.
37. a device comprises:
Receiver, it receives first signal and secondary signal;
Low-converter, it becomes first analog in-phase (I) component and first simulation quadrature (Q) component with described first conversion of signals, and converts described secondary signal to the second Simulation with I component and the second simulation Q component; And
Common analog to digital converter (ADC), it converts the described first and second Simulation with I components to corresponding first and second digital I components, and converts the described first and second simulation Q components to corresponding first and second digital Q components.
38. according to the device of claim 37, wherein said receiver is a wireless receiver, described signal is a wireless signal.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US69596805P | 2005-07-01 | 2005-07-01 | |
| US60/695,968 | 2005-07-01 | ||
| US11/390,991 | 2006-03-28 |
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| Publication Number | Publication Date |
|---|---|
| CN101213737A true CN101213737A (en) | 2008-07-02 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2006800240140A Pending CN101213737A (en) | 2005-07-01 | 2006-06-27 | Analog to digital converter with ping-pong architecture |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103053114A (en) * | 2010-08-25 | 2013-04-17 | 德克萨斯仪器股份有限公司 | Power and area efficient interleaved ADC |
| CN103905047A (en) * | 2014-03-04 | 2014-07-02 | 东莞博用电子科技有限公司 | Circuit system topological structure and method for increasing sampling rate of ADC |
| CN103997342A (en) * | 2012-07-02 | 2014-08-20 | 英飞凌科技股份有限公司 | Analog-digital-wandlung mit abtast-halte-schaltungen |
| CN107040259A (en) * | 2015-11-24 | 2017-08-11 | 恩智浦有限公司 | Data processor |
| CN107342781A (en) * | 2016-04-28 | 2017-11-10 | 恩智浦有限公司 | Acceptor circuit |
| CN108809294A (en) * | 2018-08-30 | 2018-11-13 | 北京神经元网络技术有限公司 | A kind of dynamic cell match circuit |
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2006
- 2006-06-27 CN CNA2006800240140A patent/CN101213737A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103053114A (en) * | 2010-08-25 | 2013-04-17 | 德克萨斯仪器股份有限公司 | Power and area efficient interleaved ADC |
| CN103997342A (en) * | 2012-07-02 | 2014-08-20 | 英飞凌科技股份有限公司 | Analog-digital-wandlung mit abtast-halte-schaltungen |
| CN103905047A (en) * | 2014-03-04 | 2014-07-02 | 东莞博用电子科技有限公司 | Circuit system topological structure and method for increasing sampling rate of ADC |
| CN107040259A (en) * | 2015-11-24 | 2017-08-11 | 恩智浦有限公司 | Data processor |
| CN107342781A (en) * | 2016-04-28 | 2017-11-10 | 恩智浦有限公司 | Acceptor circuit |
| CN107342781B (en) * | 2016-04-28 | 2020-12-04 | 恩智浦有限公司 | Receiver circuit |
| CN108809294A (en) * | 2018-08-30 | 2018-11-13 | 北京神经元网络技术有限公司 | A kind of dynamic cell match circuit |
| CN108809294B (en) * | 2018-08-30 | 2023-11-14 | 北京神经元网络技术有限公司 | Dynamic unit matching circuit |
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Application publication date: 20080702 |